Preface. Any questions from last time? A bit more motivation, information about me. A bit more about this class. Later: Will review 1st 22 slides

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1 Preface Any questions from last time? Will review 1st 22 slides A bit more motivation, information about me Research ND A bit more about this class Microsoft Later: HW 1 Review session MD McNally about Lab 1 1

2 (1) Any questions from last time? Chapter 8: Programmable Processors Slides to accompany the textbook, First Edition, by, John Wiley and Sons Publishers, Copyright 2007 Instructors of courses requiring Vahid's textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities, subject to keeping Digital this copyright Design notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf with animations) may not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means. Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors 2 may obtain PowerPoint Frank source Vahid or obtain special use permissions from Wiley see for information.

3 Introduction 8.1 Programmable (general-purpose) processor Mass-produced, then programmed to implement different processing tasks Well-known common programmable processors: Pentium, Sparc, Power Lesser-known but still common: ARM, MIPS, 8051, PIC Low-cost embedded processors found in cell phones, blinking shoes, etc. Instructive to design a very simple programmable processor Seatbelt warning light single-purpose processor Real processors can be much more complex e x4 x(t) x(t-1) x(t-2) xt0 c0 xt1 c1 xt2 c2 + + reg 3-tap F filter single-purpose processor s i Seatbelt Note: 3-tap F filter warning light program 1st, a program simple processor, t a p 2nd, more complex, a Instruction then memory Pentium! I r t 0 Note: Slides with animation are denoted with a small red "a" near the animated items n o c o t g Other programs Register file RF Datapath General-purpose processor 3

4 Basic Architecture Processing generally consists of: Loading some data Transforming that data Storing that data Basic datapath: Useful circuit in a programmable processor Can read/write data memory, where main data exists Has register file to hold data locally Has to transform local data s i t a p a a r t n o c o t g 8.2 somehow connected to the outside world Compare to Slide15, Lecture 01. Datapath 4

5 Basic Datapath Operations Load operation: Load data from data memory to RF operation: Transforms data by passing one or two RF register values through, performing operation (ADD, SUB, AND, OR, etc.), and writing back into RF. Store operation: Stores RF register value back into data memory Each operation can be done in one clock cycle Understand idea of register file? Versus RAM? Load operation operation Store operation 5

6 Basic Datapath Operations Q: Which are valid single-cycle operations for given datapath? Move D[1] to RF[1] (i.e., RF[1] = D[1]) A: YES That's a load operation Store RF[1] to D[9] and store RF[2] to D[10] A: NO Requires two separate store operations Add D[0] plus D[1], store result in D[9] A: NO operation (ADD) only works with RF. Requires two load operations (e.g., RF[0]=D[0]; RF[1]=D[1], an operation (e.g., RF[2]=RF[0]+RF[1]), and a store operation (e.g., D[9]=RF[2]) Letʼs do 1 more example Load operation operation Store operation 6

7 One more example Q: Which are valid single-cycle operations for given datapath? Add d(0) + R1, store in R2? A: NO! We can t do this in 1 CC Why? No direct path from memory to 2x 1 7

8 Exercise: Basic Datapath Operations Q: How many cycles does each of the following take for given datapath? Move RF[1] to RF[2] 1 Add D[8] with RF[2] and store the result in RF[4] 2 Add D[8] with RF[1], then add the result with RF[4], and store the final result in D[8] 4 X.S. Hu 8

9 One more example Q: How can we do: d(0) + R1, store in R2? Need at least 2 instructions: MOV R3, D(0) # LOAD D(0) ADD R2, R1, R3 # Do the ADD 2x 1 9

10 Basic Architecture Control Unit D[9] = D[0] + D[1] requires a sequence of four datapath operations: 0: RF[0] = D[0] 1: RF[1] = D[1] 2: RF[2] = RF[0] + RF[1] 3: D[9] = RF[2] Each operation is an instruction Sequence of instructions program Looks cumbersome, but that's the world of programmable processors Decomposing desired computations into processor-supported operations Store program in Instruction memory reads each instruction and executes it on the datapath : Program counter address of current instruction : Instruction register current instruction Instruction memory 3: D[9]=RF[2] I Datapath 10

11 Basic Architecture Control Unit To carry out each instruction, the control unit must: Fetch Read instruction from inst. mem. Decode Determine the operation and operands of the instruction Execute Carry out the instruction's operation using the datapath Instruction memory I 3: D[9]=RF[2] 0 >1 (a) Fetch RF[0]=D[0] Instruction memory I 3: D[9]=RF[2] 1 RF[0]=D[0] (b) Decode "load" Instruction memory I 3: D[9]=RF[2] 1 RF[0]=D[0] Execute D[0]: 99 R[0]:?? 99 (c) Datapath 11

12 Basic Architecture Control Unit To carry out each instruction, the control unit must: Fetch Read instruction from inst. mem. Decode Determine the operation and operands of the instruction Execute Carry out the instruction's operation using the datapath Instruction memory I 3: D[9]=RF[2] 1 >2 (a) Fetch RF[1]=D[1} Instruction memory I 3: D[9]=RF[2] 2 RF[1]=D[1] (b) Decode "load" Instruction memory I 3: D[9]=RF[2] 2 RF[1]=D[1] Execute D[1]: 102 R[1]:?? 102 (c) Datapath 12

13 Basic Architecture Control Unit To carry out each instruction, the control unit must: Fetch Read instruction from inst. mem. Decode Determine the operation and operands of the instruction Execute Carry out the instruction's operation using the datapath Instruction memory I 3: D[9]=RF[2] 2 >3 (a) Fetch RF[2]=RF[0]+RF[1] Instruction memory I 3: D[9]=RF[2] 3 RF[2]=RF[0]+RF[1] (b) Decode " (add)" Instruction memory I 3: D[9]=RF[2] 3 RF[2]=RF[0]+RF[1] Execute R[2]:?? 201 (c) Datapath

14 Basic Architecture Control Unit To carry out each instruction, the control unit must: Fetch Read instruction from inst. mem. Decode Determine the operation and operands of the instruction Execute Carry out the instruction's operation using the datapath Instruction memory I 3: D[9]=RF[2] 3 >4 (a) Fetch D[9]=RF[2] Instruction memory I 3: D[9]=RF[2] 4 D[9]=RF[2] (b) Decode "store" Instruction memory I 3: D[9]=RF[2] 4 D[9]=RF[2] Execute D[9]=?? 201 R[2]: 201 (c) Datapath 14

15 Basic Architecture Control Unit Init =0 Fetch = I[] =+1 Decode Execute Instruction memory I 3: D[9]=RF[2] Letʼs summarize together Datapath 15

16 Creating a Sequence of Instructions Q: Create sequence of instructions to compute D[3] = D[0]+D[1]+D[2] on earlier-introduced processor A1: One possible sequence A2: Alternative sequence First load data memory locations into register file First load D[0] and D[1] and add them R[3] = D[0] R[1] = D[0] R[4] = D[1] R[2] = D[1] R[2] = D[2] R[1] = R[1] + R[2] (Note arbitrary register locations) Next, load D[2] and add Next, perform the additions R[2] = D[2] R[1] = R[3] + R[4] R[1] = R[1] + R[2] Finally, store result D[3] = R[1] Questions from last time? R[1] = R[1] + R[2] Finally, store result D[3] = R[1]

17 Exercise: Creating Instruction Sequences Q1: D[8] = D[8] + RF[1] + RF[4] RF[2] = RF[1] + RF[4] RF[3] = D[8] RF[2] = RF[2] + RF[3] D[8] = RF[2] Q2: RF[2] = RF[1] RF[2] = RF[1] + 0 Letʼs do 1 more example X.S. Hu 17

18 One more example R2 = R3 R3 = R2 (swap) -- Thoughts? MOV d(x), R2 MOV d(y), R3 MOV R2, d(y) MOV R2, d(x) Datapath Could do in 3 but only with added functionality: How? 18

19 Three-Instruction Programmable Processor 8.3 Instruction Set List of allowable instructions and their representation in memory, e.g., Load instruction 0000 r 3 r 2 r 1 r 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 Store instruction 0001 r 3 r 2 r 1 r 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 Add instruction 0010 ra 3 ra 2 ra 1 ra 0 rb 3 rb 2 rb 1 rb 0 rc 3 rc 2 rc 1 rc 0 Desired program 3: D[9]=RF[2} Instruction is an idea that helps abstract 1s, 0s, but still provides info. about HW Instruction memory 0: : : : I Instructions in 0s and 1s machine code opcode operands 19

20 Program for Three-Instruction Processor OODE = sequence of 1s, 0s thatʼs fed to controller to tell datapath what to do Desired program 3: D[9]=RF[2} Instruction memoryi 0: : : : Computes D[9]=D[0]+D[1] 2 1 Datapath 20

21 Program for Three-Instruction Processor Another example program in machine code Compute D[5] = D[5] + D[6] + D[7] 0: // RF[0] = D[5] 1: // RF[1] = D[6] 2: // RF[2] = D[7] 3: // RF[0] = RF[0] + RF[1] // which is D[5]+D[6] 4: // RF[0] = RF[0] + RF[2] // now D[5]+D[6]+D[7] 5: // D[5] = RF[0] Load instruction 0000 r 3 r 2 r 1 r 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 Store instruction 0001 r 3 r 2 r 1 r 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 Add instruction 0010 ra 3 ra 2 ra 1 ra 0 rb 3 rb 2 rb 1 rb 0 rc 3 rc 2 rc 1 rc 0 21

22 Assembly Code Machine code (0s and 1s) hard to work with Assembly code Uses mnemonics Load instruction MOV Ra, d specifies the operation RF[a]=D[d]. a must be 0,1,..., or 15 so R0 means RF[0], R1 means RF[1], etc. d must be 0, 1,..., 255 Store instruction MOV d, Ra specifies the operation D[d]=RF[a] Add instruction ADD Ra, Rb, Rc specifies the operation RF[a]=RF[b]+RF[c] Instruction is an idea that helps abstract 1s, 0s, but still provides info. about HW Desired program 3: D[9]=RF[2] 0: : : : : MOV R0, 0 1: MOV R1, 1 2: ADD R2, R0, R1 3: MOV 9, R2 machine code assembly code 22

23 Exercise: Creating Assembly Code Q1: D[8] = D[8] + RF[1] + RF[4] RF[2] = RF[1] + RF[4] Add R2, R1, R4 RF[3] = D[8] MOV R3, 8 RF[2] = RF[2] + RF[3] Add R2, R2, R3 D[8] = RF[2] MOV 8, R2 Q2: RF[2] = RF[1] RF[2] = RF[1] + 0 MOV R1, 0?? X.S. Hu 23

24 Control-Unit and Datapath for Three-Instruction Processor To design the processor, we can begin with a high-level state machine description of the processor's behavior Init =0 Fetch =I[] =+1 Decode op=0000 op=0001 op=0010 Load RF[ra]=D[d] Store D[d]=RF[ra] Add RF[ra] = RF[rb]+ RF[rc] Your 1st lab is about state machines. Theyʼre important b/c they help to automate instruction processing. 24

25 Control-Unit and Datapath for Three-Instruction Processor Create detailed connections among components Load Init =0 RF[ra]=D[d] Fetch Decode Store D[d]=RF[ra] =I[] =+1 op=0000 op=0001 op=0010 Add RF[ra] = RF[rb]+ RF[rc] addr clr up rd _ r d R _ l d I P C _ c l r I P C _ i n c data Id I alu_s0 D_addr 8 addr D_rd Data memory rd D D_wr 256x wr W_data R_data RF_s RF_W_addr 4 RF_W_wr RF_Rp_addr 4 RF_Rp_rd RF_Rq_addr 4 RF_Rq_rd Datapath 1 s -bit 2x 1 W_data W_addr W_wr Rp_addr Rp_rd Rq_addr Rq_rd Rp_data s0 0 A B Before D x RF Rq_data 25

26 Control-Unit and Datapath for Three-Instruction Convert high-level state machine description of entire processor to FSM description of controller that uses datapath and other components to achieve same behavior s t a t e s Init =0 _ clr=1 Load RF[ra]=D[d] D_addr=d D_rd=1 RF_s=1 RF_W_addr=ra RF_W_wr=1 E x e c u t e Fetch Decode op=0000 op=0001 op=0010 Store D[d]=RF[ra] D_addr=d D_wr=1 RF_s=X RF_Rp_addr=ra RF_Rp_rd=1 =I[] =+1 I_rd=1 =+1 _inc=1 _ld=1 Add Add RF[ra] RF[ra] = RF[rb]+ = RF[rb]+ RF[rc] RF_Rp_addr=rb RF[rc] RF_Rp_rd=1 RF_s=0 RF_Rq_addr=rc RF_Rq _rd=1 RF_W_addr=ra RF_W_wr=1 alu_s0=1 Processor addr clr up rd data Id _ r d R _ l d I P C _ c l r I P C _ i n c I RF_W_addr RF_W_wr RF_Rp_addr RF_Rp_rd RF_Rq_addr RF_Rq_rd alu_s0 D_addr 8 addr D_rd rd D_wr 256x wr W_dataR_data RF_s s Datapath 1 0 -bit W_data W_addr W_wr Rp_addr Rp_rd Rq_addr Rq_rd D x RF Rp_data Rq_data s0 A B 26

27 Exercise: Understanding the Processor Design (1) Will the correct instruction be fetched if is incremented during the fetch cycle? No, since will not be updated until the beginning of the next cycle While executing MOV R1, 3, what is the content of and at the end of the 1st cycle, 2nd cycle, 3rd cycle, etc.? 1st cycle: = 0, = xxxx 2 nd cycle: = 1, = I[0] 3 rd cycle: = 1, = I[0] What if it takes more than 1 cycle for memory read? Cannot decode until is loaded X.S. Hu 27

28 Exercise: Understanding the Processor Design (2) Q1: D[8] = D[8] + RF[1] + RF[4] I[15]: Add R2, R1, R4 RF[1] = 4 CLK I[]: MOV R3, 8 RF[4] = 5 I[17]: Add R2, R2, R3 D[8] = 7 (n+1) Fetch =15 =xxxx (n+2) Decode = =2214h (n+3) Execute = =2214h RF[2]= xxxxh (n+4) (n+5) Fetch Decode = =17 =2214h =0308h RF[2]= 0009h (n+6) Execute =17 =0308h RF[3]= xxxxh (n+7) Fetch =17 =0308h RF[3]= 0007h X.S. Hu 28

29 Exercise: Extending the Three-Instruction Processor Add a instruction: JMP: jump to a location specified by the 12-bit offset RTL: = +I[15:4] AS: JMP 3 MC: Init =0 Fetch Decode op=0000 op=0001 op=0010 =I[] =+1 op=1000 Jump a+b-1 12 addr up ld clr Let s talk about A+B-1 a bit more Also, why is this instruction useful? rd data Id I alu_s0 D_addr 8 D_rd D_wr RF_s RF_W_addr 4 RF_W_wr RF_Rp_addr 4 RF_Rp_rd RF_Rq_addr 4 RF_Rq_rd addr rd 256x wr W_data R_data s 1 -bit W_data W_addr W_wr Rp_addr Rp_rd Rq_addr Rq_rd Rp_data 0 D x RF Rq_data _ld =1 s0 A B X.S. Hu Datapath 29

30 A Six-Instruction Programmable Processor 8.4 Let's add three more instructions: Load-constant instruction 0011 r 3 r 2 r 1 r 0 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 MOV Ra, #c specifies the operation RF[a]=c Subtract instruction 0100 ra 3 ra 2 ra 1 ra 0 rb 3 rb 2 rb 1 rb 0 rc 3 rc 2 rc 1 rc 0 SUB Ra, Rb, Rc specifies the operation RF[a]=RF[b] RF[c] Jump-if-zero instruction 0101 ra 3 ra 2 ra 1 ra 0 o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 JMPZ Ra, offset specifies the operation = + offset if RF[a] is 0 30

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