How To Understand The Rules Of The Game Of Chess
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1 Insiue for Sofware Technology Qualiy Assurance in Sofware Developmen Qualiässicherung in der Sofwareenwicklung A.o.Univ.-Prof. Dipl.-Ing. Dr. Bernhard Aichernig Insiue for Sofware Technology Graz Universiy of Technology Ausria Summer Term / 31
2 Agenda 1 Conformance Tesing Properies 2 Labelled Transiion Sysems Equivalence Preorder ioco Examples 3 Tes generaion 2 / 31
3 Insiue for Sofware Technology Inpu/Oupu Conformance Relaion Jan Tremans Based on IO-Labeled Transiion Sysems 3 / 31
4 Insiue for Sofware Technology Inpu/Oupu Conformance Relaion Jan Tremans Based on IO-Labeled Transiion Sysems 3 / 31
5 Conformance Tesing 4 / 31
6 Conformance Tesing - Soundness Tes suie is sound: conformance all ess pass 5 / 31
7 Conformance Tesing - Soundness Tes suie is sound: conformance all ess pass 5 / 31
8 Conformance Tesing - Exhausiveness Tes suie is exhausive: conformance all ess pass 6 / 31
9 Conformance Tesing - Exhausiveness Tes suie is exhausive: conformance all ess pass 6 / 31
10 Conformance Tesing - Compleeness Tes suie is complee: conformance all ess pass 7 / 31
11 Conformance Tesing - Compleeness Tes suie is complee: conformance all ess pass 7 / 31
12 Conformance Tesing wih ioco Sysem (Implemenaion) is modeled as IOTS weakly inpu enabled Specificaion is an IOLTS possibly incomplee possible non-deerminisic!g1 τ τ!g1?g2!g3?g2!g3!g1 8 / 31
13 Conformance Tesing wih ioco Sysem (Implemenaion) is modeled as IOTS weakly inpu enabled Specificaion is an IOLTS possibly incomplee possible non-deerminisic!g1 τ τ!g1?g2!g3?g2!g3!g1 8 / 31
14 Inpu Oupu Labeled Transiion Sysems Inpu Oupu Labeled Transiion Sysem An IOLTS is an LTS M = (Q M, A M, M, q M 0 ) wih Q M a finie se of saes A M = A M I A M O {τ} where A M I and A M O are inpu and oupu alphabes τ A M I A M O is an unobservable, inernal acion M Q M A M Q M is he ransiion relaion q M 0 QUESTION? QM is he iniial sae. Wha means: The implemenaion conforms-o he specificaion? 9 / 31
15 Inpu Oupu Labeled Transiion Sysems Inpu Oupu Labeled Transiion Sysem An IOLTS is an LTS M = (Q M, A M, M, q M 0 ) wih Q M a finie se of saes A M = A M I A M O {τ} where A M I and A M O are inpu and oupu alphabes τ A M I A M O is an unobservable, inernal acion M Q M A M Q M is he ransiion relaion q M 0 QUESTION? QM is he iniial sae. Wha means: The implemenaion conforms-o he specificaion? 9 / 31
16 How o relae 2 LTSs? Equivalence Relaions (=) Bisimulaion Trace Equivalence Tesing Equivalence... Preorder Relaions ( ) Trace Preorder Tesing Preorder... Inpu-Oupu Relaions ioconf ioco / 31
17 (Weak) Bisimulaion Two saes are bisimilar iff hey simulae each oher and go o saes which are bisimilar Bisimulaion is no suied for esing! 11 / 31
18 Insiue for Sofware Technology Trace Equivalence A race is an observable sequence of acions Two saes are race equivalen iff hey have he same races Trace equivalence is he weakes noion of conformance 12 / 31
19 Equivalence vs. Preorder Relaions Equivalence Relaion (R) reflexive (srs) symmeric: irs sri ransiive: irs sr ir Preorder Relaions ( ) NOT necessarily anisymmeric: irs i s s i simplifies esing e.g.: Trace Preorder i r s races(i) races(s) 13 / 31
20 Insiue for Sofware Technology Some Noaions: Transiions q a M q = df (q, a, q ) M q ɛ q = df (q = q ) (q τ M q 1 q n 1 τ M q ) q a q = df q 1, q 2 : q ɛ M q 1 a M q 2 ɛ M q 14 / 31
21 Some Noaions: Quiescence δ is used o represen quiescence q δ q = df q is a quiescen sae. Quiescen sae = no edge labeled wih an oupu or an inernal acion 15 / 31
22 Some Noaions: Quiescence δ is used o represen quiescence q δ q = df q is a quiescen sae. Quiescen sae = no edge labeled wih an oupu or an inernal acion 15 / 31
23 Some Noaions: Suspension Auomaon (M) = (Q M, A (M), (M), q0 M) where: A (M) = A M {δ} wih δ A (M) O (M) is obained from M by adding loops q δ q for each quiescen sae 16 / 31
24 Insiue for Sofware Technology Some Noaions: Afer q afer M σ = df {q q σ M q } Q afer M σ = df q Q (q afer M σ). 17 / 31
25 Insiue for Sofware Technology Some Noaions: Ou Ou M (q) = df {a A M O q a M } Ou M (Q) = df q Q (Ou M(q)) 18 / 31
26 ioco Definiion: ioco Le IUT = (Q IUT, A IUT, IUT, q0 IUT ) be weakly inpu enabled wih A IUT = A IUT I A IUT O {τ} and S = ( ) Q S, A S, S, q0 S be srongly responsive wih A S = A S I A S O {τ}. Then: IUT ioco S = df σ races( (S)) : Ou IUT ( (IUT ) afer IUT σ) Ou S ( (S) afer S σ). IUT ioco S iff oupus (and quiescences) of he IUT are possible in S afer an arbirary suspension race of S. 19 / 31
27 ioco Definiion: ioco Le IUT = (Q IUT, A IUT, IUT, q0 IUT ) be weakly inpu enabled wih A IUT = A IUT I A IUT O {τ} and S = ( ) Q S, A S, S, q0 S be srongly responsive wih A S = A S I A S O {τ}. Then: IUT ioco S = df σ races( (S)) : Ou IUT ( (IUT ) afer IUT σ) Ou S ( (S) afer S σ). IUT ioco S iff oupus (and quiescences) of he IUT are possible in S afer an arbirary suspension race of S. 19 / 31
28 Insiue for Sofware Technology P ioco S? P ioco S = df σ races( (S)) : Ou IUT ( (P) afer IUT σ) Ou S ( (S) afer S σ). 20 / 31
29 Insiue for Sofware Technology P ioco S? P ioco S = df σ races( (S)) : Ou IUT ( (P) afer IUT σ) Ou S ( (S) afer S σ). 20 / 31
30 Insiue for Sofware Technology P ioco S? P ioco S = df σ races( (S)) : Ou IUT ( (P) afer IUT σ) Ou S ( (S) afer S σ). 21 / 31
31 Insiue for Sofware Technology P ioco S? P ioco S = df σ races( (S)) : Ou IUT ( (P) afer IUT σ) Ou S ( (S) afer S σ). 21 / 31
32 Insiue for Sofware Technology P ioco S? P ioco S = df σ races( (S)) : Ou IUT ( (P) afer IUT σ) Ou S ( (S) afer S σ). 22 / 31
33 Insiue for Sofware Technology P ioco S? P ioco S = df σ races( (S)) : Ou IUT ( (P) afer IUT σ) Ou S ( (S) afer S σ). 22 / 31
34 Insiue for Sofware Technology P ioco S? P ioco S = df σ races( (S)) : Ou IUT ( (P) afer IUT σ) Ou S ( (S) afer S σ). 23 / 31
35 Insiue for Sofware Technology P ioco S? P ioco S = df σ races( (S)) : Ou IUT ( (P) afer IUT σ) Ou S ( (S) afer S σ). 23 / 31
36 Insiue for Sofware Technology P ioco S? P ioco S = df σ races( (S)) : Ou IUT ( (P) afer IUT σ) Ou S ( (S) afer S σ). 24 / 31
37 Insiue for Sofware Technology P ioco S? P ioco S = df σ races( (S)) : Ou IUT ( (P) afer IUT σ) Ou S ( (S) afer S σ). 24 / 31
38 Insiue for Sofware Technology P ioco S? P ioco S = df σ races( (S)) : Ou IUT ( (P) afer IUT σ) Ou S ( (S) afer S σ). 25 / 31
39 Insiue for Sofware Technology P ioco S? P ioco S = df σ races( (S)) : Ou IUT ( (P) afer IUT σ) Ou S ( (S) afer S σ). 25 / 31
40 Tes Cases A es case is an IOLTS Inpus = Oupus IUT, Oupus = Inpus IUT Equipped wih verdic saes (pass, fail) In each sae (excep Pass, Fail): Single oupu and all inpus All inpus and θ 26 / 31
41 Formal Tes Execuion 27 / 31
42 Formal Tes Execuion 27 / 31
43 Formal Tes Execuion 27 / 31
44 Formal Tes Execuion 27 / 31
45 Formal Tes Execuion 27 / 31
46 Formal Tes Execuion 27 / 31
47 Formal Tes Execuion 27 / 31
48 Formal Tes Execuion 27 / 31
49 Formal Tes Execuion 27 / 31
50 Formal Tes Execuion 27 / 31
51 Formal Tes Execuion 27 / 31
52 A Complee Tes Generaion Algorihm Given he suspension auomaon of a specificaion as an LTS S = (Q S, A S, S, q S 0 ) 1 Iniially compue K = q0 S afer S ɛ 2 Do non-deerminisically, eiher: Sop es case wih verdic pass Le he es case produce an oupu (!a) wih K = K afer S?a. Also accep all inpus a he same ime and add fail saes for unexpeced resuls. Accep all inpus (and quiescence) and add fail saes for unexpeced resuls. Compue new K for valid inpus. 3 Repea Sep 2 wih new se K. 28 / 31
53 A Complee Tes Generaion Algorihm δ δ 29 / 31
54 A Complee Tes Generaion Algorihm δ δ 29 / 31
55 A Complee Tes Generaion Algorihm δ δ 29 / 31
56 A Complee Tes Generaion Algorihm δ δ 29 / 31
57 A Complee Tes Generaion Algorihm δ δ 29 / 31
58 A Complee Tes Generaion Algorihm δ δ 29 / 31
59 A Complee Tes Generaion Algorihm δ δ 29 / 31
60 Insiue for Sofware Technology Tools TGV: offline esing ool jtorx: online esing MoMu: offline model-based muaion esing ool, AIT and TU Graz SpecExplorer: uses Alernaing Simulaion (equivalen o ioco for deerminisic LTS) 30 / 31
61 References Marin Weiglhofer, Bernhard Aichernig, and Franz Woawa. Faul-based conformance esing in pracice. Inernaional Journal of Sofware and Informaics, 3(2-3): , June/Sepember Copyrigh by Insiue for Sofware, Chinese Academy of Science. 31 / 31
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Analogue and Digital Signal Processing. First Term Third Year CS Engineering By Dr Mukhtiar Ali Unar
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