SEMICONDUCTOR TECHNICAL DATA

Transcription

1 SEMIONDUTOR TEHNIAL DATA The phase locked loop contains two phase comparators, a voltage controlled oscillator (VO), source follower, and zener diode. The comparators have two common signal inputs, PAin and. Input PAin can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. The self bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator (an exclusive OR gate) provides a digital error signal Pout, and maintains 90 phase shift at the center frequency between PAin and signals (both at 50% duty cycle). Phase comparator (with leading edge sensing logic) provides digital error signals, Pout and LD, and maintains a 0 phase shift between PAin and signals (duty cycle is immaterial). The linear VO produces an output signal VOout whose frequency is determined by the voltage of input VOin and the capacitor and resistors connected to pins A, B, R, and R. The source follower output SFout with an external resistor is used where the VOin signal is needed but no loading can be tolerated. The inhibit input Inh, when high, disables the VO and source follower to minimize standby power consumption. The zener diode can be used to assist in power supply regulation. Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage to frequency conversion and motor speed control. Buffered Outputs ompatible with MHTL and Low Power TTL Diode Protection on All Inputs Supply Voltage Range = 3.0 to 8 V Pin for Pin Replacement for D4046B Phase omparator is an Exclusive Or Gate and is Duty ycle Limited Phase omparator switches on Rising Edges and is not Duty ycle Limited BLOK DIAGRAM L SUFFIX ERAMI ASE 60 ORDERING INFORMATION M4XXXBP M4XXXBL M4XXXBDW Plastic eramic SOI TA = 55 to 5 for all packages. PIN ASSIGNMENT LD Pout VOout INH A B VSS P SUFFIX PLASTI ASE 648 DW SUFFIX SOI ASE 75G 9 ZENER PAin Pout R R SFout VOin PAin 4 3 SELF BIAS IRUIT PHASE OMPARATOR PHASE OMPARATOR Pout 3 Pout LD = PIN 6 VSS = PIN 8 VOin 9 TAGE ONTROLLED OSILLATOR (VO) 4 VOout R R 6 A 7 B INH 5 VSS SOURE FOLLOWER SFout ZENER REV 3 /94 MOTOROLA Motorola, Inc. 995 MOS LOGI DATA

2 Î Î Î MAXIMUM RATINGS* (Voltages Referenced to VSS) Î Rating Symbol Value Unit D Supply Voltage Î 0.5 to + 8 Vdc Input Voltage, All Inputs Î Vin 0.5 to Vdc D Input urrent, per Pin Î Iin ± madc Power Dissipation, per Package Î PD 500 mw Operating Temperature Range Î TA 55 to + 5 Storage Temperature Range Î Tstg 65 to + 0 Î * Maximum Ratings are those values beyond which damage to the device may occur. Î Temperature Derating: Plastic P and D/DW Packages: 7.0 mw/ From 65 To 5 Î Î eramic L Packages: mw/ From 0 To 5 ELETRIAL HARATERISTIS (Voltages Referenced to VSS) Î ÎÎ haracteristic Symbol ÎÎ Î Vdc Min Max Min Typ Max Min Max Unit Output Voltage 0 Level Vdc Î Î Î Î Vin = or Î ÎÎ 0.05 Level Î Î Î 4.95 Vdc Vin = 0 or ÎÎ 4.95 Input Voltage # 0 Level VIL Vdc ÎÎ (VO = 4.5 or 0.5 Vdc) Î.5 Î.5.5 Î.5 (VO = 9.0 or.0 Vdc) (VO = 3.5 or.5 Vdc) (VO = 0.5 or 4.5 Vdc) Level VIH Î Î.75 Î 3.5 Vdc ÎÎ (VO =.0 or 9.0 Vdc) Î 7.0 Î (VO =.5 or 3.5 Vdc) Î ÎÎ Output Drive urrent IOH madc ÎÎ ( =.5 Vdc) SourceÎÎ Î..0Î.7 Î 0.7 ÎÎ ( = 4.6 Vdc) Î ( = 9.5 Vdc) ( = 3.5 Vdc) 0.5 Î Î ÎÎ ( = 0.4 Vdc) Sink IOL Î Î 0.88 Î 0.36 madc ÎÎ ( = 0.5 Vdc) Î.6 Î ( =.5 Vdc) Î ÎÎ Î Î Î Input urrent I in ± 0. ± ± 0. ±.0 µadc ÎÎ Î Î Î Input apacitance in 7.5 pf Quiescent urrent IDD µadc ÎÎ (Per Package) Inh = PAin =, Zener = VOin = 0 V, = or 0 V, Iout = 0 µa ÎÎ 300 ÎÎ 600 Total Supply urrent IT IT = (.46 µa/khz) f + IDD madc Î ÎÎ (Inh = 0, fo = khz, L = 50 pf, ÎÎ R =.0 MΩ, R = RSF =, and 50% Duty ycle) IT = (.9 µa/khz) f + IDD IT = (4.37 µa/khz) f + IDD #Noise immunity specified for worst case input combination. Noise Margin for both and 0 level =.0 Vdc = Vdc.0 Vdc = Vdc.5 Vdc = Vdc To alculate Total urrent in General: VOin.65 IT. x. + V DD.35 3/4. VOin.65 3/4 +.6 x.. + x 3 (L + 9) f + R R RSF x. 0% Duty ycle of PA in. + I Q 0 where: IT in µa, L in pf, VOin, in Vdc, f in khz, and R, R, RSF in MΩ, L on VOout.

3 Î Î ELETRIAL HARATERISTIS* Î Î Î ÎÎ Î (L = 50 pf, TA = 5 ) Î Î Î Î Minimum ÎÎ Î Maximum Î haracteristic Î Symbol Î Vdc Î Device ÎÎ Typical Î Device Units Î Output Rise Time Î Î Î ÎÎ Î ttlh ns Î Î Î ttlh = (3.0 ns/pf) L + 30 ns Î ÎÎ 80 Î 350 ttlh = (.5 ns/pf) L + ns ttlh = (. ns/pf) L + ns Î ÎÎ Î Î Output Fall Time Î tthl Î ÎÎ ns tthl = (.5 ns/pf) L + 5 ns 0 75 Î tthl = (0.75 ns/pf) L +.5 ns tthl = (0.55 ns/pf) L ns Î Î 55 PHASE OMPARATORS and Î Input Resistance PAin Rin.0.0 MΩ Î Î Î Î ÎÎ 0. Î Î Î Î Î ÎÎ Î Rin 0 00 MΩ Î Î Î Î ÎÎ Î Minimum Input Sensitivity Vin mv p p Î A oupled PAin series = 00 pf, f = 50 khz Î Î Î D oupled PAin, 5 to See Noise Immunity Î TAGE ONTROLLED OSILLATOR (VO) Î Maximum Frequency fmax MHz Î (VOin =, = 50 pf Î Î Î.0 ÎÎ.4 Î Î Î Î Î ÎÎ Î R = kω, and R = ).4.9 Î Temperature Frequency Stability Î Î Î ÎÎ 0. Î %/ (R = ) 0.04 ÎÎ 0.0 Î Î Linearity (R = ) Î Î ÎÎ Î % Î Î Î (VOin =.5 V ± 0.3 V, R > kω) Î ÎÎ.0 Î (VOin = V ±.5 V, R > 400 kω) (VOin = 7.5 V ± V, R 00 kω).0 Î Î Î Î ÎÎ.0 Î Î Output Duty ycle 5 to 50 Î % Input Resistance VOin Rin 0 00 MΩ Î SOURE FOLLOWER Î Offset Voltage.65. V (VOin minus SFout, RSF > 500 kω) Î ÎÎ Î Î ÎÎ.65 Î..65. Linearity % Î (VOin =.5 V ± 0.3 V, RSF > 50 kω) 0. (VOin = V ±.5 V, RSF > 50 kω) (VOin = 7.5 V ± V, RSF > 50 kω) 0.6 Î 0.8 Î ZENER DIODE Î Zener Voltage (Iz = 50 µa) VZ Î V Dynamic Resistance (Iz =.0 ma) Î Î ÎÎ RZ Î Î 0 Î Î Ω * The formula given is for the typical characteristics only. 3

4 PHASE OMPARATOR Input Stage X X PAin 00 0 Pout 0 Input Stage PHASE OMPARATOR X X PAin State Pout 0 Output Disconnected LD 0 0 (Lock Detect) Refer to Waveforms in Figure 3. Figure. Phase omparators State Diagrams haracteristic Using Phase omparator Using Phase omparator No signal on input PAin. VO in PLL system adjusts to center VO in PLL system adjusts to minimum frequency (f0). frequency (fmin). Phase angle between PAin and. 90 at center frequency (f0), approaching 0 Always 0 in lock (positive rising edges). and 80 at ends of lock range (fl) Locks on harmonics of center frequency. ÎÎ Yes No Signal input noise rejection. ÎÎ High Low Lock frequency range (fl). ÎÎ The frequency range of the input signal on which the loop will stay locked if it was ÎÎ initially in lock; fl = full VO frequency range = fmax fmin. apture frequency range (f). ÎÎ The frequency range of the input signal on which the loop will lock if it was initially Î ÎÎ out of lock. Depends on low pass filter characteristics (see Figure 3). f f = fl ÎÎ fl enter frequency (f0). ÎÎ The frequency of VOout, when VOin = / VO output frequency (f). ÎÎ fmin = (VO input = VSS) Î R( + 3 pf) Note: These equations are intended to be ÎÎ a design guide. Since calculated component fmax = values may be in error by as much as a ÎÎ + fmin (VO input = ) R ( + 3 pf) ÎÎ factor of 4, laboratory experimentation may be required for fixed designs. Part to part Where: K R M frequency variation with identical passive ÎÎ ÎÎ K R M components is typically less than ± 0%. ÎÎ 0pF.0 µf Figure. Design Information 4

5 VOin 9 SOURE FOLLOWER RSF SFout FREQUENY f 4 3 PHASE OMPARATOR OR 3 Pout OR Pout EXTERNAL LOW PASS FILTER EXTERNAL N OUNTER 9 VO IA IB R R I FREQUENY Nf = f (a) INPUT R3 OUTPUT f fl R3 Typical Low Pass Filters (a) INPUT R3 R4 OUTPUT Typically: R4 6N fmax N f (R3 3, 000) 0Nf fmax f = fmax fmin R 4 NOTE: Sometimes R3 is split into two series resistors each R3. A capacitor is then placed from the midpoint to ground. The value for should be such that the corner frequency of this network does not significantly affect ωn. In Figure B, the ratio of R3 to R4 sets the damping, R4 (0.)(R3) for optimum results. Definitions: N = Total division ratio in feedback loop Kφ = /π for Phase omparator Kφ = /4 π for Phase omparator KVO f VO V for a typical design fr ωn (at phase detector input) ζ Filter A n KKVO NR 3 N n K KVO F(s) R 3 S LOW PASS FILTER Filter B K KVO n N (R3 R4) 0.5 n (R 3 N K KVO ) R3S F(s) S(R 3 R 4 ) Waveforms PAin Pout VOin Phase omparator Phase omparator VSS PAin Pout VOin Note: for further information, see: () F. Gardner, Phase Lock Techniques, John Wiley and Son, New York, 966. () G. S. Moschytz, Miniature R Filters Using Phase Locked Loop, BSTJ, May, 965. (3) Garth Nash, Phase Lock Loop Design Fundamentals, AN 535, Motorola Inc. (4) A. B. Przedpelski, Phase Locked Loop Design Articles, AR54, reprinted by Motorola Inc. LD VSS Figure 3. General Phase Locked Loop onnections and Waveforms 5

6 OUTLINE DIMENSIONS L SUFFIX ERAMI DIP PAKAGE ASE 60 ISSUE V T SEATING PLANE F A E G D 6 PL 0.5 (0.0) M T N B A S K L M J 6 PL 0.5 (0.0) M T B S NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y4.5M, 98.. ONTROLLING DIMENSION: INH. 3. DIMENSION L TO ENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE ERAMI BODY. INHES MILLIMETERS DIM MIN MAX MIN MAX A B D E BS.7 BS F G 0.0 BS.54 BS H K L BS 7.6 BS M 0 0 N P SUFFIX PLASTI DIP PAKAGE ASE ISSUE R 6 H A 8 G F 9 D 6 PL B S K 0.5 (0.0) M T SEATING T PLANE A M J L M NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y4.5M, 98.. ONTROLLING DIMENSION: INH. 3. DIMENSION L TO ENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INLUDE MOLD FLASH. 5. ROUNDED ORNERS OPTIONAL. INHES MILLIMETERS DIM MIN MAX MIN MAX A B D F G 0.0 BS.54 BS H BS.7 BS J K L M 0 0 S

7 OUTLINE DIMENSIONS D SUFFIX PLASTI SOI PAKAGE ASE 75B 05 ISSUE J T SEATING PLANE G A D 6 PL K B P 8 PL 0.5 (0.0) M B S 0.5 (0.0) M T B S A S M R X 45 J F NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y4.5M, 98.. ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0. (0.006) PER SIDE. 5. DIMENSION D DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.7 (0.005) TOTAL IN EXESS OF THE D DIMENSION AT MAXIMUM MATERIAL ONDITION. MILLIMETERS INHES DIM MIN MAX MIN MAX A B D F G.7 BS BS J K M P R Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi SPD JLD, 6F Seibu Butsuryu enter, P.O. Box 09; Phoenix, Arizona or Tatsumi Koto Ku, Tokyo 35, Japan MFAX: RMFAX0@ .sps.mot.com TOUHTONE ASIA/PAIFI: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: NET.com 5 Ting Kok Road, Tai Po, N.T., Hong Kong /D 7

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