6.976 High Speed Communication Circuits and Systems Lecture 7 Noise Modeling in Amplifiers

Transcription

1 6.976 High Speed Communication Circuits and Systems Lecture 7 Noise Modeling in Amplifiers Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott

2 Notation for Mean, Variance, and Correlation Consider random variables x and y with probability density functions f x (x) and f y (y) and joint probability function f xy (x,y) - Expected value (mean) of x is Note: we will often abuse notation and denote as a random variable (i.e., noise) rather than its mean - The variance of x (assuming it has zero mean) is - A useful statistic is If the above is zero, x and y are said to be uncorrelated

3 Relationship Between Variance and Spectral Density Two-Sided Spectrum A S x (f) One-Sided Spectrum 2A S x (f) -f 2 -f 1 Two-sided spectrum 0 f 1 f 2 f 0 f 1 f 2 f - Since spectrum is symmetric One-sided spectrum defined over positive frequencies - Magnitude defined as twice that of its corresponding two-sided spectrum In the next few lectures, we assume a one-sided spectrum for all noise analysis

4 The Impact of Filtering on Spectral Density S x (f) H(f) 2 S y (f) A B AB 0 f 0 f 0 f x(t) H(f) y(t) For the random signal passing through a linear, time-invariant system with transfer function H(f) - We see that if x(t) is amplified by gain A, we have

5 Noise in Resistors Can be described in terms of either voltage or current R e n R i n k is Boltzmann s constant T is temperature (in Kelvins) - Usually assume room temperature of 27 degrees Celsius

6 Noise In Inductors and Capacitors Ideal capacitors and inductors have no noise! C L In practice, however, they will have parasitic resistance - Induces noise - Parameterized by adding resistances in parallel/series with inductor/capacitor Include parasitic resistor noise sources

7 Noise in CMOS Transistors (Assumed in Saturation) G I D D Transistor Noise Sources Drain Noise (Thermal and 1/f) S Gate Noise (Induced and Routing Parasitic) Modeling of noise in transistors must include several noise sources - Drain noise Thermal and 1/f influenced by transistor size and bias - Gate noise Induced from channel influenced by transistor size and bias Caused by routing resistance to gate (including resistance of polysilicon gate) Can be made negligible with proper layout such as fingering of devices

8 Drain Noise Thermal (Assume Device in Saturation) i nd V GS G V D > V Thermally agitated carriers in the channel cause a randomly varying current S D 2 i nd f - γ is called excess noise factor = 2/3 in long channel = 2 to 3 (or higher!) in short channel NMOS (less in PMOS) - g do will be discussed shortly 4kTγg do f

9 Drain Noise 1/f (Assume Device in Saturation) i nd V GS G V D > V S D Traps at channel/oxide interface randomly capture/release carriers 2 i nd f - Parameterized by K f and n Provided by fab (note n 1) Currently: K f of PMOS << K f of NMOS due to buried channel 4kTγg do - To minimize: want large area (high WL) drain 1/f noise 1/f noise corner frequency drain thermal noise f

10 Induced Gate Noise (Assume Device in Saturation) i ng i ndg V GS G V D > V S D Fluctuating channel potential couples capacitively into the gate terminal, causing a noise gate current 2 i ng f 4kTδg do slope = 20 db/decade - δ is gate noise coefficient Typically assumed to be 2γ - Correlated to drain noise! 5 f t α f

11 Useful References on MOSFET Noise Thermal Noise - B. Wang et. al., MOSFET Thermal Noise Modeling for Analog Integrated Circuits, JSSC, July 1994 Gate Noise - Jung-Suk Goo, High Frequency Noise in CMOS Low Noise Amplifiers, PhD Thesis, Stanford University, August Jung-Suk Goo et. al., The Equivalence of van der Ziel and BSIM4 Models in Modeling the Induced Gate Noise of MOSFETS, IEDM 2000, Todd Sepke, Investigation of Noise Sources in Scaled CMOS Field-Effect Transistors, MS Thesis, MIT, June

12 Drain-Source Conductance: g do g do is defined as channel resistance with V ds =0 - Transistor in triode, so that - Equals g m for long channel devices Key parameters for 0.18µ NMOS devices

13 Plot of g m and g dο versus V gs for 0.18µ NMOS Device 4 Transconductances g m and g do versus Gate Voltage V gs I d 3.5 V gs M 1 W L = 1.8µ 0.18µ Transconductance (milliamps/volts) g d0 =µ n C ox W/L(V gs -V T ) g m (simulated in Hspice) Gate Voltage V gs (Volts) For V gs bias voltages around 1.2 V:

14 Plot of g m and g dο versus I dens for 0.18µ NMOS Device Transconductances g m and g do versus Current Density 4 I d 3.5 V gs M 1 W L = 1.8µ 0.18µ Transconductance (milliamps/volts) g d0 =µ n C ox W/L(V gs -V T ) g m (simulated in Hspice) Current Density (microamps/micron)

15 Noise Sources in a CMOS Amplifier R D e nd R G e ng R gpar e ngpar i ng 1 g g v gs C gd C gs g m v gs -g mb v s r o i nd C db I D R D R G V out C sb e ndeg v s V in R S R deg

16 Remove Model Components for Simplicity R D e nd R G e ng R gpar e ngpar i ng 1 g g v gs C gd C gs g m v gs -g mb v s r o i nd C db I D R D R G V out C sb e ndeg v s V in R S R deg

17 Key Noise Sources for Noise Analysis R D e nd R G e ng i ng v gs C gs g m v gs i nd I R D D R G V out e ndeg v s V in R S R deg Transistor gate noise Transistor drain noise Thermal noise 1/f noise

18 Apply Thevenin Techniques to Simplify Noise Analysis G i out D Z g Z gs i ng v gs C gs g m v gs i nd S Z deg G i out D Z g Z gs v gs C gs g m v gs i ndg S Z deg Assumption: noise independent of load resistor on drain

19 Calculation of Equivalent Output Noise for Each Case G i out D Z g Z gs i ng v gs C gs g m v gs i nd S Z deg G i out D Z g Z gs v gs C gs g m v gs i ndg S Z deg

20 Calculation of Z gs G i out D i test Z g Z gs v test v gs C gs g m v gs S v 1 Z deg Write KCL equations After much algebra:

21 Calculation of η G i out D Z g Z gs v gs C gs g m v gs i test S v 1 Z deg Determine V gs to find i out in terms of i test After much algebra:

22 Calculation of Output Current Noise Variance (Power) G I out D S Z g G Z gs v gs C gs i out g m v gs D i ndg Z g Z deg S Z deg To find noise variance:

23 Variance (i.e., Power) Calc. for Output Current Noise Noise variance calculation Define correlation coefficient c between i ng and i nd

24 Parameterized Expression for Output Noise Variance Key equation from last slide Solve for noise ratio Define parameters Z gsw and χ d

25 Small Signal Model for Noise Calculations G I out D S Z g G Z gs v gs C gs i out g m v gs D i ndg Z g Z deg S Z deg

26 Example: Output Current Noise with Z s = R s, Z deg = 0 Source i out R s e ns V in Z gs v gs C gs g m v gs i ndg Step 1: Determine key noise parameters - For 0.18µ CMOS, we will assume the following Step 2: calculate η and Z gsw

27 Calculation of Output Current Noise (continued) Step 3: Plug values into the previously derived expression Drain Noise Multiplying Factor - For w << 1/(R s C gs ): - For w >> 1/(R s C gs ): Gate noise contribution Gate noise contribution

28 Plot of Drain Noise Multiplying Factor (0.18µ NMOS) Drain Noise Multiplying Factor Versus Frequency for 0.18 µ NMOS Device 1 f << 1/(2πR s C gs ) 0.95 Drain Noise Gain Factor f >> 1/(2πR s C gs ) 1/100 1/ Normalized Frequency --- f/(2πr s C gs ) (Hz) Conclusion: gate noise has little effect on common source amp when source impedance is purely resistive!

29 Broadband Amplifier Design Considerations for Noise 2 i ndg f 4kTγg do drain 1/f noise drain thermal noise gate noise contribution with purely resistive source impedance 1/f noise corner frequency 1 2πR s C gs f Drain thermal noise is the chief issue of concern when designing amplifiers with > 1 GHz bandwidth - 1/f noise corner is usually less than 1 MHz - Gate noise contribution only has influence at high frequencies (such noise will likely be filtered out) Noise performance specification is usually given in terms of input referred voltage noise

30 Narrowband Amplifier Noise Requirements 2 i ndg f 4kTγg do drain 1/f noise drain thermal noise gate noise contribution with purely resistive source impedance 1/f noise corner frequency Narrowband amplifier frequency range 1 2πR s C gs f Here we focus on a narrowband of operation - Don t care about noise outside that band since it will be filtered out Gate noise is a significant issue here - Using reactive elements in the source dramatically impacts the influence of gate noise Specification usually given in terms of Noise Figure

31 The Impact of Gate Noise with Z s = R s +sl g Source i out R s e ns L g V in Z gs v gs C gs g m v gs i ndg Step 1: Determine key noise parameters - For 0.18µ CMOS, again assume the following Step 2: Note that η =1, calculate Z gsw

32 Evaluate Z gsw At Resonance Source i out R s e ns L g V in Z gs v gs C gs g m v gs i ndg Set L g such that it resonates with C gs at the center frequency (w o ) of the narrow band of interest Calculate Z gsw at frequency w o

33 The Impact of Gate Noise with Z s = R s +sl g (Cont.) Key noise expression derived earlier Substitute in for Z gsw Gate noise contribution Gate noise contribution is a function of Q! - Rises monotonically with Q

34 At What Value of Q Does Gate Noise Exceed Drain Noise? 2 i ndg f Narrowband amplifier frequency range 4kTγg do drain thermal noise gate noise contribution w o /2π Q 2 f Determine crossover point for Q value =1 - Critical Q value for crossover is primarily set by process

35 Calculation of the Signal Spectrum at the Output Source i out R s e ns L g V in Z gs v gs C gs g m v gs i ndg First calculate relationship between v in and i out At resonance: Spectral density of signal at output at resonant frequency

36 Impact of Q on SNR (Ignoring R s Noise) 2 i ndg f Narrowband amplifier frequency range signal spectrum Q 2 4kTγg do drain thermal noise gate noise contribution w o /2π Q 2 f SNR (assume constant spectra, ignore noise from R s ): For small Q such that gate noise < drain noise - SNR out improves dramatically as Q is increased For large Q such that gate noise > drain noise - SNR out improves very little as Q is increased

37 Noise Factor and Noise Figure R s e nrs Equivalent output referred current noise (assumed to be independent of Z out and Z L ) Definitions v in Linear,Time Invariant Circuit (Noiseless) Z out i nout Z in v x Z L i out Calculation of SNR in and SNR out

38 Calculate Noise Factor (Part 1) Source i out R s e ns L g V in Z gs v gs C gs g m v gs i ndg First calculate SNR out (must include R s noise for this) - R s noise calculation (same as for V in ) - SNR out : Then calculate SNR in :

39 Calculate Noise Factor (Part 2) Noise Factor calculation: From previous analysis

40 Calculate Noise Factor (Part 3) Modify denominator using expressions for Q and w t Resulting expression for noise factor: Noise Factor scaling coefficient - Noise factor primarily depends on Q, w o /w t, and process specs

41 Minimum Noise Factor Noise Factor scaling coefficient We see that the noise factor will be minimized for some value of Q - Could solve analytically by differentiating with respect to Q and solving for peak value (i.e. where deriv. = 0) In Tom Lee s book (pp ), the minimum noise factor for the MOS common source amplifier (i.e. no degeneration) is found to be: How do these compare? Noise Factor scaling coefficient

42 Plot of Minimum Noise Factor and Noise Factor Vs. Q Noise Factor Scaling Coefficient Versus Q for 0.18 µ NMOS Device 8 Noise Factor Scaling Coefficient c = -j0 c = -j0.55 c = -j1 Note: curves meet if we approximate Q 2 +1 Q 2 Achievable values as a function of Q under the constraint that 1 = w o L g C gs Minimum across all values of Q and 1 L g C gs c = -j0 c = -j0.55 c = -j Q

43 Achieving Minimum Noise Factor For common source amplifier without degeneration - Minimum noise factor can only be achieved at resonance if gate noise is uncorrelated to drain noise (i.e., if c = 0) we ll see this next lecture - We typically must operate slightly away from resonance in practice to achieve minimum noise factor since c will be nonzero How do we determine the optimum source impedance to minimize noise figure in classical analysis? - Next lecture!