IA-64 & x86-64 ISA s
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1 IA-64 & x86-64 ISA s Competing specifications for the 64-bit microprocessor market 2 February 2005 /mtu/ee5970/f02/btd 1
2 Divergence approaches The x86 ISA has been the dominant ISA for many years INTEL, AMD, Cyrix, Transmeta, Via The ISA has been augmented repeatedly through the generations {386 extensions, MMX, SSE} New ISA s have failed {Alpha, i960, etc} due to compatibility issues Both Intel & AMD are designing next generation processors with a new ISA Intel : Itanium (IA-64) available since 1H01 AMD : Hammer (x86-64) available since 2H03 2 February 2005 /mtu/ee5970/f02/btd 2
3 AMD Processor Roadmap 2 February 2005 /mtu/ee5970/f02/btd 3
4 AMD Processor roadmap 2 February 2005 /mtu/ee5970/f02/btd 4
5 Intel Processor Roadmap 2 February 2005 /mtu/ee5970/f02/btd 5
6 Intel Roadmap 2 February 2005 /mtu/ee5970/f02/btd 6
7 Why 64-bits 4 GBytes of memory corresponds to a 32-bit address If a program desires to address more than 4GBytes of memory, the addressing must be extended beyond 32 bits Increased precision Floating point values >64 bits: 64 bit functional units More Parallel Data DSP / Multi-Media Vectors have a 128-bit wide data path (SSE2) 2 February 2005 /mtu/ee5970/f02/btd 7
8 Fundamental Differences IA-64 is a clean break from previous ISA s but it will still execute x86 instructions (in emulated i.e. slow mode) Adds functionality to increase processor performance Makes the job of the hardware designer easier x86-64 is philosophically (some would say pathologically) another extension to the ages-old x86 architecture. Has a single execution pipe for both legacy x86 and new x86-64 code Extends address and data registers (x86 does NOT really have GPRs) 64 bits 2 February 2005 /mtu/ee5970/f02/btd 8
9 RISC vs. CISC The performance differential between CISC & RISC has been reducing since the debate began x86 (CISC) processors are essentially RISC at their core with translation in decode Updated graph would probably show x86 (CISC) with higher perf than any RISC Used as a motivation why x86-64 (CISC) need not be radically overhauled 2 February 2005 /mtu/ee5970/f02/btd 9
10 X86-64 Intro Opteron (Sledgehammer) Server Market Athlon64 (Clawhammer) Consumer Market AMD is making the Hammer range backwardly compatible with current x86 code. adding 8 new 64-bit (now 16) general purpose registers (GPRs) 64-bit versions of the original 8 x86 GPRs. Has SSE & SSE2 support with 8 new (128-bit) SSE2 registers Increased memory addresses ability for large processor intensive software. 2 February 2005 /mtu/ee5970/f02/btd 10
11 64-bit flat virtual addressing x86-64 "long -mode" supports 64-bits of virtual address space, more memory than current computers (or super-computers) Opteron has 48-bits of virtual address space 40-bits of physical address space A single design platform for consumer and workstation level processor offerings 2 February 2005 /mtu/ee5970/f02/btd 11
12 Wider GPR's to 64-bits The x86-64 supports 64-bit integers so very large numbers can be handled accurately & quickly with Legacy mode support for x86 mode: 16 & 32-bit operating systems. Long mode support allows 64-bit operating system to execute 16 & 32-bit software. 64-bit Long mode for advanced 64-bit operation via x86-64 extensions. 64-bit Virtual address space. 2 February 2005 /mtu/ee5970/f02/btd 12
13 x86-64 Registers Adds 8 new (much needed) GPR SSE are DSP/Graphics operations for vectors of lowprecision values Most registers only available in new 64-bit Long mode 2 February 2005 /mtu/ee5970/f02/btd 13
14 x86-64 Operating Modes Three operating modes (2) modes are directly backward compatible (1) mode will continue to execute old operating systems Three modes enable performance improvement with existing hardware as new operating systems and software are developed and installed 2 February 2005 /mtu/ee5970/f02/btd 14
15 Opteron System design Significant Changes to Bus Topology Uses HyperTransport Protocol DRAM controller on the processor die 2 February 2005 /mtu/ee5970/f02/btd 15
16 AMD SledgeHammer codename become OPTERON Trademark ClawHammer codename became Athlon64 Trademark Systems were Demo ed as early as Feb 27, February 2005 /mtu/ee5970/f02/btd 16
17 IA - 64 IA-64 is a 64-bit architecture-a first for Intel. In IA-64 designs, instructions are scheduled by the compiler, not by the hardware. Much of the logic that groups, schedules, and tracks instructions is not needed thus simplifying the circuitry and promising to improve performance. EPIC Explicitly Parallel Instruction set Computing Not CISC, Not RISC but very much like VLIW
18 The Compiler s Goal Generate code to take advantage of Instruction Level Parallelism The whole point of EPIC is to generate code that can be executed in parallel Because of this, a compiler that simply works does not put out code that runs at average or reasonable speeds The processor optimizations have been moved to become a compiler responsibility The compiler makes an incredible difference in the performance of the processor This is bleeding edge compiler technology Operating systems and applications compiled on a functional compiler rather than a fully optimized compiler will probably be slower than current versions on current 32bit CPUs. 2 February 2005 /mtu/ee5970/f02/btd 18
19 IA-64 Strategies Extracting parallelism is difficult Existing architectures contain limitations that prevent sufficient parallelism on in-order implementations Strategy Allow the compiler to exploit parallelism by removing static scheduling barriers (control and data speculation) Enable wider machines through large register files, static dependence specification, static resource allocation 2 February 2005 /mtu/ee5970/f02/btd 19
20 Instruction Bundling Uses a form of VLIW architecture Referred to as EPIC Explicitly Parallel Instruction set Computing Three Instructions are combined into a 128-bit instruction bundle Facilitates Parallel Instructions. Instructions are executed in groups 2 February 2005 /mtu/ee5970/f02/btd 20
21 Processor State Directly accessible CPU state 128 x 65-bit General registers (GR) 128 x 82-bit Floating-point registers (FR) 64 x 1-bit Predicate registers (PR) 8 x 64-bit Branch registers (BR) Indirectly accessible CPU state Current Frame Marker (CFM) Instruction Pointer (IP) Control and Status registers 19 Application registers (AR) User Mask (UM) CPU Identifiers (CPUID) Performance Monitors (PMC,PMD) Memory 2 February 2005 /mtu/ee5970/f02/btd 21
22 Predication Branches interrupt control flow/scheduling Mispredictions limit performance Even with perfect branch prediction, small basic blocks of code cannot fully utilize wide machines Strategies Allow compiler to eliminate branches (and increase basic block size) with predication Reduce the number and duration of branch mispredicts by using compiler generated branch hints Allow compiler to schedule more than one branch per clock -multiway branch 2 February 2005 /mtu/ee5970/f02/btd 22
23 Predication Concepts Branching causes difficult to handle effects Istream changes (reduces fetching efficiency) Requires branch prediction hardware Requires execution of branch instructions Potential branch mispredictions IA-64 provides predication Allows some branches to be moved Allows some types of safe code motion beyond branches Basis for branch architecture and conditional execution 2 February 2005 /mtu/ee5970/f02/btd 23
24 Predication Example The Branch is eliminated and parallel (speculative) instructions are generated Increases fetch efficiency Eliminates Control Hazard 2 February 2005 /mtu/ee5970/f02/btd 24
25 Parallel Compares Parallel compares allow compound conditionals to be executed in a single instruction group. Example: if ( a && b && c ) {... } Assembly: cmp.ne p1 = ra,0 cmp.ne.and p1 = rb,0 cmp.ne.and p1 = rc,0 2 February 2005 /mtu/ee5970/f02/btd 25
26 Height Reduction Predication registers can significantly reduce the control dependencies in applications 2 February 2005 /mtu/ee5970/f02/btd 26
27 Prefetching 65 th bit of GPR s represents NaT NaT: Not-a-Thing Represents an exception in speculative state NaN: Not-a-Number Represents +/- infinity & indeterminate values in IEEE 754 Floating Point std. Loads can be hoisted out of basic block & up the instruction stream Architecturally knowledgeable Compiler can guess the appropriate number of cycles of prefetch With the 65 th bit representing speculative exception even USE of a value can be hoisted 2 February 2005 /mtu/ee5970/f02/btd 27
28 Value Speculation Enables Prefetching but has far more uses 2 February 2005 /mtu/ee5970/f02/btd 28
29 Rotating Register File Procedure calls interrupt scheduling/control flow Software modularity is standard Call overhead from saving/restoring registers Strategy Provide special support for software modularity Reduce procedure call/return overhead Register Stack Register Stack Engine (RSE) 2 February 2005 /mtu/ee5970/f02/btd 29
30 Rotating Registers 128 Integer registers and 128 Floating Point registers 32 Static registers and 96 Rotating registers. Similar to SPARC register windows Amount of rotating registers is programmable. Uses register renaming to implement the rotating registers. 2 February 2005 /mtu/ee5970/f02/btd 30
31 The Register Stack Procedures are stored on the register stack. Each procedure frame overlaps to simplify parameter passing between routines. 2 February 2005 /mtu/ee5970/f02/btd 31
32 Register Stack Engine (RSE) The RSE is used for two main functions The automation of register saves and restores in hardware across procedure calls. Maps the stack to memory. Its ability to be used to make use of unused memory bandwidth for fill and spill operations. 2 February 2005 /mtu/ee5970/f02/btd 32
33 Software Pipelining Rotating Register Bases Circular Buffer of General and FP Registers Loop Branches Decrement both RRBs Makes data transfer between stages transparent => same virtual registers are used in each loop iteration Advantages Traditionally performed through loop unrolling Lower overhead, less code, increased regularity Especially useful for integer code with small number of loop iterations 2 February 2005 /mtu/ee5970/f02/btd 33
34 Software Pipelining Software Pipelining Overlapping Loop Iterations 2 February 2005 /mtu/ee5970/f02/btd 34
35 Floating Point Architecture The 82-bit IA-64 floating point architecture enables a lot higher precision and range of values. Smaller rounding error iterative calculations converge faster 2 February 2005 /mtu/ee5970/f02/btd 35
36 Floating Point New Features Combined Multiply and Add operations improve performance. With 128 Registers, a lot more than its predecessor architectures, the IA-64 enables greater resource availability. 2 February 2005 /mtu/ee5970/f02/btd 36
37 32-bit Compatibility Itanium directly executes IA- 32 binary code Seamless Architecture allows full Itanium performance 2 February 2005 /mtu/ee5970/f02/btd 37
38 2 February 2005 /mtu/ee5970/f02/btd 38
39 Intel Itanium has been available in machines since 2001 Low volumes sold due to performance less than Pentium 4 on x86 applications Next generation IA-64 (McKinley) ITANIUM/2 promises higher performance Can an implementation demonstrate the advantage of ISA enhancement promises? 2 February 2005 /mtu/ee5970/f02/btd 39
40 The AMD Opteron processor 200 Series Server Benchmark Performance SPECint SPECfp Itanium 2 1.5GHz % Itanium 2 1.5GHz % AMD Opteron % AMD Opteron % Xeon 3.06GHz 1MB L % P4 3.2GHz 800FSB % P4 3.2GHz 800FSB % AMD Opteron % AMD Opteron 244 Xeon 3.06GHz % 100% Xeon 3.06GHz 1MB L3 Xeon 3.06GHz % 90% TPC-H 100GB TPC-H 300GB AMD Opteron 246 HP Alpha 1.0GHz % % AMD Opteron 246 (16 CPUs) PIII Xeon 900MHz (64 CPUs) HP Alpha 1.0GHz (16 CPUs) % % 98% TPC-H 100GB AMD Opteron 246 HP Alpha 1.0GHz Transactions per $10k TPC-H 300GB Transactions per $10k 28 20% % AMD Opteron 246 (16 CPUs) PIII Xeon 900MHz (64 CPUs) HP Alpha 1.0GHz (16 CPUs) % 32% % 2003 Advanced Micro Devices. AMD, the AMD Arrow Logo, AMD Opteron and any combinations thereof are trademarks of Advanced Micro Devices. SPEC and the benchmark names SPECfp, SPECint and SPECweb are registered trademarks of the Standard Performance Evaluation Corp. Competitive numbers shown reflect results published on as of August 5, For the latest SPEC results visit For full MMB2 results visit TPC-H data is current as of 8/5/03 and includes previously published TPC results. TPC-H data obtained from publicly available information and is subject to change without notice. For more information visit 2 February 2005 /mtu/ee5970/f02/btd 40
41 The AMD Opteron processor 200 Series SPECint _rate AMD Opteron 246 Itanium 2 1.5GHz Xeon 3.06GHz 1MB L3 AMD Opteron 244 Xeon 3.06GHz Server Benchmark Performance % 101% 100% 114% 114% SPECfp _rate Itanium 2 1.5GHz AMD Opteron 246 AMD Opteron 244 Xeon 3.06GHz 1MB L3 Xeon 3.06GHz % % 112% 100% % SPECjbb2000 Itanium 2 1.5GHz AMD Opteron 246 Xeon 3.06GHz 1MB L3 AMD Opteron 244 Xeon 3.06GHz MMB2 Itanium 2 1.5GHz Xeon 3.06GHz % AMD Opteron % % SPECweb 99_SSL 120% 120% 115% % 108% AMD Opteron % Xeon 3.06GHz % Itanium 2 N/A 2003 Advanced Micro Devices. AMD, the AMD Arrow Logo, AMD Opteron and any combinations thereof are trademarks of Advanced Micro Devices. SPEC and the benchmark names SPECfp, SPECint and SPECweb are registered trademarks of the Standard Performance Evaluation Corp. Competitive numbers shown reflect results published on as of August 5, For the latest SPEC results visit For full MMB2 results visit 2 February 2005 /mtu/ee5970/f02/btd 41
42 The AMD Opteron processor 800 Series SPECint _rate **846 Scores Estimated Server Benchmark Performance SPECfp _rate Itanium 2 1.5GHz % Itanium 2 1.5GHz % AMD Opteron 846** % AMD Opteron 846** % AMD Opteron % AMD Opteron % Xeon MP 2.8GHz Xeon MP 2.0GHz % 98% Xeon MP 2.8GHz Xeon MP 2.0GHz % 41% SPECjbb2000 SPECweb 99_SSL Itanium 2 1.5GHz AMD Opteron 846** Xeon MP 2.8GHz AMD Opteron % 100% 128% 120% Itanium 2 1.5GHz AMD Opteron 844 Xeon MP 2.8GHz % % 100% MMB2 TPC-C Xeon MP 2.8GHz % Itanium 2 1.5GHz 131, % AMD Opteron % Xeon MP 2.8GHz 84, % Itanium 2 N/A AMD Opteron , % 2003 Advanced Micro Devices. AMD, the AMD Arrow Logo, AMD Opteron and any combinations thereof are trademarks of Advanced Micro Devices. SPEC and the benchmark names SPECfp, SPECint and SPECweb are registered trademarks of the Standard Performance Evaluation Corp. Competitive numbers shown reflect results published on as of August 5, For the latest SPEC results visit For full MMB2 results visit TPC-C data is current as of 8/5/03 and includes previously published TPC results. TPC-C data obtained from publicly available information and is subject to change without notice. For more information visit 2 February 2005 /mtu/ee5970/f02/btd 42
43 Comments IA-64 is a unique ground-up ISA Will x86 performance suffer due to IA-64 core? Many unique ground-up ISAs have failed due to installed code base X86-64 is the next phase in a saga, with baggage from each phase 8080->8088->8086-> 268->386->MMX:SSE:3d!NOW ->586->x86-64 Will x86-64 enable competitive performance without the parallelism enhancements in IA-64 Other factors Cost, Power Consumption, Market Arrival, etc 2 February 2005 /mtu/ee5970/f02/btd 43
44 Slashdot The latest offerings in the Pentium 4 family now support AMD's x86-64 architecture, even though Intel is not willing to admit it very openly, by using cryptic names like EM64T and (gasp) IA- 32e. Intel's FAQ admits their implementation is basically compatible with x86-64, except for the minor differences that have always set Athlons and P4s apart. It's about time Intel jumped on AMD's bandwagon, since its homegrown 64-bit architecture seems not to be doing very well. 2 February 2005 /mtu/ee5970/f02/btd 44
45 References IA - 64 An Overview www-ist.massey.ac.nz/~crjessho/comp_arch/html/ia64.ppt Hot Chips Reading Assignments: "AMD: x86-64 Technology White Paper" Itanium Processor Microarchitecture 2 February 2005 /mtu/ee5970/f02/btd 45
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