Overview. Example 1: State Diagram. State Diagrams. CPEN Digital System Design. Spring 2007
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1 PEN igital System esign Spring 2007 hapter 6 - Sequential ircuits Sequential ircuit esign. Gerousis Logic and omputer esign Fundamentals, 3 rd Ed., Mano Prentice Hall harles Kime & Thomas Kaminski 2004 Pearson Education, Inc. Overview Part 1 - Storage Elements and nalysis eview of sequential circuits Types of sequential circuits Storage elements Latches Flip-flops Sequential circuit analysis State tables State diagrams Part 2 - Sequential ircuit esign Specification ssignment of State odes Implementation State iagrams Example 1: State iagram Label form: On circle with output included: state/output Moore type output depends only on state On directed arc with the output included: input/output Mealy type output depends on state and input Which type? iagram gets confusing for large circuits For small circuits, usually easier to understand than the state table x=0/y=0 0 0 x=0/y=1 x=0/y=1 1 0 x=0/y=
2 Moore and Mealy Models Example 2 Sequential ircuits or Sequential Machines are also called Finite State Machines (FSMs). Two formal models exist: Moore Model Named after E.F. Moore. Outputs are a function ONLY of states Usually specified on the states. Mealy Model Named after G. Mealy Outputs are a function of inputs N states Usually specified on the state transition arcs. In contemporary design, models are sometimes mixed Moore and Mealy What is the Next State Function/Equation? What is the Output Equation? What model is this FSM? Example 2 State Table/iagram The esign Procedure ( =t Z + 1) = X Y Specification Write a specification of the circuit Formulation - Obtain a state diagram or state table State ssignment - ssign binary codes to the states Flip-Flop Input Equation etermination - Select flip-flop types and derive flip-flop equations from next state entries in the table Output Equation etermination - erive output equations from output entries in the table Optimization - Optimize the equations Technology Mapping - Find circuit from equations and map to flip-flops and gate technology Verification - Verify correctness of final design 2
3 Formulation: Finding a State iagram In specifying a circuit, we use states to remember meaningful properties of past input sequences that are essential to predicting future output values. sequence recognizer is a sequential circuit that produces a distinct output value whenever a prescribed pattern of input symbols occur in sequence, i.e, recognizes an input sequence occurence. We will develop a procedure specific to sequence recognizers to convert a problem statement into a state diagram. Next, the state diagram, will be converted to a state table from which the circuit will be designed. Sequence ecognizer Example Example: ecognize the sequence 1101 Note that the sequence contains 1101 and "11" is a proper sub-sequence of the sequence. lso, the sequence contains 1101 as both an initial subsequence and a final subsequence with some overlap, i. e., or nd, the 1 in the middle, , is in both subsequences. The sequence 1101 must be recognized each time it occurs in the input sequence. Example: ecognize 1101 efine states for the sequence to be recognized: assuming it starts with first symbol, continues through each symbol in the sequence to be recognized, and uses output 1 to mean the full sequence has occurred, with output 0 otherwise. Starting in the initial state (rbitrarily named ""): dd a state that recognizes the first "1. State "" is the initial state, and state "" is the state which represents the fact that the "first" one in the input subsequence has occurred. The output symbol "0" means that the full recognized sequence has not yet occurred. Example: ecognize 1101 (continued) fter one more 1, we have: is the state obtained when the input sequence has two "1"s. Finally, after 110 and a 1, we have: Transition arcs are used to denote the output function (Mealy Model) Output 1 on the arc from means the sequence has been recognized To what state should the arc from state go? emember: ? 3
4 Example: ecognize 1101 (continued) learly the final 1 in the recognized sequence 1101 is a sub-sequence of It follows a 0 which is not a sub-sequence of Thus it should represent the same state reached from the initial state after a first 1 is observed. We obtain? Example: ecognize 1101 (continued) The state have the following abstract meanings: : No proper sub-sequence of the sequence has occurred. : The sub-sequence 1 has occurred. : The sub-sequence 11 has occurred. : The sub-sequence 110 has occurred. The on the arc from to means that the last 1 has occurred and thus, the sequence is recognized. Example: ecognize 1101 (continued) The other arcs are added to each state for inputs not yet listed. Which arcs are missing? nswer: "0" arc from "0" arc from "1" arc from "0" arc from. Example: ecognize 1101 (continued) State transition arcs must represent the fact that an input subsequence has occurred. Thus we get: Note that the 1 arc from state to state implies that State means two or more 1's have occurred. * : The occurrence of the first 1 in the sequence * 4
5 Formulation: Find State Table Formulation: Find State Table From the State iagram, we can fill in the State Table. There are 4 states, one input, and one output. We will choose the form with four rows, one for each current state. From State, the 0 and 1 input transitions have been filled in along with the outputs. Present State Next State Output x=0 x=1 x=0 x=1 0 0 From the state diagram, we complete the state table. Present Next State Output State x=0 x=1 x=0 x= State ssignment = 0 0, = 0 1, = 1 1, = 1 0 The resulting coded state table: Part 2- Sequential ircuit esign Part 2 - Sequential ircuit esign Specification ssignment of State odes Implementation 5
6 State ssignment FF I/O Equations = 0 0, = 0 1, = 1 1, = 1 0 The resulting coded state table: Maps for Input and output ( 1) =Σm(3,6,7) ( 1) =Σm(1,3,5,7) Z(,, X ) =Σm(5) ( 1) =Σm(3,6,7) ( 1) =Σm(1,3,5,7) Z(,, X ) =Σm(5) Map Technology Mapped ircuit - Final esult Library: Flip-flops with eset (not inverted) NN gates with up to 4 inputs and inverters X Initial ircuit: Y 1 Y 2 Z X Y 1 Y 2 Z lock eset lock eset 6
7 Table 6-7 ecause of their lesser importance in contemporary design relative to -flip-flops, analysis and design examples for JK and T flip flops circuits are given on the companion website. 7
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