Microcontroller Systems. ELET 3232 Topic 21: Partial and Full Memory Decoding

Transcription

1 Microcontroller Systems ELET 3232 Topic 21: Partial and Full Memory Decoding 1

2 Agenda To become familiar with the concepts of memory expansion, the data, the address bus, and control signals To design embedded systems expanded memory systems using: Full decoding Partial decoding 2

3 Introduction In the examples in the preceding topic, the RAM chips were completely decoded Also referred to as Fully Decoded or Full Decoding Meaning that each RAM chip (or bank) would respond to one and only one range of addresses The lower ten address lines (A 0 A 9 ) selected one of the 1024 addressable memory locations on each chip (or bank) The upper six address lines (A 10 A 15 ) select one of the RAM chips (or banks) 3

4 Binary Address The beginning and ending address for each RAM chip of Example 1 is shown below Notice that A 0 A 9 may take on any value (a 1 or a 0) A 10 A 15 remain unchanged for that RAM chip 4

5 Full Decoding Notice that A 10 and/or A 11 change states when selecting one of the four RAM chips A 12 A 15 are always low Every address line is used in decoding these addresses Each RAM chip responds to only one range of addresses 5

6 Full/Partial Decoding If the enable input to the decoder was grounded instead of using A 12 A 15, then A 12 A 15 would have no affect on selecting RAM0 RAM3 Partial Decoding Full Decoding 6

7 Partial Decoding If the enable input to the decoder was grounded then the decoder would always be enabled. If A 10 and A 11 are both low, RAM0 would respond no matter the state of A 12 A 15 7

8 Partial Decoding In this table, the x s under A 0 A 9 mean that these address lines are directly connected to the RAM IC and have no effect on selecting the IC 8

9 Partial Decoding Because the enable is grounded, A 12 A 15 can be at any state and RAM0 will still be selected if A 11 and A 10 are low 9

10 Partial Decoding This is OK, as long as RAM0 is the only memory IC (or memory bank) that responds to these addresses. 10

11 Bus Contention It is very important that only one bank of memory respond to any address If the circuit is incorrectly designed and more than one memory bank responds to an address, we have bus contention Bus contention is a condition in which more than one memory device is attempting to interact with the data bus This condition will cause: Overloading of the data bus Incorrect data being read or written (Bus contention is BAD) 11

12 In-Class Exercise In-Class Exercise Develop the address map (address table) for a memory system that has 16k bytes of RAM and 2k bytes of ROM Use full decoding The RAM chips available are 4k x 8 The starting address for RAM should be $0000 RAM is contiguous The ROM is 2k x 8 and should start at address $

13 Solution (pg 1) RAM 4k x 8 log = 12 A 0 A 11 would, therefore, be directly connected to each RAM chip 8 data lines 13

14 Solution (pg 2) ROM 2k x 8 log = 11 A 0 A 10 would, therefore, be directly connected to the ROM chip 8 data lines 14

15 Solution (pg 3) RAM: we have 4 RAM ICs we need 2 bits (A 12 & A 13 ) to choose between 4 RAM ICs Count from 0 to 3 (RAM0 to RAM3) on A 12 & A 13 Beginning Address replace the Xs with 0 Ending Address replace the Xs with 1 15

16 Solution (pg 4) RAM: we have 4 RAM ICs we need 2 bits (A 12 & A 13 ) to choose between 4 RAM ICs Count from 0 to 3 (RAM0 to RAM3) on A 12 & A 13 Use all 0s for A 14 & A 15 for full decoding RAM start address was $

17 Solution (pg 4) ROM was to start at $4000 2k x 8: needs 11 address lines Others should ensure we are addressing $

18 Solution (pg 5) The RAM can be decoded with a 2-to-4 decoder A 12 A 15 can be used for decoding the RAM chips. A 14 and A 15 are always low so they will be used to enable the decoder. A 12 and A 13 count the four banks of memory, so they will be used as the inputs to the decoder 18

19 Solution (pg 6) The RAM can be decoded with a 2-to-4 decoder A 12 A 15 can be used for decoding the RAM chips. A 14 and A 15 are always low so they will be used to enable the decoder. A 12 and A 13 count the four banks of memory, so they will be used as the inputs to the decoder The outputs will be connected to the enable pins on the RAM ICs 19

20 Address Strobe So, what is this AS signal? 20

21 Address Strobe So, what is this AS signal? AS is a signal used to let external circuitry know that an address is on the external address bus. AS is also used to latch the lower address lines, so that Port C can be used for data for the remainder of the clock cycle (we ll get to this soon). So, AS is included in the decoding circuits above to ensure that the decoding circuitry is disabled until AS is low. This will prevent memories from turning off and on as addresses change on the address bus. 21

22 Memory Spaces Processors using the Harvard architecture have separate memory spaces for: Program memory Data memory I/O space Stack or heap The processor has separate control signals to indicate which address space is to be used This may be done with a separate signal line that goes active when a particular space is being addressed Or several status lines that, when decoded, define the appropriate memory space

23 Harvard Architecture The 8051 family uses the Harvard architecture: There will be more than one unique location with the same address The control signals specify which is being accessed Data

24 Motorola 680x0 The Motorola 680x0 family: There is one memory space each has a unique address I/O addresses are also in this space Memory mapped I/O

25 Decoders The address lines and control lines are decoded to provide individual chip enable signals to memory and I/O A standard n-line to 2n-line decoder is commonly used to decode the address lines A common decoder is the 74LS138, a 3-to-8 line decoder that drives one of eight output lines low, depending on the three bit binary number on the input, and its enable input.

26 74138 Decoder This is a diagram of the 74138, 3 to 8 decoder another popular decoding chip. It has 2 active low and 1 active high enable pins. It has 3 select inputs. When an output is selected and all of the enable pins are at an active state, the output pin will go low, otherwise it is high 26

27 Address Inputs With 16 address lines there are 64K unique locations in a memory address space This would require eight memory ICs if each one contains 8K locations By connecting the three decoder inputs to the most significant bits of the address bus

28 Memory Enable Inputs With 16 address lines there are 64K unique locations in a memory address space This would require eight memory ICs if each one contains 8K locations By connecting the three decoder inputs to the most significant bits of the address bus and each of the eight decoder outputs to a memory chip enable

29 Device Selection With 16 address lines there are 64K unique locations in a memory address space This would require eight memory ICs if each one contains 8K locations By connecting the three decoder inputs to the most significant bits of the address bus and each of the eight decoder outputs to a memory chip enable one of the eight memory devices will be selected for any given address

30 Memory Mapped I/O I/O may be addressed in the same way Here we have a single bit input port and a single bit output port Each responds to a different address than memory or the other port

31 Memory Mapped I/O I/O may be addressed in the same way Here we have a two bit input/output port Each responds to the same address than memory or the other port

32 Memory Mapped I/O I/O may be addressed in the same way Here we have a two bit input/output port Each responds to the same address than memory or the other port Of course, other I/O ICs may be connected as well: parallel ports serial ports D-to-A converters

33 Clock We ll start discussing timing in the next topic For this system, the microcontroller will: Places addresses on the outputs (address bus) during the low state of the clock Data is transmitted (either read or written) during the high state of the clock 33

34 Controller So, the controller side of the circuit looks like: Note that the write enable signal is the combined R/W and Clock 34

35 Controller So, the controller side of the circuit looks like: This is the latch. It holds the lower address signals through the whole clock cycle so that data can be transmitted during the high state of the clock. Note that the write enable signal is the combined R/W and Clock 35

36 RAM The RAM connections look like: RAMx is the RAM0, RAM1, RAM2, or RAM3 signal from the decoder 36

37 RAM The RAM connections look like: RAMx is the RAM0, RAM1, RAM2, or RAM3 signal from the decoder The write enable signal is the same as the one on the previous slide: the combined R/W and Clock 37

38 RAM The RAM connections look like: RAMx is the RAM0, RAM1, RAM2, or RAM3 signal from the decoder The write enable signal is the same as the one on the previous slide: the combined R/W and Clock The R/W signal is connected to the Output Enable (OE) signal because it instructs the RAM to place data on the bus when low 38

39 ROM The ROM connections are almost identical to the RAM: We have the ROM enable and the output enable. We don t have a write enable because this ROM is not written to 39

40 The Complete Diagram We have the connections to the address bus 40

41 The Complete Diagram We have the connections to the address bus. We have the connections to the data bus 41

42 The Complete Diagram We have the connections to the address bus. We have the connections to the data bus We have the control signals going in/out of the Decoding Logic Box as well as the AS and WE 42

43 The Complete Diagram We have the connections to the address bus. We have the connections to the data bus We have the control signals going in/out of the Decoding Logic Box as well as the AS and WE In the Decoding Logic Box we have: 43

44 Summary Discussed the concepts of memory expansion, the data, the address bus, and control signals Discussed embedded systems memory systems design using: Full decoding Partial decoding 44