Computer Organization

Transcription

1 5 Computer Organization 5.1 Foundations of Computer Science & Cengage Learning

2 Objectives After studying this chapter, the student should be able to: List the three subsystems of a computer. Describe the role of the central processing unit (CPU). Describe the fetch-decode-execute phases of a cycle. Describe the main memory and its addressing space. Define the input/output subsystem. Understand the interconnection of subsystems. Describe different methods of input/output addressing. Distinguish the two major trends in the design of computers. Understand how computer throughput can be improved using pipelining and parallel processing. 5.2

3 three broad categories or subsystems that make up a computer: the central processing unit (CPU), the main memory and the input/output subsystem. 5.3 Computer hardware (subsystems)

4 5-1 CENTRAL PROCESSING UNIT The central processing unit (CPU) performs operations on data. In most architectures it has three parts: an arithmetic logic unit (ALU) a control unit a set of registers (fast storage locations) 5.4

5 Registers Registers are fast stand-alone storage locations that hold data temporarily. Multiple registers are needed to facilitate the operation of the CPU Data registers Instruction register Program counter 5.5

6 5-2 MAIN MEMORY Main memory is the second major subsystem in a computer It consists of a collection of storage locations, each with a unique identifier, called an address. Data is transferred to and from memory in groups of bits called words. A word can be a group of 8 bits, 16 bits, 32 bits or 64 bits (and growing). If the word is 8 bits, it is referred to as a byte. 5.6

7 Main Memory Address Space A word 5.7

8 Address Space each word is identified by an address. The total number of uniquely identifiable locations in memory is called the address space For example, a memory with 64 kilobytes and a word size of 1 byte has an address space that ranges from 0 to 65,

9 i Memory addresses are defined using unsigned binary integers. 5.9

10 Example 5.1 A computer has 32 MB (megabytes) of memory. How many bits are needed to address any single byte in memory? Solution: The memory address space is 32 MB, or 2 25 ( ). This means that we need log , or 25 bits, to address each byte. 5.10

11 Example 5.2 A computer has 128 MB of memory. Each word in this computer is eight bytes. How many bits are needed to address any single word in memory? Solution: The memory space is 128 MB, which means 2 27 bytes Each word is eight (2 3 ) bytes, which means that we have 2 24 words. So we need log , or 24 bits, to address each word. 5.11

12 Memory Types 5.12 Two main types of memory exist: RAM and ROM. Random access memory (RAM) Static RAM (SRAM) Dynamic RAM (DRAM) Read-only memory (ROM) Fast but expensive Slow but inexpensive Programmable read-only memory (PROM). Erasable programmable read-only memory (EPROM). Electrically erasable programmable read-only memory (EEPROM).

13 Memory Hierarchy Computer users need a lot of memory, especially memory that is very fast and inexpensive. very fast memory is usually not cheap. A compromise needs to be made 5.13

14 Cache Memory Cache memory, which is normally small in size, is placed between the CPU and main memory Cache memory is faster than main memory, but slower than the CPU and its registers 5.14

15 5-3 INPUT/OUTPUT SUBSYSTEM the input/output (I/O) subsystem allows a computer to communicate with the outside world and to store programs and data even when the power is off Input/output devices can be divided into two broad categories: non-storage and storage devices. 5.15

16 Non-storage devices allow the CPU/memory to communicate with the outside world, but they cannot store information. Keyboard and monitor Printer 5.16

17 Storage devices can store large amounts of information to be retrieved at a later time. cheaper than main memory, and their contents are nonvolatile (not erased when the power is turned off) sometimes referred to as auxiliary storage devices. We can categorize them as either magnetic or optical. 5.17

18 Magnetic Disk Surface is divide into tracks, and each track is divided into sector. Rotational speed: how fast the disk is spinning Seek time: time to move the read/write head to the desired track Transfer time: time to move data 5.18

19 Magnetic Tape Surface is divided into 9 tracks, each location on a track storing 1 bit info. Sequential access device Slower and cheaper than a magnetic disk 5.19

20 Optical Storage Devices: CD-ROM Read using a low-power laser beam Beam is reflected by a aluminum surface Reflected twice when it encounters a pit, one by the pit boundary and once by the aluminum boundary The pit depth is chosen to exactly ¼ of the beam length Sensor detects less light when the location is a pit 5.20

21 High-power infrared laser 鑄模 鋁 聚碳酸酯樹脂 5.21

22 5.22

23 CD-ROM Format Error-correction code 5.23

24 Making a CD-R (write once, read many) 金 染料 5.24

25 Making a CD-RW (rewritable) 合金 結晶 非晶 5.25

26 DVD Capability Pits are smaller Tracks are closer Use red laser instead of infrared 5.26

27 5-4 SUBSYSTEM INTERCONNECTION explore how the three subsystems (CPU, main memory, and I/O) are interconnected 5.27

28 Connecting CPU and memory The CPU and memory are normally connected by three groups of connections, each called a bus: data bus, address bus and control bus 5.28

29 Buses Data bus One connection for a bit (32 bits are needed for a 32-bit word) Address bus Number of connections depends on the address space of the memory Control bus m connections for 2 m control actions (read/write, ) 5.29

30 Connecting I/O devices I/O devices cannot be connected directly to the buses that connect the CPU and memory, because the nature of I/O devices is different from the nature of CPU and memory. I/O devices are electromechanical, magnetic, or optical devices, whereas the CPU and memory are electronic devices. I/O devices operate at a much slower speed than the CPU/memory. 5.30

31 I/O Controllers Input/output devices are attached to the buses through input/output controllers or interfaces. one specific controller for each I/O device 5.31

32 SCSI Controller parallel interface with 8, 16, or 32 connections Each device must have a unique ID 5.32

33 FireWire (IEEE 1394) controller serial interface 5.33 No terminator is needed

34 USB Controller serial interface Tree-like topology 5.34

35 Addressing input/output devices The CPU usually uses the same bus to read data from or write data to main memory and I/O device. The only difference is the instruction. If the instruction refers to a word in main memory, data transfer is between main memory and the CPU. If the instruction identifies an I/O device, data transfer is between the I/O device and the CPU. two methods for handling the addressing of I/O devices: isolated I/O and memory-mapped I/O 5.35

36 Isolated I/O addressing Instructions used to read/write memory are different from those used to read/write I/O devices Each I/O device has its own address (can overlap with a memory address) 5.36

37 Memory-mapped I/O addressing CPU treats each register in the I/O controller as a word in memory Memory instructions can be used by I/O devices Part of memory address space is allocated to registers in I/O controllers 5.37

38 5-5 PROGRAM EXECUTION general-purpose computers use a set of instructions called a program to process data. A computer executes the program to create output data from input data. Both the program and the data are stored in memory. 5.38

39 Machine cycle The CPU uses repeating machine cycles to execute instructions in the program, one by one, from beginning to end. A simplified cycle can consist of three phases: fetch, decode and execute 5.39

40 Input/output operation Commands are required to transfer data from I/O devices to the CPU and memory. Because I/O devices operate at much slower speeds than the CPU, the operation of the CPU must be somehow synchronized with the I/O devices. Three methods have been devised for this synchronization: programmed I/O, interrupt driven I/O, and direct memory access (DMA). 5.40

41 Programmed I/O The CPU waits for the I/O device CPU time is wasted to or from memory 5.41

42 Interrupt driven I/O to or from memory The CPU does not test the status of the I/O device continuously 5.42

43 DMA Connection to the General Bus Transfers a large block of data between a high-speed I/O device and memory without passing it through the CPU 5.43

44 DMA Input/Output The CPU is idle only during the data transfer between the DMA and memory 5.44

45 5-6 DIFFERENT ARCHITECTURES The architecture and organization of computers has gone through many changes in recent decades. In this section we discuss some common architectures and organization that differ from the simple computer architecture we discussed earlier 5.45

46 Complex Instruction Set Computer (CISC) have a large set of instructions, including complex ones Programming CISC-based computers is easier than in other designs because there is a single instruction for both simple and complex tasks. Programmers, therefore, do not have to write a set of instructions to do a complex task. 5.46

47 Reduced Instruction Set Computer (RISC) have a small set of instructions that do a minimum number of simple operations. Complex instructions are simulated using a subset of simple instructions. Programming in RISC is more difficult and time-consuming most of the complex instructions are simulated using simple instructions 5.47

48 Pipelining the next instruction can start before the previous one is finished improve the throughput (the total number of instructions performed in each period of time) 5.48

49 Parallel processing a single computer with multiple control units, multiple arithmetic logic units and multiple memory units. 5.49

50 5.50 SISD Organization

51 SIMD Organization (14, 25, 17,, -9) + (22, 32, 81,, 7) 5.51

52 MISD Organization Has never been implemented 5.52

53 MIMD Organization Several tasks can be performed simultaneously Can use a single shared memory or multiple memory sections 5.53

54 5-7 A SIMPLE COMPUTER 5.54 Use memory-mapped addresses

55 Instruction Set a set of sixteen instructions (14 used) 5.55

56 5.56

57 Processing the Instructions A machine cycle is made of three phases: fetch, decode and execute During the fetch phase, the instruction whose address is determined by the PC is obtained from the memory and loaded into the IR During the decode phase, the instruction in IR is decoded and the required operands are fetched from the register or from memory During the execute phase, the instruction is executed and the results are placed in the appropriate memory location or the register 5.57

58 An Example add two integers A and B and create the result as C integers are in two s complement format the first two integers are stored in memory locations (40) 16 and (41) 16 and the result should be stored in memory location (42)

59 5.59 In the language of our simple computer, these five instructions are encoded as:

60 Storing Program and Data We can store the five-line program in memory starting from location (00) 16 to (04) 16. the data needs to be stored in memory locations (40) 16, (41) 16, and (42) 16. Our computer uses one cycle per instruction, so we need five cycles 5.60

61 5.61 Cycle 1: R 0 M 40

62 5.62 Cycle 2: R 1 M 41

63 5.63 Cycle 3: R 2 R 0 + R 1

64 5.64 Cycle 4: M 42 R 2

65 5.65 Cycle 5: HALT

66 Another Example: Read & Write Modifications to the program: enter the first two integers into memory using an input device such as keyboard (a read operation) display the third integer through an output device such as a monitor (a write operation) 5.66

67 5.67 Modifications

68 The Read Operation In our computer we can simulate read operation using the LOAD instruction. LOAD reads data input to the CPU. We need two instructions to read data from keyboard into memory The input operation must always read data from an input device into memory 5.68

69 The Write Operation In our computer we can simulate write operation using the STORE instruction STORE write data from the CPU. We need two instructions to write data out of memory to monitor The output operation must always write data from memory to an output device. 5.69

70 The Program is Coded As Operations 1 to 4 are for input it waits for the user to input two integers on the keyboard and press the enter key Operations 9 and 10 are for output. It displays the result on the monitor. 5.70