Cost of a Chip. Example: An IBM chip. Parallel Scan Output Compaction. Parallel Scan. Illinois Scan Architecture. Cost of Testing Semiconductor Chips
|
|
|
- Leonard Gilbert
- 7 years ago
- Views:
Transcription
1 Illinois Architecture Janak. Patel Center for Reliable and igh-performance Computing University of Illinois at Urbana-Champaign Cost of a Chip 3mm wafer will give ~1cm 2 chips Material Costs (wafer, copper etc) ~5% Fab amortization cost ($3B/fab) plus Fab operational cost ~25% Personnel cost ~2% Package Cost ~% Testing Cost ~4%!!! 25 Janak. Patel 2 Cost of Testing Semiconductor Chips Three main variable components Test Application Time When amortizing the cost of a tester over all chips, higher test time results in to higher actual cost Rule of thumb: 1 second per chip! Test Data Volume Low and medium cost testers have limited storage Tester Pins Cost of a tester is directly proportional to the number of pins it supports 3 Example: An IBM chip million gates (logic only, RAM not included) 25k Flip-Flops Full design, all FFs connected as shift register in 25, ffs out Test Vectors Test Application Time: x25k = 1.5 cycles at Mz scan speed it takes 1.5 Seconds! at 5Mz scan speed it takes 3.5 Seconds Tester memory required: x25k = 1.5 bits 4 Parallel Parallel Output Compaction -in Parallel Chains by 25 FFs -out -in Parallel Chains by 25 FFs output compactor scan-in pins! scan-out pins! A Combinational Compactor is a tree of XOR gates Reduces Test Vector Load time by a factor of! Channels on a Tester range from to 2 5 A Sequential Compactor is a Linear Feedback Shift Register with multiple parallel inputs XORed. Also called a Multiple Input Signature Analyzer (MISR) 6
2 Parallel - Summary Test Vector Compaction loading time can be reduced by dividing the single scan chain in to parallel scan chains Some Observations Output Compaction is well established Number of scan chains is limited by the availability of pins on a chip and tester scan channels Additional pins on an embedded core require more routing in the SOC Parallel has no impact on test data volume For example, all 4 ISCAS 85 and ISCAS89 (full scan) circuits, sizes of the test sets generated by MinTest (amzaoglu and Patel, ICCAD 1998, pp ) meets Lower bounds for 31 out of 4 ISCAS circuits. This shows that Compaction has already reached theoretical lower bounds in many instances So we must look for other solutions beyond vector compaction Test Vectors Lower Min Bound Test C C C S S S S BIST: STUMPS Architecture Limitations of Logic BIST P.. Bardell and W.. McAnney, Self-Testing of Multichip Logic Modules, Proc. Of Int. Test Conf., pp. 2-24, Nov (used by IBM for multi-chip-modules) L F S R Linear Feedback Shift Register Phase Shifter Chain Chain Chain Chain Under Test This has the same limitations as any other BIST based scheme M I S R Multiple Input Signature Register 9 BIST is excellent for Data Volume, But Lower Fault Coverage. Test Point insertion and/or additional logic in test generator is required to cover Random Resistant Faults Design Modification needed to permit any arbitrary test pattern Tri-State logic must be fully decoded No floating bus is permitted, since unknown values can corrupt the signature Switching activities of various modules, and hence the power, cannot be easily controlled Will almost always increase the tester time! Failure Diagnosis becomes extremely difficult Proposed New Method Illinois Architecture Illinois Architecture Applicable to full-scan embedded cores and fullscan stand-alone chips Addresses all issues raised earlier - Low test application time, low pin overhead, and low test data volume Does not have any of the limitations of the BIST No test point insertions and No design modifications! Undesirable test vectors can be filtered, e.g., Vectors that produce Tri-State Conflicts, Unknown value generation, or igh switching activity 11 in in Take a Serial 1. Divide it up into several chains keeping the same -in pin 2. Add a MISR to compact the outputs MISR out out 12
3 Cycles Circ uit Illinois Untestable Faults in Illinois -in pin Internal Chains Output Compactor scan in In the figure shown on left, all three scan chains will have identical test vectors Therefore, only applicable test vectors are and 111 for the AND gate Test vectors, and 1 cannot be applied due to Broadcast constraint This makes three faults on the AND gate Untestable In practice, how serious is this problem? ow many faults become untestable? Additional Untestable Faults Two Test Modes of Illinois Illinois puts constraints on inputs Cannot generate tests for some of the faults that are testable under normal scan The number of such Additional Untestable Faults is surprisingly small even for arbitrary partition! Experimental Data for Chain divided into 16 chains (arbitrary partition), with a single scan input Untestable Faults ILS-132 ILS-1585 ILS ILS-3841 ILS In 1. Broadcast Test Mode Chain 1 Chain 2 Chain n M I S R 1. Reduces Time by a factor of n 2. Reduces Data by a factor of n But may require many more vectors and may reduce fault-coverage! Out In 2. Serial Test Mode Chain 1 Chain 2 Chain n Mode 2 Used for covering the loss of fault-coverage in the Broadcast Mode enerates top-off vectors. M I S R Out Number of Test Vectors Number of Test Cycles Vectors fs132 ILS-132 scan vectors broadcast vectors fs1585 ILS-1585 fs35932 ILS fs3841 ILS-3841 fs38584 ILS Versions: fs = full scan, and ILS = Illinois, DIV16 1 2, 15, 15, 125,, 5, 5, 25, fs132 ILS-132 scan cycles broadcast cycles fs1585 ILS-1585 fs35932 ILS fs3841 ILS-3841 Versions: fs = full scan, and ILS = Illinois, DIV16 fs38584 ILS
4 45, 4, 35, Illinois Data Volume Test Data Broadcast Test Data Illinois internal scan chains Data Bits 3, 25, 2, 15, scan-in pin, 5, fs132 fs1585 fs35932 fs3841 fs38584 Versions: fs = full scan, and ILS = Illinois, DIV16 19 output compactor 2 external scan-in pins Illinois with multiple pins internal scan chains output compactor 21 Case Study at Texas Instruments Original : 15K logic gates, 93 scan flip-flops 9 Vectors, 94.25% stuck-at fault coverage Illinois Version DIV16 DIV24 DIV32 Broadcast Vectors 15, 14, 12, Broadcast Fault Coverage 94.8% 94.9% 93.8% Additional Untestable Faults Serial Vectors needed Serial Broadcast Fault Vectors Coverage needed % 6% 3% Data Volume Factor Similar reduction was also found in Transition Fault Data Frank su, Ken Butler and Janak Patel, A Case Study on the Implementation of the Illinois Architecture, Int. Test Conf. Oct IBM Data using Illinois (OPMISR+) Design Chip1 Chip2 Chip3* ate Count 1.M 2.1M 15k flip-flops 23k 31k 41k Test Time 13x 38x 21x Chip4* 1.2M 65k 8x 12x * These chips already had their scan divided by customer x Test Volume 2x 54x.scan fan-out, which is sometimes informally referred to as Illinois [ix]. In the Cadence ATP tools we refer to this as OPMISR+. Data and quote From: Test Compression Methods in Cadence Encounter Test Design Edition, Technology Application Note, December 23 Intel Data on Illinois From a Paper by D. Wu et. al. of Intel, published in 23 Int. Test Conf. The first test chip has 81 scan-in and 81 scan-out channels, we use Illinois with 4 scan-in and 81 scan-out. The results are quite surprising: both methods got the same test coverage. We have implemented Illinois scan into one of the microprocessors, but the silicon results will not be ready for the timing of this year s ITC
5 More Data on Illinois M ates, 25k flip-flops, test vectors Illinois in CAD Tools Cadence (formerly IBM) Illinois on their patented OPMISR is called OPMISR+ Syntest Illinois is called Virtual Synopsis ATP Tools understand and support Illinois Mentor raphics No Illinois! Proprietary tool called TestCompress Source: V. Chickermane, B. Fautz and B. Keller, Channel-Masking Synthesis for Efficient On-Chip Test Compression, Int. Test Conf., Illinois with multiple pins Large Industrial s have used Illinois with multiple pins IBM ASIC-4 chip (Design and Test, Sept. 22, pp. 65-2) 1.14 million gates, 46 pins, 269 internal chains Intel chips (Int. Test Conf., Sept. 23, pp ) ASIC-1, 4 pins, 81 internal chains ASIC-2, 4 pins, 96 internal chains Next generation microprocessor (no data given) All of the above scan-chain groupings are ad-hoc! Optimal rouping of Chains scan-in pins scan chains Objective: Minimize number of -In Pins without loss in fault coverage Compatibility among Chains Compatibility between two scan cells Two inputs (scan cells) are compatible if and only if no fault becomes untestable as a result of tying the two cells to a single input (Chen&upta, ITC 1995) Compatibility between two scan chains Two chains are compatible if and only if every pair of scan-cells that receive the same broadcast value are compatible (amzaoglu&patel, FTCS 1999) Determination of all pair wise compatibilities is computationally very expensive Resort to an inexpensive algorithm which gives a subset of all compatible pairs Incompatibilities from a Test Set A Partially Specified Test Vector, 2-bits long folded on to 5 chains Chain 1x xx1 x1x 11 xx11 1 x a No conflicting values found x x 1 b x 1 x c 1 1 d x x 1 1 e 1x xx1 x11x 11 xx11 Chains a and c are incompatible, so are chains c and d 1 x a x x 1 b x 1 1 x c 1 1 d x x 1 1 e 29 3
6 Example of Chain rouping Dual-mode Illinois iven Incompatible Pairs: AB, AD, A, BD, BE, BF, CE, CF, EF, E, E, F Construct a raph with Nodes=Chains and Edges=Incompatibility A A B B A B C D E F A B C D E F C D E F Single Pin Broadcast Mode roup Mode C D E F Perform raph Coloring Algorithm Conflict-free Chain rouping Some Results on Pin Illinois : Summary s132.1 s no. of Chains no. of Pins Factor A simple DFT technique, ideal for reducing test costs for large chips Significant reduction in test application time, test data and test pins without loss in fault coverage Even a dumb partition is very effective! For very large chips, 2 fold reduction is likely! s3841 s Things should be made as simple as possible, but not any simpler Albert Einstein More information on Illinois 1. I. amzaoglu and J.. Patel, Reducing test application time for full-scan embedded cores, Proc. 29th Int. Symp. On Fault-Tolerant Computing (FTCS-29), pp.26-26, June F. su, K. Butler and J.. Patel, A case study on the implementation of Illinois Architecture, Proc. Int. Test Conf. pp , October A.R. Pandey and J.. Patel, An incremental algorithm for test generation in Illinois Architecture based designs, Proc. Of Design Automation and Test in Europe (DATE), pp , March A.R. Pandey and J.. Patel, Reconfiguration techniques for reducing test time and test data volume in Illinois Architecture based designs, IEEE VLSI Test Symp. (VTS), pp. 9-15, April M.A. Shah and J.. Patel, Enhancement of the Illinois Architecture for Use with Multiple Inputs, IEEE Computer Society Annual Symposium on VLSI, pp , Feb
Power Reduction Techniques in the SoC Clock Network. Clock Power
Power Reduction Techniques in the SoC Network Low Power Design for SoCs ASIC Tutorial SoC.1 Power Why clock power is important/large» Generally the signal with the highest frequency» Typically drives a
Design Verification & Testing Design for Testability and Scan
Overview esign for testability (FT) makes it possible to: Assure the detection of all faults in a circuit Reduce the cost and time associated with test development Reduce the execution time of performing
Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression
Test esource Partitioning and educed Pin-Count Testing Based on Test Data Compression nshuman Chandra and Krishnendu Chakrabarty Department of Electrical and Computer Engineering Duke University, Durham,
Testing Low Power Designs with Power-Aware Test Manage Manufacturing Test Power Issues with DFTMAX and TetraMAX
White Paper Testing Low Power Designs with Power-Aware Test Manage Manufacturing Test Power Issues with DFTMAX and TetraMAX April 2010 Cy Hay Product Manager, Synopsys Introduction The most important trend
VLSI Design Verification and Testing
VLSI Design Verification and Testing Instructor Chintan Patel (Contact using email: cpatel2@cs.umbc.edu). Text Michael L. Bushnell and Vishwani D. Agrawal, Essentials of Electronic Testing, for Digital,
Testing of Digital System-on- Chip (SoC)
Testing of Digital System-on- Chip (SoC) 1 Outline of the Talk Introduction to system-on-chip (SoC) design Approaches to SoC design SoC test requirements and challenges Core test wrapper P1500 core test
Encounter DFT Architect
Full-chip, synthesis-based, power-aware test architecture development Cadence Encounter DFT Architect addresses and optimizes multiple design and manufacturing objectives such as timing, area, wiring,
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths N. KRANITIS M. PSARAKIS D. GIZOPOULOS 2 A. PASCHALIS 3 Y. ZORIAN 4 Institute of Informatics & Telecommunications, NCSR
Design Verification and Test of Digital VLSI Circuits NPTEL Video Course. Module-VII Lecture-I Introduction to Digital VLSI Testing
Design Verification and Test of Digital VLSI Circuits NPTEL Video Course Module-VII Lecture-I Introduction to Digital VLSI Testing VLSI Design, Verification and Test Flow Customer's Requirements Specifications
Test compression bandwidth management in system-on-a-chip designs
Politechnika Poznańska Wydział Elektroniki i Telekomunikacji Poznań University of Technology Faculty of Electronics and Telecommunications Ph. D. Thesis Test compression bandwidth management in system-on-a-chip
What is a System on a Chip?
What is a System on a Chip? Integration of a complete system, that until recently consisted of multiple ICs, onto a single IC. CPU PCI DSP SRAM ROM MPEG SoC DRAM System Chips Why? Characteristics: Complex
Introduction to VLSI Testing
Introduction to VLSI Testing 李 昆 忠 Kuen-Jong Lee Dept. of Electrical Engineering National Cheng-Kung University Tainan, Taiwan, R.O.C. Introduction to VLSI Testing.1 Problems to Think A 32 bit adder A
A Fast Signature Computation Algorithm for LFSR and MISR
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 9, SEPTEMBER 2000 1031 A Fast Signature Computation Algorithm for LFSR and MISR Bin-Hong Lin, Shao-Hui Shieh,
Arbitrary Density Pattern (ADP) Based Reduction of Testing Time in Scan-BIST VLSI Circuits
Arbitrary Density Pattern (ADP) Based Reduction of Testing Time in Scan-BIST VLSI Circuits G. Naveen Balaji S. Vinoth Vijay Abstract Test power reduction done by Arbitrary Density Patterns (ADP) in which
THE ADVANTAGES OF COMBINING LOW PIN COUNT TEST WITH SCAN COMPRESSION OF VLSI TESTING
Zbornik radova 56. Konferencije za ETRAN, Zlatibor, 11-14. juna 2012. Proc. 56th ETRAN Conference, Zlatibor, June 11-14, 2012 THE ADVANTAGES OF COMBINING LOW PIN COUNT TEST WITH SCAN COMPRESSION OF VLSI
TABLE OF CONTENTS. xiii List of Tables. xviii List of Design-for-Test Rules. xix Preface to the First Edition. xxi Preface to the Second Edition
TABLE OF CONTENTS List of Figures xiii List of Tables xviii List of Design-for-Test Rules xix Preface to the First Edition xxi Preface to the Second Edition xxiii Acknowledgement xxv 1 Boundary-Scan Basics
FAULT TOLERANCE FOR MULTIPROCESSOR SYSTEMS VIA TIME REDUNDANT TASK SCHEDULING
FAULT TOLERANCE FOR MULTIPROCESSOR SYSTEMS VIA TIME REDUNDANT TASK SCHEDULING Hussain Al-Asaad and Alireza Sarvi Department of Electrical & Computer Engineering University of California Davis, CA, U.S.A.
A New Multi-site Test for System-on-Chip Using Multi-site Star Test Architecture
A New Multi-site Test for System-on-Chip Using Multi-site Star Test Architecture Dongkwan Han, Yong Lee, and Sungho Kang As the system-on-chip (SoC) design becomes more complex, the test costs are increasing.
Chapter 2 Logic Gates and Introduction to Computer Architecture
Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are
Combinational Controllability Controllability Formulas (Cont.)
Outline Digital Testing: Testability Measures The case for DFT Testability Measures Controllability and observability SCOA measures Combinational circuits Sequential circuits Adhoc techniques Easily testable
Implementation Details
LEON3-FT Processor System Scan-I/F FT FT Add-on Add-on 2 2 kbyte kbyte I- I- Cache Cache Scan Scan Test Test UART UART 0 0 UART UART 1 1 Serial 0 Serial 1 EJTAG LEON_3FT LEON_3FT Core Core 8 Reg. Windows
Memory Testing. Memory testing.1
Memory Testing Introduction Memory Architecture & Fault Models Test Algorithms DC / AC / Dynamic Tests Built-in Self Testing Schemes Built-in Self Repair Schemes Memory testing.1 Memory Market Share in
SoC Curricula at Tallinn Technical University
SoC Curricula at Tallinn Technical University Margus Kruus, Kalle Tammemäe, Peeter Ellervee Tallinn Technical University Phone: +372-6202250, Fax: +372-6202246 kruus@cc.ttu.ee nalle@cc.ttu.ee lrv@cc.ttu.ee
At-Speed Test Considering Deep Submicron Effects. D. M. H. Walker Dept. of Computer Science Texas A&M University walker@cs.tamu.
At-Speed Test Considering Deep Submicron Effects D. M. H. Walker Dept. of Computer Science Teas A&M University walker@cs.tamu.edu Integrated Circuit Testing IC Test What s Going On Test Generation Test
Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell
Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, and José Luis Huertas Instituto de Microelectrónica
DEVELOPING TRENDS OF SYSTEM ON A CHIP AND EMBEDDED SYSTEM
DEVELOPING TRENDS OF SYSTEM ON A CHIP AND EMBEDDED SYSTEM * Monire Norouzi Young Researchers and Elite Club, Shabestar Branch, Islamic Azad University, Shabestar, Iran *Author for Correspondence ABSTRACT
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow Bradley R. Quinton Dept. of Electrical and Computer Engineering University of British Columbia bradq@ece.ubc.ca
Chung-Ho Chen Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
A Hybrid Software-Based Self-Testing methodology for Embedded Processor Tai-Hua Lu Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan aaron@casmail.ee.ncku.edu.tw Chung-Ho
1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.
File: chap04, Chapter 04 1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. 2. True or False? A gate is a device that accepts a single input signal and produces one
Security in the Age of Nanocomputing. Hacking Devices
Security in the Age of Nanocomputing Matthew Tan Creti Hacking Devices The ESA estimates its total worldwide losses due to piracy at $3 billion annually [2] One million unlocked iphones could cost Apple
A RDT-Based Interconnection Network for Scalable Network-on-Chip Designs
A RDT-Based Interconnection Network for Scalable Network-on-Chip Designs ang u, Mei ang, ulu ang, and ingtao Jiang Dept. of Computer Science Nankai University Tianjing, 300071, China yuyang_79@yahoo.com.cn,
Programming NAND devices
Technical Guide Programming NAND devices Kelly Hirsch, Director of Advanced Technology, Data I/O Corporation Recent Design Trends In the past, embedded system designs have used NAND devices for storing
Non-Contact Test Access for Surface Mount Technology IEEE 1149.1-1990
Non-Contact Test Access for Surface Mount Technology IEEE 1149.1-1990 ABSTRACT Mechanical and chemical process challenges initially limited acceptance of surface mount technology (SMT). As those challenges
Objective. Testing Principle. Types of Testing. Characterization Test. Verification Testing. VLSI Design Verification and Testing.
VLSI Design Verification and Testing Objective VLSI Testing Mohammad Tehranipoor Electrical and Computer Engineering University of Connecticut Need to understand Types of tests performed at different stages
Lesson 7: SYSTEM-ON. SoC) AND USE OF VLSI CIRCUIT DESIGN TECHNOLOGY. Chapter-1L07: "Embedded Systems - ", Raj Kamal, Publs.: McGraw-Hill Education
Lesson 7: SYSTEM-ON ON-CHIP (SoC( SoC) AND USE OF VLSI CIRCUIT DESIGN TECHNOLOGY 1 VLSI chip Integration of high-level components Possess gate-level sophistication in circuits above that of the counter,
Fault Modeling. Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults. Transistor faults Summary
Fault Modeling Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults Single stuck-at faults Fault equivalence Fault dominance and checkpoint theorem Classes of stuck-at
Floating Point Fused Add-Subtract and Fused Dot-Product Units
Floating Point Fused Add-Subtract and Fused Dot-Product Units S. Kishor [1], S. P. Prakash [2] PG Scholar (VLSI DESIGN), Department of ECE Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu,
Agenda. Michele Taliercio, Il circuito Integrato, Novembre 2001
Agenda Introduzione Il mercato Dal circuito integrato al System on a Chip (SoC) La progettazione di un SoC La tecnologia Una fabbrica di circuiti integrati 28 How to handle complexity G The engineering
EEC 119B Spring 2014 Final Project: System-On-Chip Module
EEC 119B Spring 2014 Final Project: System-On-Chip Module Dept. of Electrical and Computer Engineering University of California, Davis Issued: March 14, 2014 Subject to Revision Final Report Due: June
Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications
Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications TRIPTI SHARMA, K. G. SHARMA, B. P. SINGH, NEHA ARORA Electronics & Communication Department MITS Deemed University,
Introduction to Digital System Design
Introduction to Digital System Design Chapter 1 1 Outline 1. Why Digital? 2. Device Technologies 3. System Representation 4. Abstraction 5. Development Tasks 6. Development Flow Chapter 1 2 1. Why Digital
Leakage Power Reduction Using Sleepy Stack Power Gating Technique
Leakage Power Reduction Using Sleepy Stack Power Gating Technique M.Lavanya, P.Anitha M.E Student [Applied Electronics], Dept. of ECE, Kingston Engineering College, Vellore, Tamil Nadu, India Assistant
A Computer Vision System on a Chip: a case study from the automotive domain
A Computer Vision System on a Chip: a case study from the automotive domain Gideon P. Stein Elchanan Rushinek Gaby Hayun Amnon Shashua Mobileye Vision Technologies Ltd. Hebrew University Jerusalem, Israel
Test Time Minimization for Hybrid BIST of Systems-on-Chip
TALLINN TECHNICAL UNIVERSITY Faculty of Information Technology Department of Computer Engineering Chair of Computer Engineering and Diagnostics Bachelor Thesis IAF34LT Test Time Minimization for Hybrid
March SS: A Test for All Static Simple RAM Faults
March SS: A Test for All Static Simple RAM Faults Said Hamdioui 1 2 Ad J. van de Goor 2 Mike Rodgers 1 1 Intel Corporation, 2200 Mission College Boulevard, Santa Clara, CA 95052 2 Delft University of Technology,
A PPM-like, tag-based branch predictor
Journal of Instruction-Level Parallelism 7 (25) 1-1 Submitted 1/5; published 4/5 A PPM-like, tag-based branch predictor Pierre Michaud IRISA/INRIA Campus de Beaulieu, Rennes 35, France pmichaud@irisa.fr
Design and Implementation of Concurrent Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications
Design and Implementation of Concurrent Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications 1 Abhilash B T, 2 Veerabhadrappa S T, 3 Anuradha M G Department of E&C,
VON BRAUN LABS. Issue #1 WE PROVIDE COMPLETE SOLUTIONS ULTRA LOW POWER STATE MACHINE SOLUTIONS VON BRAUN LABS. State Machine Technology
VON BRAUN LABS WE PROVIDE COMPLETE SOLUTIONS WWW.VONBRAUNLABS.COM Issue #1 VON BRAUN LABS WE PROVIDE COMPLETE SOLUTIONS ULTRA LOW POWER STATE MACHINE SOLUTIONS State Machine Technology IoT Solutions Learn
Built-In Current Sensor for I DDQ Testing Embedded I DDQ Testing Architecture Based on IEEE 1149.1
SCOPE http://www.cs.uoi.gr VLSI Technology and Computer Architecture Lab Research and teaching in the area of architectures and design techniques for VLSI integrated circuits and systems. ACTIVITIES PERSONEL
Efficient Online and Offline Testing of Embedded DRAMs
1 Efficient Online and Offline Testing of Embedded DRAMs Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, and Vyacheslav N. Yarmolik AbstractÐThis paper presents an integrated
Architectural Level Power Consumption of Network on Chip. Presenter: YUAN Zheng
Architectural Level Power Consumption of Network Presenter: YUAN Zheng Why Architectural Low Power Design? High-speed and large volume communication among different parts on a chip Problem: Power consumption
ARM Ltd 110 Fulbourn Road, Cambridge, CB1 9NJ, UK. *peter.harrod@arm.com
Serial Wire Debug and the CoreSight TM Debug and Trace Architecture Eddie Ashfield, Ian Field, Peter Harrod *, Sean Houlihane, William Orme and Sheldon Woodhouse ARM Ltd 110 Fulbourn Road, Cambridge, CB1
Aims and Objectives. E 3.05 Digital System Design. Course Syllabus. Course Syllabus (1) Programmable Logic
Aims and Objectives E 3.05 Digital System Design Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk How to go
AN EFFICIENT ALGORITHM FOR WRAPPER AND TAM CO-OPTIMIZATION TO REDUCE TEST APPLICATION TIME IN CORE BASED SOC
International Journal of Electronics and Communication Engineering & Technology (IJECET) Volume 7, Issue 2, March-April 2016, pp. 09-17, Article ID: IJECET_07_02_002 Available online at http://www.iaeme.com/ijecet/issues.asp?jtype=ijecet&vtype=7&itype=2
FPGA Implementation of an Advanced Traffic Light Controller using Verilog HDL
FPGA Implementation of an Advanced Traffic Light Controller using Verilog HDL B. Dilip, Y. Alekhya, P. Divya Bharathi Abstract Traffic lights are the signaling devices used to manage traffic on multi-way
Interconnection Networks. Interconnection Networks. Interconnection networks are used everywhere!
Interconnection Networks Interconnection Networks Interconnection networks are used everywhere! Supercomputers connecting the processors Routers connecting the ports can consider a router as a parallel
G. Squillero, M. Rebaudengo. Test Techniques for Systems-on-a-Chip
G. Squillero, M. Rebaudengo Test Techniques for Systems-on-a-Chip December 2005 Preface Fast innovation in VLSI technologies makes possible the integration a complete system into a single chip (System-on-Chip,
Digital Circuit Design
Test and Diagnosis of of ICs Fault coverage (%) 95 9 85 8 75 7 65 97.92 SSL 4,246 Shawn Blanton Professor Department of ECE Center for Silicon System Implementation CMU Laboratory for Integrated Systems
Architectures and Platforms
Hardware/Software Codesign Arch&Platf. - 1 Architectures and Platforms 1. Architecture Selection: The Basic Trade-Offs 2. General Purpose vs. Application-Specific Processors 3. Processor Specialisation
The Boundary Scan Test (BST) technology
The Boundary Scan Test () technology J. M. Martins Ferreira FEUP / DEEC - Rua Dr. Roberto Frias 42-537 Porto - PORTUGAL Tel. 35 225 8 748 / Fax: 35 225 8 443 (jmf@fe.up.pt / http://www.fe.up.pt/~jmf) Objectives
CHAPTER 3 Boolean Algebra and Digital Logic
CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4
Chapter 4 Register Transfer and Microoperations. Section 4.1 Register Transfer Language
Chapter 4 Register Transfer and Microoperations Section 4.1 Register Transfer Language Digital systems are composed of modules that are constructed from digital components, such as registers, decoders,
GARDA: a Diagnostic ATPG for Large Synchronous Sequential Circuits
GARDA: a Diagnostic ATPG for Large Synchronous Sequential Circuits F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda Politecnico di Torino Dipartimento di Automatica e Informatica Torino, Italy Abstract
On the Use of Strong BCH Codes for Improving Multilevel NAND Flash Memory Storage Capacity
On the Use of Strong BCH Codes for Improving Multilevel NAND Flash Memory Storage Capacity Fei Sun, Ken Rose, and Tong Zhang ECSE Department, Rensselaer Polytechnic Institute, USA Abstract This paper investigates
CHAPTER 5 FINITE STATE MACHINE FOR LOOKUP ENGINE
CHAPTER 5 71 FINITE STATE MACHINE FOR LOOKUP ENGINE 5.1 INTRODUCTION Finite State Machines (FSMs) are important components of digital systems. Therefore, techniques for area efficiency and fast implementation
UNIT 2 CLASSIFICATION OF PARALLEL COMPUTERS
UNIT 2 CLASSIFICATION OF PARALLEL COMPUTERS Structure Page Nos. 2.0 Introduction 27 2.1 Objectives 27 2.2 Types of Classification 28 2.3 Flynn s Classification 28 2.3.1 Instruction Cycle 2.3.2 Instruction
ON SUITABILITY OF FPGA BASED EVOLVABLE HARDWARE SYSTEMS TO INTEGRATE RECONFIGURABLE CIRCUITS WITH HOST PROCESSING UNIT
216 ON SUITABILITY OF FPGA BASED EVOLVABLE HARDWARE SYSTEMS TO INTEGRATE RECONFIGURABLE CIRCUITS WITH HOST PROCESSING UNIT *P.Nirmalkumar, **J.Raja Paul Perinbam, @S.Ravi and #B.Rajan *Research Scholar,
List of courses MEngg (Computer Systems)
List of courses MEngg (Computer Systems) Course No. Course Title Non-Credit Courses CS-401 CS-402 CS-403 CS-404 CS-405 CS-406 Introduction to Programming Systems Design System Design using Microprocessors
3D On-chip Data Center Networks Using Circuit Switches and Packet Switches
3D On-chip Data Center Networks Using Circuit Switches and Packet Switches Takahide Ikeda Yuichi Ohsita, and Masayuki Murata Graduate School of Information Science and Technology, Osaka University Osaka,
Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology
Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology Nahid Rahman Department of electronics and communication FET-MITS (Deemed university), Lakshmangarh, India B. P. Singh Department
NAME AND SURNAME. TIME: 1 hour 30 minutes 1/6
E.T.S.E.T.B. MSc in ICT FINAL EXAM VLSI Digital Design Spring Course 2005-2006 June 6, 2006 Score publication date: June 19, 2006 Exam review request deadline: June 22, 2006 Academic consultancy: June
SDLC Controller. Documentation. Design File Formats. Verification
January 15, 2004 Product Specification 11 Stonewall Court Woodcliff Lake, NJ 07677 USA Phone: +1-201-391-8300 Fax: +1-201-391-8694 E-mail: info@cast-inc.com URL: www.cast-inc.com Features AllianceCORE
路 論 Chapter 15 System-Level Physical Design
Introduction to VLSI Circuits and Systems 路 論 Chapter 15 System-Level Physical Design Dept. of Electronic Engineering National Chin-Yi University of Technology Fall 2007 Outline Clocked Flip-flops CMOS
COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design
PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits
Curriculum for a Master s Degree in ECE with focus on Mixed Signal SOC Design
Curriculum for a Master s Degree in ECE with focus on Mixed Signal SOC Design Department of Electrical and Computer Engineering Overview The VLSI Design program is part of two tracks in the department:
WITH continued growth in semiconductor industries and. Fault Simulation and Response Compaction in Full Scan Circuits Using HOPE
2310 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 54, NO. 6, DECEMBER 2005 Fault Simulation and Response Compaction in Full Scan Circuits Using HOPE Sunil R. Das, Life Fellow, IEEE, Chittoor
Programmable Logic Devices: A Test Approach for the Input/Output Blocks and Pad-to-Pin Interconnections
Programmable Logic Devices: A Test Approach for the Input/Output Blocks and Pad-to-Pin Interconnections Manuel G. Gericota, Gustavo R. Alves Department of Electrical Engineering ISEP Rua Dr. António Bernardino
A comprehensive survey on various ETC techniques for secure Data transmission
A comprehensive survey on various ETC techniques for secure Data transmission Shaikh Nasreen 1, Prof. Suchita Wankhade 2 1, 2 Department of Computer Engineering 1, 2 Trinity College of Engineering and
Breaking the Interleaving Bottleneck in Communication Applications for Efficient SoC Implementations
Microelectronic System Design Research Group University Kaiserslautern www.eit.uni-kl.de/wehn Breaking the Interleaving Bottleneck in Communication Applications for Efficient SoC Implementations Norbert
How To Fix A 3 Bit Error In Data From A Data Point To A Bit Code (Data Point) With A Power Source (Data Source) And A Power Cell (Power Source)
FPGA IMPLEMENTATION OF 4D-PARITY BASED DATA CODING TECHNIQUE Vijay Tawar 1, Rajani Gupta 2 1 Student, KNPCST, Hoshangabad Road, Misrod, Bhopal, Pin no.462047 2 Head of Department (EC), KNPCST, Hoshangabad
3D NAND Technology Implications to Enterprise Storage Applications
3D NAND Technology Implications to Enterprise Storage Applications Jung H. Yoon Memory Technology IBM Systems Supply Chain Outline Memory Technology Scaling - Driving Forces Density trends & outlook Bit
Lecture 5: Gate Logic Logic Optimization
Lecture 5: Gate Logic Logic Optimization MAH, AEN EE271 Lecture 5 1 Overview Reading McCluskey, Logic Design Principles- or any text in boolean algebra Introduction We could design at the level of irsim
RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition
RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition A Tutorial Approach James O. Hamblen Georgia Institute of Technology Michael D. Furman Georgia Institute of Technology KLUWER ACADEMIC PUBLISHERS Boston
Research Article Engineering Change Orders Design Using Multiple Variables Linear Programming for VLSI Design
VLSI Design, rticle ID 698041, 5 pages http://dx.doi.org/10.1155/2014/698041 Research rticle Engineering Change Orders Design Using Multiple Variables Linear Programming for VLSI Design Yu-Cheng Fan, Chih-Kang
ADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-12: ARM
ADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-12: ARM 1 The ARM architecture processors popular in Mobile phone systems 2 ARM Features ARM has 32-bit architecture but supports 16 bit
Remote Testing and Diagnosis of System-on-Chips Using Network Management Frameworks 1
Remote Testing and Diagnosis of System-on-Chips Using Network Management Frameworks 1 Oussama Laouamri & Chouki Aktouf DeFacTo Technologies, 167 rue de Mayoussard, 38 430 Moirans, FRANCE Abstract This
Error Detection and Data Recovery Architecture for Systolic Motion Estimators
Error Detection and Data Recovery Architecture for Systolic Motion Estimators L. Arun Kumar #1, L. Sheela *2 # PG Scholar, * Assistant Professor, Embedded System Technologies, Regional Center of Anna University
Reconfigurable Architecture Requirements for Co-Designed Virtual Machines
Reconfigurable Architecture Requirements for Co-Designed Virtual Machines Kenneth B. Kent University of New Brunswick Faculty of Computer Science Fredericton, New Brunswick, Canada ken@unb.ca Micaela Serra
IMPROVING PERFORMANCE OF RANDOMIZED SIGNATURE SORT USING HASHING AND BITWISE OPERATORS
Volume 2, No. 3, March 2011 Journal of Global Research in Computer Science RESEARCH PAPER Available Online at www.jgrcs.info IMPROVING PERFORMANCE OF RANDOMIZED SIGNATURE SORT USING HASHING AND BITWISE
Euler Vector: A Combinatorial Signature for Gray-Tone Images
Euler Vector: A Combinatorial Signature for Gray-Tone Images Arijit Bishnu, Bhargab B. Bhattacharya y, Malay K. Kundu, C. A. Murthy fbishnu t, bhargab, malay, murthyg@isical.ac.in Indian Statistical Institute,
Design of a High Speed Communications Link Using Field Programmable Gate Arrays
Customer-Authored Application Note AC103 Design of a High Speed Communications Link Using Field Programmable Gate Arrays Amy Lovelace, Technical Staff Engineer Alcatel Network Systems Introduction A communication
Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements
THE semiconductor industry is adopting new fabrication
896 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 5, MAY 2007 Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers Nisar
Module 2. Embedded Processors and Memory. Version 2 EE IIT, Kharagpur 1
Module 2 Embedded Processors and Memory Version 2 EE IIT, Kharagpur 1 Lesson 5 Memory-I Version 2 EE IIT, Kharagpur 2 Instructional Objectives After going through this lesson the student would Pre-Requisite
JTAG Applications. Product Life-Cycle Support. Software Debug. Integration & Test. Figure 1. Product Life Cycle Support
JTAG Applications While it is obvious that JTAG based testing can be used in the production phase of a product, new developments and applications of the IEEE-1149.1 standard have enabled the use of JTAG
Switching and Finite Automata Theory
Switching and Finite Automata Theory Understand the structure, behavior, and limitations of logic machines with this thoroughly updated third edition. New topics include: CMOS gates logic synthesis logic
Computer Network. Interconnected collection of autonomous computers that are able to exchange information
Introduction Computer Network. Interconnected collection of autonomous computers that are able to exchange information No master/slave relationship between the computers in the network Data Communications.
Reconfigurable Low Area Complexity Filter Bank Architecture for Software Defined Radio
Reconfigurable Low Area Complexity Filter Bank Architecture for Software Defined Radio 1 Anuradha S. Deshmukh, 2 Prof. M. N. Thakare, 3 Prof.G.D.Korde 1 M.Tech (VLSI) III rd sem Student, 2 Assistant Professor(Selection
Improving Hardware Security by Using Hidden Information of Computer
Improving Hardware Security by Using Hidden Information of Computer System Ilya Levin, 2 Osnat Keren, 2 Vladimir Sinelnikov * Tel Aviv University, ilia@post.tau.ac.il 2 Bar Ilan University, kereno@eng.biu.ac.il
From Concept to Production in Secure Voice Communications
From Concept to Production in Secure Voice Communications Earl E. Swartzlander, Jr. Electrical and Computer Engineering Department University of Texas at Austin Austin, TX 78712 Abstract In the 1970s secure