Ultra Thin Body and Buried oxide substrate supply chain

Transcription

1 1 Ultra Thin Body and Buried oxide substrate supply chain 2013 / 6 / 15 FD-SOI Workshop at Kyoto, Japan

2 2 Outline 1. Introduction of Shin Etsu 2. SOI Wafer Line Up 3. Quality Data of FD SOI Wafer 4. Capability and Conclusion

3 3 Outline 1. Introduction of Shin Etsu 2. SOI Wafer Line Up 3. Quality Data of FD SOI Wafer 4. Capability and Conclusion

4 4 SHIN ETSU GROUP MAJOR ELECTRONIC MATERIALS Semiconductor Silicon Quartz Products Synthetic Quartz Photomask Substrate Fiber Optic Preforms Quartz Stepper Lens Blanks Quartz Crucibles High Performance Polymer Composites Compound Semiconductors Processed Resin Materials Molding Compounds Rare Earth Magnets Pellicles Thermally Conductive Silicone Grease Photoresists Shin Etsu Handotai

5 5

6 6 SEH Total Solution of Wafer Supply From CZ to FD SOI

7 7 Outline 1. Introduction of Shin Etsu 2. SOI Wafer Line Up 3. Quality Data of FD SOI Wafer 4. Capability and Conclusion

8 8 Shin Etsu Handotai Silicon On Insulator 1988 BG SOI Production start at Nagano Denshi 1997 Introduce SmartCut Technology from SOITEC mm Thin SOI Production start mm Thin SOI Production start 2012 extend 10 years contract with SOITEC Nagano Denshi Chikuma shi, Nagano Thick SOI :100mm,125mm 150mm, 200mm Thin SOI : 150mm, 200mm Isobe Plant SOI Production Dept. Annaka shi, Gunma Thin SOI : 300mm

9 9 SEH SOI Process and SOI Application SOI Thickness ( micron ) Epi Thin Thick Bonded SOI PD-SOI MEMS Power Device BCD RF Thickness SOI BOX Si Substrate Thickness FIN-SOI 0.01 FD-SOI BOX Thickness ( micron )

10 10 Outline 1. Introduction of Shin Etsu 2. SOI Wafer Line Up 3. Quality Data of FD SOI Wafer 4. Capability and Conclusion

11 11 Requirement for FD SOI substrate Item SOI layer BOX layer Defect Roughness Requirement 12+/ 0.5nm (all point) Range < 1nm Thin BOX : 25nm Low defectivity RMS < 0.1nm SOI thickness BOX thickness HF defect LLS SOI (12nm) BOX ( 25nm) Handle wafer Roughness B.Doris et al., FD Workshop at SFO, 2012

12 12 Improvement of SOI thickness uniformity Optimization of oxidation condition Oxidation Donor wafer Range:1.12nm Range:0.11nm Implantation Optimization of implantation & Splitting condition Frequency 60% 50% 40% 30% 20% 10% 0% After optimization < 0.1nm < 0.2nm < 0.3nm < 0.4nm < 0.5nm < 0.6nm < 0.7nm < 0.8nm < 0.9nm < 1.0nm < 1.1nm < 1.2nm < 1.3nm < 1.4nm < 1.5nm < 1.6nm < 1.7nm < 1.8nm < 1.9nm < 2.0nm Range in a wafer [nm] Optimization of oxidation condition SOI thickness uniformity Handle wafer Bonding Splitting Smoothing anneal & Oxidation

13 SOI thickness SOI (12nm) BOX ( 25nm) 12nm SOI Handle wafer 25nm BOX Max Ave. Min EE=3mm. 41p/wf by ellipsometer 13 SOI thickness [nm] Target +/ 0.5nm is available 35% 30% 25% 20% 15% 10% 5% 0% Handle wafer 0.1nm 0.2nm 0.3nm 0.4nm 0.5nm 0.6nm 0.7nm 0.8nm 0.9nm 1.0nm 1.1nm 1.2nm 1.3nm 1.4nm 1.5nm 1.6nm 1.7nm 1.8nm 1.9nm < 2.0nm Relative Frequency Cumulative SOI thickness Range in a wafer 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0%

14 SOI (12nm) BOX ( 25nm) BOX thickness Handle wafer Max Ave. Min EE=3mm. 41p/wf by ellipsometer 14 BOX thickness [nm] Target +/ 0.5nm is available 45% 40% 35% 30% 25% 20% 15% 10% 5% 0% 0.1nm 0.2nm 0.3nm 0.4nm 0.5nm 0.6nm 0.7nm 0.8nm 0.9nm 1.0nm 1.1nm 1.2nm 1.3nm 1.4nm 1.5nm 1.6nm 1.7nm 1.8nm 1.9nm < 2.0nm Relative Frequency Cumulative BOX thickness Range in a wafer 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0%

15 15 Max 1Q Average Median 3Q Min 50 SOD: 0.09um up Defectivity SOI/BOX=12nm/25nm 50 Area: 0.5um up Measurement tool : SP2 Defects Map um up LLS [nm] Ave. 11.1cnt/wf 0.5um up LLS [nm] Ave. 4.1cnt/wf SOD: 11cnt Area: 4cnt 0 0 Low defect counts are available.

16 16 Surface roughness Oxidation Donor wafer Roughness = local thickness deviation Implantation SOI (12nm) BOX ( 25nm) Handle wafer Bonding Splitting Roughness [nm] Smoothing anneal & Oxidation Handle wafer Annealing Time AFM roughness is very close to ideal region. (RMS<0.1nm) After Smoothing anneal RMS: 0.11nm Rmax: 1.1nm 30um x 30um measurement

17 17 Outline 1. Introduction of Shin Etsu 2. SOI Wafer Line Up 3. Quality Data of FD SOI Wafer 4. Capability and Conclusion

18 18 SEH can produce FD SOI 1) Quality Achieved 2) Enough Experience ( See table on the right) SEH has already achieved required wafer quality for FD SOI. SOI thickness range =< 1nm Micro roughness is about 0.1nm RMS in AFM measurement. SEH is world s largest Si wafer supplier for over 40 years. (Polished wafer, Epitaxial wafer, Annealed wafer etc) SEH has 10 years experience in 300mm thin SOI mass production. ( for PD SOI device application SOI thickness = 50 90nm) 3) Enough factories for rapid expansion SEH can quickly expand the existing capacity to meet the demand increase. 4) Shin Etsu group is also stable in terms of finances. Moody s Rating : Aa3 (Shin Etsu Chemical Co., Ltd) Table TEM Observation 25nm BOX Handle AFM Mapping RMS: 0.11nm Rmax: 1.1nm 12nm SOI SOI Thickness Map 41p/wf by ellipsometer Range: 0.30nm

19 19 Thank you for your attention!