Ultra Low Power Logic Gates

Transcription

1 Website: (ISSN , ISO 91:8 Certified Journal, Volume 3, Issue 7, July 213) Abstract In this wk, implementation of all the basic logic gates is presented using 18nm CMOS technology with a very low voltage of.7v. Ideally logic family should not dissipate power, have zero propagation delay, controlled rise fall times with noise immunity. The property of CMOS closely approaches these characteristics. Another desirable characteristic of CMOS are its robustness with respect to voltage size scaling. Though with all the desirable characteristics of CMOS when it is implemented in the field of VLSI design there is always a tradeoff between area, power dissipation speed of operation. The main objective of this paper is to implement all the basic logic gates by exploiting the property of voltage Gate size scaling of CMOS with ultra low power dissipation without affecting the nmal operation of the basic gates. In IC technology which is powered by battery, if the total power dissipation is low, the service time offer by the battery is much longer. Keywds CMOS, Dynamic Power, Logic family, Static Power, Universal Gate, W/L ratio. I. INTRODUCTION In IC design technology where numbers of logic gates are integrated, constant continuous wks is being carried out by different experts to reduce the power dissipation. It is still a big challenge f researchers to design a reliable circuit with very low power dissipation. There are different approaches to minimize the power dissipation base on architecture, circuit level, layout, process technology. Among all these techniques, at the circuit design level considerable amount of power savings can be achieve by means of proper choice of a logic style f implementing combinational circuits. This is because all the imptant parameters governing power dissipation switching capacitance, transition activity, sht-circuit currents are strongly influenced by the chosen logic circuit [1]. Another approach to reduce power dissipation is by using stack technique where each of the NMOS PMOS in the logic gate is split into two transists [2]. Sub threshold circuit design operation technique also reduces power dissipation in CMOS where circuits should be operated in near-threshold region [3]. Another effective way is by reducing the supply voltage as CMOS total power dissipation depends upon two power i.e. dynamic power static power. As these both power depends upon V DD if supply voltage is reduced the total power can be minimize. Ultra Low Power Logic Gates N K Kaphungkui Dept. Of ECE, Dibrugarh University, Assam, India 76 The main aim of this paper is to reduce the power dissipation of logic gates by voltage reduction technique. II. GENERAL REVIEW OF TOTAL POWER CONSUMPTION IN CMOS. The basic equation governing the total power in CMOS circuit is given by P Total = P Dynamic + P Static P Total = ½ C L V DD 2 af + I Sc V DD + I Static V DD (1) Where C L is the load capacitance, f is the frequency of operation, a is the activity fact, I Sc is the sht circuit current [3] [4]. The equation (1) implies that both the dynamic static power depends upon the supply voltage V DD at large. The dynamic power consumption is mainly due to the charging dis-charging of the capacitance sht circuit current. A sht circuit current flows when the pull up pull down netwks in a CMOS circuit are simultaneously on a direct path exists between the supply line ground. Dynamic power is directly proptional to the square of the supply voltage. Therefe, dynamic power reduces in a quadratic manner when the supply voltage is reduced. Leakage power is dependent on the leakage current flowing in the CMOS circuit. If the supply voltage V DD is reduced the total power dissipation in the CMOS circuit can be decrease tremendously. This wk is carried out at supply voltage of.7v with 18nm CMOS technology by scaling the size of MOS transist to its minimum optimum level so that the basic gate operation is not affected. III. CIRCUIT IMPLEMENTATION The implementation of logic family include universal logic gates (NAND gate, NOR gate) basic gates such as OR gate (implementing with NOR gate), AND gate (implementing with NAND gate), XOR gate XNOR gate. Simulation is carried out with a supply voltage V DD of.7v. A stream of bits is used as input bits. Each of the bits with magnitude.7v cresponds to logic 1 the ground state cresponds to logic. Bit that cresponds to logic 1 has a rise fall time of 1 psec each. Simulation is carried out at a bit frequency of 2 MHz. All the Gates are simulated f logic Gates having two input terminal A B with output terminal C.

2 Website: (ISSN , ISO 91:8 Certified Journal, Volume 3, Issue 7, July 213) The W/L ratios of each gate are preciously optimized f proper operation without affecting the basic Gate operation. (a). NAND GATE If any one of the input of NAND Gate is logic the output is always high as shown in the simulation result Fig 1 (a). To simulate the gate, bit of stream (1) is gave to input A (111) to input B. C is the output with bit stream (1111). With four transists NAND gate in Fig.1 is implemented the total power dissipation from this gate is only 8.36 pw which is the lowest among all the Gates. The operation table of NAND gate is also shown in Table I. (B). NOR GATE Fig.1 (a) Simulation result of NAND Gate When one of the input to NOR Gate is logic 1 the output is always logic. The condition f NOR Gate output to go high is when all the inputs are logic. NOR Gate is the complement of OR gate. NOR Gate is implemented with four transists as shown in Fig. 2. The power dissipate from this Gate is 33.5 pw with the circuit current of pa only. The input output result its simulation results is shown in Table II Fig 2. (a) Respectively. Input A B are bits (1) (111). C is the resultant output with bit stream (111) Fig.1 NAND GATE Table I NAND GATE OPERATION TABLE Fig. 2 NOR GATE 77

3 8 - - n 8 9 n 8 9 n Website: (ISSN , ISO 91:8 Certified Journal, Volume 3, Issue 7, July 213) Table II NOR GATE OPERATION TABLE Table III OR GATE OPERATION TABLE Fig.3 (a) Simulation Result of OR Gate Fig.2 (a) Simulation Result of NOR Gate (c). OR GATE When either of the input to OR Gate is logic 1 the output is always logic 1. This gate is implemented with one of the universal gate i.e with NOR gate as shown in Fig.3. Four NMOS four PMOS are required to construct OR Gate. The total power dissipated from this gate is pw with a circuit current consumption of pa. The operation of OR Gate its simulation result is also shown below in Table III Fig. 3 (a) respectively. Stream of bits (1111) () are input A B. C is the resultant output with bits (1111) (d). AND GATE The condition f AND gate output to go high is all the input should be logic 1. If this condition is not met if one of the inputs is logic then output will always be in logic states. With two NAND gate this basic gate is implemented as shown in Fig.4.the circuit current consumption is pa its power dissipation is only pw which is the second lowest power consumption among all the gates. Operation table, Table IV shows the various input combination its resultant output the simulation result is also shown in Fig. 4 (a). To simulate the Gate, bit string ( ) (11111) represent input A B at the output terminal C resultant bit (11111) is obtained. Fig.3 OR GATE 78 Fig.4 AND GATE

4 v( d) x run x run x run Website: (ISSN , ISO 91:8 Certified Journal, Volume 3, Issue 7, July 213) Table IV AND GATE OPERATION TABLE Table V XOR GATE OPERATION TABLE (e). XOR GATE Fig.4 (a) Simulation Result of AND Gate Eight MOS transist two inverters are required to implement this gate shown in Fig 5. Power dissipation is also higher as the number of transist is increased. F two input XOR gate, output is logic when all the input are same else it will give logic 1 at the output as shown in the operation table, Table V. XOR gate dissipate a total power of pw its simulation result f two input combination of bit streams is also shown in Fig. 5 (a) (f). XNOR Fig.5 (a) Simulation Result of XOR Gate This gate is the complement of XOR gate implementing with the same number of transist as XOR Gate in Fig.6 but with the highest power dissipation of pw due to different gate dimension. F two input gate if the inputs are same i.e. if input are (,) (1,1) output is logic 1 else it will fce its output to logic as shown in simulation result Fig. 6 (a) along with its basic operation table in Table VI Fig.5 XOR GATE 79 Fig.6 XNOR GATE

5 xn xn xn Website: (ISSN , ISO 91:8 Certified Journal, Volume 3, Issue 7, July 213) Table VI XNOR GATE OPERATION TABLE IV. CONCLUSION The technology use f implementing the MOS transist is CMOS 18nm technology the simulation toll is TANNER software. The power dissipation can thus be reduce as low as in the range of Pico-Watt by reducing V DD as low as.7v along with scaling the size of length width of the MOS device. The first timing wavefm in each simulation result represents the output result along with two input bits stream operating at 2MHz. The total current power consumes by each of the logic family is also tabled in Table VII. Circuit power dissipation mainly depends upon the supply voltage. So by lowering the supply voltage scaling the Gate s dimension of the CMOS at the appropriate proption, the total circuit power dissipation is thus lowered without affecting the overall circuit perfmance as shown in the entire simulation figure. Fig.6 (a) Simulation Result of XNOR Gate The total circuit current n power dissipation in each of the logic gates is listed in the table below as shown in Table VII Table VII POWER DISSIPATION IN EACH GATE REFERENCES [1 ] Reto Zimmermann Wolfgang Fichtner, Fellow, IEE Low- Power Logic Styles: CMOS Versus PassTransist Logic IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 7, JULY 1997 [2 ] Sreenivasa Rao Ijjada, B.Ramparamesh, Dr. V.Malleswara Rao Reduction of Power Dissipation in Logic Circuits International Journal of Computer Applications ( )Volume 24 No.6, June 211 [3 ] N. Geetha Rani1, N. Praveen Kumar2, Dr. B. Dr. B. Stephen Charles 3 Dr. P. Chrasekhar Reddy 4 S.Md.Imran Ali 5 Design of Near- Threshold CMOS Logic Gates International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 212 [4 ] [4] Subodh Wairya1, Rajendra Kumar Nagaria2 Sudarshan Tiwari2 Comparative Perfmance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits F Low Voltage VLSI Design International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 212 8