Digital Integrated Circuits Lecture 10: Wires
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1 Digital Integrated Circuits Lecture 10: Wires Chih-Wei Liu VLSI Signal Processing LAB National Chiao Tung University DIC-Lec10 1
2 Outline Introduction Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters DIC-Lec10 2
3 Introduction Chips are mostly made of wires called interconnect In stick diagram, wires set size Transistors are little things under the wires Many layers of wires Wires are as important as transistors Speed Power Noise Alternating layers run orthogonally DIC-Lec10 3
4 Wire Geometry Pitch = w + s Aspect ratio: AR = t/w Old processes had AR << 1 Modern processes have AR 2 Pack in many skinny wires w s l t h DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 4
5 Layer Stack AMI 0.6 μm process has 3 metal layers Modern processes use metal layers Example: Intel 180 nm process M1: thin, narrow (< 3λ) High density cells M2-M4: thicker For longer wires M5-M6: thickest For V DD, GND, clk Layer T (nm) W (nm) S (nm) AR Substrate DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 5
6 Wire Resistance ρ = resistivity (Ω*m) R = ρ l t w w l t DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 6
7 Wire Resistance ρ = resistivity (Ω*m) ρ l R = = R t w l w R = sheet resistance (Ω/) is a dimensionless unit(!) Count number of squares w l w w R = R * (# of squares) l l t t 1 Rectangular Block R = R (L/W) Ω 4 Rectangular Blocks R = R (2L/2W) Ω = R (L/W) Ω DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 7
8 Choice of Metals Until 180 nm generation, most wires were aluminum Modern processes often use copper Cu atoms diffuse into silicon and damage FETs Must be surrounded by a diffusion barrier Metal Silver (Ag) Copper (Cu) Gold (Au) Aluminum (Al) Tungsten (W) Molybdenum (Mo) Bulk resistivity (μω*cm) DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 8
9 Sheet Resistance Typical sheet resistances in 180 nm process Layer Sheet Resistance (Ω/) Diffusion (silicided) 3-10 Diffusion (no silicide) Polysilicon (silicided) 3-10 Polysilicon (no silicide) Metal Metal Metal Metal Metal Metal DIC-Lec10 9
10 Contacts Resistance Contacts and vias also have 2-20 Ω Use many contacts for lower R Many small contacts for current crowding around periphery DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 10
11 Wire Capacitance Wire has capacitance per unit length To neighbors To layers above and below C total = C top + C bot + 2C adj s w layer n+1 h 2 C top t layer n h 1 C bot C adj layer n-1 DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 11
12 Capacitance Trends Parallel plate equation: C = εa/d Wires are not parallel plates, but obey trends Increasing area (W, t) increases capacitance Increasing distance (s, h) decreases capacitance Dielectric constant ε = kε 0 ε 0 = 8.85 x F/cm k = 3.9 for SiO 2 Processes are starting to use low-k dielectrics k 3 (or less) as dielectrics use air pockets DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 12
13 M2 Capacitance Data Typical wires have ~ 0.2 ff/μm Compare to 2 ff/μm for gate capacitance C total (af/μm) M1, M3 planes s = 320 s = 480 s = 640 s= Isolated s = 320 s = 480 s = 640 s= w (nm) DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 13
14 Diffusion & Polysilicon Diffusion capacitance is very high (about 2 ff/μm) Comparable to gate capacitance Diffusion also has high resistance Avoid using diffusion runners for wires! Polysilicon has lower C but high R Use for transistor gates Occasionally for very short wires between gates DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 14
15 Lumped Element Models Wires are a distributed system Approximate with lumped element models N segments R R/N R/N R/N R/N C C/N C/N C/N C/N R R R/2 R/2 C C/2 C/2 C L-model π-model T-model 3-segment π-model is accurate to 3% in simulation L-model needs 100 segments for same accuracy! Use single segment π-model for Elmore delay DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 15
16 Example Metal2 wire in 180 nm process 5 mm long 0.32 μm wide Construct a 3-segment π-model R = C permicron = DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 16
17 Example Metal2 wire in 180 nm process 5 mm long 0.32 μm wide Construct a 3-segment π-model R = 0.05 Ω/ => R = 781 Ω C permicron = 0.2 ff/μm => C = 1 pf 260 Ω 167 ff 167 ff 260 Ω 167 ff 167 ff 260 Ω 167 ff 167 ff DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 17
18 Wire RC Delay Estimate the delay of a 10x inverter driving a 2x inverter at the end of the 5mm wire from the previous example. R = 2.5 kω*μm for gates Unit inverter: 0.36 μm nmos, 0.72 μm pmos 781 Ω 690 Ω 500 ff 500 ff 4 ff t pd = 1.1 ns Driver Wire Load DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 18
19 Crosstalk A capacitor does not like to change its voltage instantaneously. A wire has high capacitance to its neighbor. When the neighbor switches from 1-> 0 or 0->1, the wire tends to switch too. Called capacitive coupling or crosstalk. Crosstalk effects Noise on nonswitching wires Increased delay on switching wires DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 19
20 Crosstalk Delay Assume layers above and below on average are quiet Second terminal of capacitor can be ignored Model as C gnd = C top + C bot Effective C adj depends on behavior of neighbors Miller effect A B C adj C gnd C gnd B ΔV C eff(a) MCF Constant Switching with A Switching opposite A DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 20
21 Crosstalk Delay Assume layers above and below on average are quiet Second terminal of capacitor can be ignored Model as C gnd = C top + C bot Effective C adj depends on behavior of neighbors Miller effect A B C adj C gnd C gnd B ΔV C eff(a) MCF Constant V DD C gnd + C adj 1 Switching with A 0 C gnd 0 Switching opposite A 2V DD C gnd + 2 C adj 2 DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 21
22 Crosstalk Noise Crosstalk causes noise on nonswitching wires If victim is floating: model as capacitive voltage divider C adj Δ Vvictim = Δ Cgnd v + Cadj V aggressor Aggressor ΔV aggressor Victim C adj C gnd-v ΔV victim DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 22
23 Driven Victims Usually victim is driven by a gate that fights noise Noise depends on relative resistances Victim driver is in linear region, agg. in saturation If sizes are same, R aggressor = 2-4 x R victim Cadj 1 Δ Vvictim = ΔV C + C 1+ k gnd v adj aggressor ΔV aggressor R aggressor C gnd-a Aggressor C adj k τ aggressor = = τ ( + ) ( + ) R C C aggressor gnd a adj R C C victim victim gnd v adj R victim C gnd-v Victim ΔV victim DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 23
24 Coupling Waveforms Simulated coupling for C adj = C victim 1.8 Aggressor Victim (undriven): 50% Victim (half size driver): 16% Victim (equal size driver): 8% Victim (double size driver): 4% t (ps) DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 24
25 Noise Implications So what if we have noise? If the noise is less than the noise margin, nothing happens Static CMOS logic will eventually settle to correct output even if disturbed by large noise spikes But glitches cause extra delay Also cause extra power from false transitions Dynamic logic never recovers from glitches Memories and other sensitive circuits also can produce the wrong answer DIC-Lec10 25
26 Wire Engineering Goal: achieve delay, area, power goals with acceptable noise Degrees of freedom: Width 1.6 Spacing Delay (ns): RC/ Pitch (nm) Coupling: 2C adj / (2C adj +C gnd ) Pitch (nm) Wire Spacing (nm) DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 26
27 Wire Engineering Goal: achieve delay, area, power goals with acceptable noise Degrees of freedom: Width 1.6 Spacing Layer Shielding Delay (ns): RC/ Pitch (nm) Coupling: 2C adj / (2C adj +C gnd ) Pitch (nm) Wire Spacing (nm) vdd a 0 a 1 gnd a 2 a 3 vdd vdd a 0 gnd a 1 vdd a 2 gnd a 0 b 0 a 1 b 1 a 2 b 2 DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 27
28 Repeaters R and C are proportional to l RC delay is proportional to l 2 Unacceptably great for long wires DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 28
29 Repeaters R and C are proportional to l RC delay is proportional to l 2 Unacceptably great for long wires Break long wires into N shorter segments Drive each one with an inverter or buffer Wire Length: l Driver Receiver l/n N Segments Segment l/n l/n Driver Repeater Repeater Repeater Receiver DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 29
30 Repeater Design How many repeaters should we use? How large should each one be? Equivalent Circuit Wire length l/n Wire Capacitance C w *l/n, Resistance R w *l/n Inverter width W (nmos = W, pmos = 2W) Gate Capacitance C *W, Resistance R/W DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 30
31 Repeater Design How many repeaters should we use? How large should each one be? Equivalent Circuit Wire length l Wire Capacitance C w *l, Resistance R w *l Inverter width W (nmos = W, pmos = 2W) Gate Capacitance C *W, Resistance R/W R w ln R/W C w l/2n C w l/2n C'W DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 31
32 Repeater Results Write equation for Elmore Delay Differentiate with respect to W and N Set equal to 0, solve t l = N pd l W = 2RC R C w w ( 2 2) = + RCw RC w RCR C w w ~60-80 ps/mm in 180 nm process DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 32
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