Interleaved Power Factor Correction (IPFC)

Transcription

1 Interleaved Power Factor Correcton (IPFC) 2009 Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 1 Welcome to the Interleaved Power Factor Correcton Reference Desgn Web Semnar. My name s, I am an Applcatons Engneer for the Hgh Performance Mcrocontroller Dvson at Mcrochp. 1

2 Agenda Introducton to Power Factor Correcton IPFC Desgn Overvew IPFC Reference Desgn Concluson 2009 Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 2 Here s the agenda for the today s semnar: we wll brefly talk about Power Factor Correcton and ts mportance. We wll also do an overvew of what Interleaved PFC s and key desgn factors wll be dscussed. Fnally Mcrochp s IPFC reference desgn wll be dscussed 2

3 Agenda Introducton to Power Factor Correcton IPFC Desgn Overvew IPFC Reference Desgn Concluson 2009 Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 3 We wll have a short ntroducton to power factor correcton termnology and why t s mportant 3

4 Introducton to PFC Appled Voltage Resultng Current Φ Φ S 2 2 = P Q S Q cos(φ) = power factor Φ P 2009 Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 4 The Power Factor s defned as the rato between the Real Power and the Apparent Power n an AC crcut. The Real Power represents the net transferred energy transferred to the load over one complete AC cycle whle the Reactve Power represents the fracton that s only temporarly stored by the load. The Real Power s the one measured and montored for power consumpton, and ts assocated energy beng s used to produce mechancal work and heatng. Tradtonally, the power factor s assocated wth the cosne of angle between the real and apparent power components. For smplcty the apparent power can be represented as the vector sum of the real and reactve power, but n the case of non snusodal perodcal sgnals a more complex relatonshp between these components s consdered. 4

5 Introducton to PFC Unutlzed power Appled Voltage Resultng Current Φ Φ S 2 2 = P Q S Q cos(φ) = power factor Φ P 2009 Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 5 The Power Factor s defned as the rato between the Real Power and the Apparent Power n an AC crcut. The Real Power represents the net transferred energy transferred to the load over one complete AC cycle whle the Reactve Power represents the fracton that s only temporarly stored by the load. The Real Power s the one measured and montored for power consumpton, and ts assocated energy beng s used to produce mechancal work and heatng. Tradtonally, the power factor s assocated wth the cosne of angle between the real and apparent power components. For smplcty the apparent power can be represented as the vector sum of the real and reactve power, but n the case of non snusodal perodcal sgnals a more complex relatonshp between these components s consdered. 5

6 Agenda Introducton to Power Factor Correcton IPFC Desgn Overvew IPFC Reference Desgn Concluson 2009 Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 6 In the followng secton we wll have an overvew of the proposed soluton for power factor correcton. We wll talk about three dfferent topologes that allow power factor correcton, and we wll also show a smplfed electrc dagram of an nterleaved Power Factor Correcton crcut 6

7 IPFC Desgn Overvew AC Supply Rectfer PFC Converter Load Vac Iac Vdc PWM Controller Specfcatons: Input AC voltage: 85 to 265V Output voltage: 400V (± 2%) Output power: 350W Power factor: > 0.99 THD: <5% Effcency: > Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 7 A power factor correcton block dagram can be dvded nto 3 man blocks: Frst, the rectfer whch provdes DC voltage to the PFC converter stage, then we have the PFC converter tself whch provdes the control over the current shape and phase lag whle regulatng the output voltage. Fnally we have the controller block. The PFC converter can be mplemented usng dfferent crcut topologes, each of them wth ther advantages and dsadvantages. As t may be observed, the nput s an AC supply, the output of the PFC s a DC voltage. An deal PFC makes sure that ts nput mpedance s purely resstve. Ths allows maxmum use of usable power, or real power. The feedback sgnals needed for the control loop are the rectfed AC voltage, nput AC current and output DC voltage. The output of the control block s a Pulse Wdth Modulaton (PWM) sgnal. 7

8 IPFC Desgn Overvew 2009 Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 8 In ths slde, three of the most common topologes of PFC mplementaton are presented. We wll hghlght advantages and dsadvantages for each of them. These topologes are: buck, boost and buckboost converters. 8

9 IPFC Desgn Overvew Buck Converter S L D C < ωt 0 ωt 2009 Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 9 Startng wth the Buck converter, the output voltage provded to the load s always less than the nput termnals (also known as step down converter). For the purpose of power factor correcton, the buck converter wll functon n dscontnuous conducton mode. 9

10 IPFC Desgn Overvew Buck Converter S L D C Boost Converter L D S C < ωt 0 ωt > ωt 0 ωt 2009 Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 10 The Boost converter has the output voltage greater than the nput (also known as step up converter). When usng ths topology for power factor correcton the current s contnuous. As shown n the current dagram, Contnuous Conducton Mode allows a contnuous current through the nductor. 10

11 IPFC Desgn Overvew Buck Converter S L D C Boost Converter L D S C BuckBoost Converter S D L C < ωt 0 ωt > ωt 0 ωt > < ωt ωt Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 11 The combnaton of the Buck Boost converter, as the name suggests, s a combnaton of a buck converter and a boost converter, so that the characterstcs of both are achevable. The output voltage can be greater of lower that the nput voltage. One dsadvantage of the buck and buckboost topologes s that the swtch s not referenced to ground, whch makes the drver crcutry more complex. The buckboost topology also nverts the sgn of the output voltage, whch brngs another dsadvantage when comes to a cost effectve mplementaton of the sensng crcutry. The preferred method for mplementng PFC and Interleaved PFC s the boost converter due to the reduced current rpple, smplcty of gate drver mplementaton and also because t meets our requrements of output voltage. The dscontnuous conducton mode of buck and buckboost topologes would have a negatve nfluence on the total harmonc dstorton, or THD, and hgher gate drver cost. 11

12 IPFC Desgn Overvew Prmary (Lve) Sde PFC Inductor L1 D1 Boost Dode HV_BUS Vac ~ ~ ~ C1 R1 R2 R3 V AC Sense Q1 PWM1H C2 R sense C3 C4 R4 R5 R6 V DC Sense LIVE_GND I AC Sense PFC MOSFET PFC MOSFET HV_BUS 2009 Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 12 The boost converter s operaton s based on the energy stored n nductance L1 as shown. When Q1 transstor s ON, the current through the nductance s rasng and flyback dode D1 stops conducton. As soon as Q1 swtch opens, there s no path for the current that was flowng through the nductor, except the dode D1, the output capactor C3 and the load. D1 dode closes and starts conductng snce the voltage on ts anode s hgher than the rectfed voltage of AC source. The voltage across nductance L1 reverses ts sgn to mantan current flow. Ths way, both the energy suppled by the AC source and the one prevously stored n the nductor are transferred to the load and the output capactor through dode D1. The nput rectfed voltage Vac and the output DC voltage Vdc are measured usng resstor dvders, whle the nput current s measured usng a shunt resstor. The role of the nductance n ths power factor correcton topology s essental. The physcal sze of the nductor ncreases wth the power ratng. Component sze s one of the man reason for mplementng an Interleave PFC desgn. 12

13 IPFC Desgn Overvew I IN I L1 I D1 I OUT PWM1H I s1 I C E snglestage = 1 LI V AC PWM1L I L2 I D2 PFC output E nterleaved = LI 1 2 LI 2 I s Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 13 An nterleaved PFC conssts of a two boost converter sharng the same load capactor. As we can see n the smplfed schematc, f we assume we have the same nductance for each boost converter, we can see that the energy stored by the system s doubled. Snce the energy stored n the nductors s a key factor for determnng the output power capabltes of the system, the output power provded by sngle stage PFC can be provded by an Interleaved PFC wth much lower nductance values. Lower nductance means smaller nductors for a gven power ratng. 13

14 Agenda Introducton to Power Factor Correcton IPFC Desgn Overvew IPFC Reference Desgn Concluson 2009 Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 14 An Interleaved PFC reference desgn s presented next 14

15 IPFC Reference Desgn AC Supply Rectfer PFC Converter 1 Load PFC Converter 2 Vac Iac Im1 PWM1 Im2 PWM2 Vdc Controller 2009 Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 15 A smplfed block dagram of a dual phase nterleaved PFC s shown. As mentoned earler, a second PFC converter s added sharng the same nputs and outputs. 15

16 IPFC Reference Desgn V DC V AC I AC V DCref V Err I Err PI Controller I CAPref I ACref PI Controller Postscaler Voltage Error Loop 1 V AVG Current Error Loop PWM1 V AC PWM2 I Ref = 0 I Err PWM PI Controller Postscaler I m1 Load Balance Loop I m Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 16 The dfference between an Interleaved PFC and a sngle stage PFC s that two nductors are used for energy storage. Snce energy should be dstrbuted equally, a load balancng controller s added to the nterleaved PFC to make sure the system compensates for varaton n nductance values or feedback crcuts. The Interleaved PFC system has three man compensators: one for voltage, one for current and one for load balance. Addtonally, a feedforward controller s mplemented to compensate for sudden nput voltage changes. The voltage error controller makes sure that the output voltage s not affected by load varatons. The nputs to ths controller are DC output voltage and the correspondng reference. The output of ths controller s the current compensator reference. The current error controller regulates the phase and shape of the nput current. Ths nput current s the sum of both nductors currents, and t s measured usng a shunt resstor. The output of ths controller s a Pulse Wdth Modulaton (PWM) duty cycle whch wll be appled to the power MOSFETS. To balance the currents through both nductors, a Load Balance Loop s mplemented. The nputs to ths compensator are the two currents Im1 and Im2. If these currents are dfferent an unbalance s detected. The PI controller wll regulate ths error and adjust the MOSFETs duty cycles. The output of the load balance control loop wll be a duty cycle correcton term (or delta PWM), whch s subtracted from PWM1 to get the fnal duty cycle of the frst boost converter, and t s added to PWM2 to determne the balanced duty cycle of the second boost converter. 16

17 IPFC Reference Desgn 12V and 3.3V Power Supply Interleaved PFC boost crcutry Fault Crcutry dspic PIM AC nput crcutry User Interface 2009 Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 17 The IPFC reference desgn board can be dvded nto 6 man functonal blocks: the PFC boost crcutry, the AC nput block, the power supply block, the fault crcutry block and user s nterface and programmng block. The two nductors can be seen for both stages, and MOSFETS wth ther respectve dodes are mounted underneath the board wth a heatsnk for better heat dsspaton. 17

18 Semconductor selecton Voltage and current ratng Conducton and commutaton losses Inductance selecton Power output ratng Input current rpple Capactor selecton Output voltage rpple (holdup tme) ESR value IPFC Reference Desgn 2009 Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 18 Ths s a bref descrpton about component selecton for the Interleaved PFC reference desgn. For the semconductor components selecton, voltage and current ratng s mportant. Besdes power ratng, conducton and commutaton losses are also mportant factors for component selecton. These losses wll determne the overall effcency of the system. Semconductor components losses represent about half of the total system losses. The nductance selecton s also related to the output power ratng. The hgher the output power, the bgger the nductance wll be. Another aspect to consder n the nductor selecton s the requred nput current rpple. The output capactor s chosen so that the output voltage rpple s wthn specfcatons. It also depends on the mnmum holdup tme so that controllers can act before the output capactor losses ts charge. The Effectve Seres Resstance (ESR) of the capactor also affects the output voltage rpple. Therefore, the capactor wth the lowest possble ESR s recommended. The ESR of the capactor can be lowered by couplng two capactors n parallel f the board layout dmensons permt t. 18

19 Agenda Introducton to Power Factor Correcton Overvew on IPFC Desgn IPFC Reference Desgn Concluson 2009 Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 19 As a concluson for ths web semnar, we wll talk about overall advantages of nterleaved PFC compared to sngle stage PFC, as well as references from our web ste that wll help users understand the techncal detals of nterleaved PFC. 19

20 Concluson IPFC represents a cost and space effcent soluton VS sngle stage PFC (consderng a certan power lmt) IPFC reference desgn usng dspic DSC offers the possblty of hgh ntegraton factor 2009 Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 20 Interleaved PFC allows a more effcent power factor correcton desgn. It also allows space savngs snce wth a much smaller nductors are needed compared to sngle stage PFC desgn. Interleaved PFC also reduces output current rpple snce two nductors are sharng one load at dfferent tmes. dspic dgtal sgnal controllers combne the rght set of perpherals and computatonal power to enable Interleaved PFC control wth a sngle devce. Ths reference desgn offers a startng platform for these types of applcatons and the modular desgn of the software makes t easy to understand and to add other functons 20

21 Resources For resources and nformaton for Swtch Mode Power Supply applcatons, vst Mcrochp s SMPS Desgn Center at: For a sngle stage PFC mplementaton please refer to applcaton note: AN1106 For a detaled descrpton of the nterleaved PFC reference desgn, please refer to applcaton note: AN1278, vst Mcrochp Technology Incorporated. All Rghts Reserved. Interleaved Power Factor Correcton Slde 21 For resources and nformaton for Swtch Mode Power Supply applcatons, please vst Mcrochp s SMPS Desgn Center at For detals about our sngle stage PFC mplementaton please refer to applcaton note: AN1106 And for a detaled descrpton of the nterleaved PFC reference desgn, please refer to applcaton note: AN1278, or vst Ths wraps up our Interleaved Power Factor Correcton web semnar. Thank you for your nterest n the dspic Dgtal Sgnal Controllers. 21