IC Design. Savant Company Inc. The 6th International System-on-Chip (SoC) Conference, Exhibit, and Workshops, November 2008, Newport Beach, California
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1 IC Design Advanced Power Management Copyright S3 Group Mark Barry Savant Company Inc. The 6th International System-on-Chip (SoC) Conference, Exhibit, and Workshops, November 2008, Newport Beach, California
2 Agenda S3 Group View of Low Power Drivers Low Power Methodologies Architectural Considerations Implementation Considerations Power Management Network Future Directions & Conclusion
3 Who is S3 Group? The Connected Consumer Technology Company Brief Statistics Founded in Employees 6 Design Centres Globally Consumer Focus Consumer Healthcare, Mobile, Home Silicon & Software IP and Solutions NXP, SanDisk, TI, Nokia, Sony etc
4 Portable Consumer Devices Trends S3 Group sees in media players, cellular handsets etc Higher data rates, more integration & richer applications All while trying to increase battery lifetime Integration
5 Mains Powered Consumer Devices Trends S3 Group sees in STB, TV, HDMI, VDSL etc Aggressive Integration leads to packaging & thermal issues Green marketing and regulations Energy star (US), EuP Directive (EU), AGO (Australia) 25 Energy Usage - FOXTEL Standard STBs Energy Use (Whr) Standby mode (Watt) On mode (Watt) UEC UEC 700 Later 2000 UEC 720F 2001 UEC 720iF 2002 UEC 720iX 2003 UEC 1000 (sat) 2003 UEC 1000 (cab) 2003 Pace 420 (sat) 2003 Pa ce420 (cab) Source: Don Brooks, NewsCorp consumer Technology Summit Pace 250 (sat) 2007 Pace 250 (cab)
6 Holistic Power Management Application Socket Heating Battery Lifetime Regulations Methodology Voltage islands Voltage gating DVFS Technology Foundry Node & Flavour Packaging Implementation Tool Flow Architecture IP Selection
7 Agenda S3 Group View of Low Power Drivers Low Power Methodologies Architectural Considerations Implementation Considerations Power Management Network Future Directions & Conclusion
8 Largest Gains at Highest Level System Level Specifications SW-HW Partition Algorithms SoC Architecture Voltage Islands Voltage Gating Voltage Scaling
9 Advanced Power Management Voltage Islands Functions with separate Vdd Reduce dynamic power Voltage Gating Turn off Vdd to islands Huge leakage reduction Dynamic Voltage Scaling Vdd related to processing Reduce dynamic power
10 Agenda S3 Group View of Low Power Drivers Low Power Methodologies Architectural Considerations Implementation Considerations Power Management Network Future Directions & Conclusion
11 Technology Representative example for 90nm Higher Leakage Multi-Vth Optimization Voltage Gating
12 Architecture Level Common Issues Power Supply N/W Voltage islands & levels? Voltage gating? Retention in RAM or FF? Modes (idle, sleep, etc) Keep it simple by limiting the number of domains
13 IP Building-Block Block Selection IP is a growing % of overall chip power Select an established supplier you can trust Good technical interaction allowing due diligence is key Analog IP Make sure it is silicon proven at Vdd Look for power-down modes Beware of spec-man-ship Digital IP Check IP set up for low power flows Compare at target voltages and clocks
14 Fast ESL based Analysis HW-SW and Digital SoC High level synthesis allows more exploration Power-annotated ESL models much better than excel Mixed Analog-Digital ICs Huge increase in CMOS RF/Analog integration FastSpice or Verilog-AMS co-simulation with digital
15 Agenda S3 Group View of Low Power Drivers Low Power Methodologies Architectural Considerations Implementation Considerations Power Management Network Future Directions & Conclusion
16 Current Flows CPF/UPF Common Format (CPF), Unified Format (UPF) Many tools can use to specify power-specific data Constructs expressing power domains and their power supplies Power control logic (level shifters, isolation, retention etc) Definition and verification of power modes (standby, sleep, etc.) Common format for entire flow Design & Verification Synthesis, STA Physical Design Copyright Silicon & Software Systems Limited Slide 16
17 RTL Level RTL level design Partition the RTL into domains with ports to assert isolation etc Additional logic needed for control of voltage domains RTL verification Verify all uses cases and correct signals to/from gated domains Use CPF/UPF to check correct sequence of powering up/down
18 Design for Test Multi-threshold leakage optimization Increases number paths for at-speed testing Voltage islands at multiple voltages Restrict scan chains to one domain Test block in independent power domain Need to ensure test of level shifters etc Adaptive voltage domains Bridging & Delay faults are Vdd dependent Need to test at multiple voltages
19 Synthesis & STA Synthesis Traditional (Clock gating, synthesis re-structuring, leakage opt) Support of voltage islands with CPF/UPF Static Timing Analysis Multiply Supply/Multiple voltage (MSMV) means lots of runs ECSM and CCS allow dynamic voltage & temperature scaling
20 Physical Design Voltage Islands Floor-planning & domain definitions MSMV aware placement and clock tree Still need to check tool outputs Run formal verification Level shifter, isolation cell, retention placement etc
21 Agenda S3 Group View of Low Power Drivers Low Power Methodologies Architectural Considerations Implementation Considerations Power Management Network Future Directions & Conclusion
22 Advanced Power Management Dilemma Performance Risk Cost External PMU IC Can select optimal process & package Reliability & inventory (unless PSoC, PSiP) Complex PMUs add >50cent to OEM BOM Internal Regulators Customize to application, closer to point-of-load Re-spin, thermal issues, noise generated Area, IP license, additional verification NRE Time to Market Board design and validation overheads Integration overhead Integrate for high volume, low current applications
23 DC-DC versus LDO DC-DC Converter Large on-chip area (around 0.6mm^2) Lots of switching noise and poor PSRR Expensive external components High efficiency and low thermal impact Linear Regulator Poor efficiency (depends on drop) Low area (around 0.2mm^2) Low noise & excellent PSRR One/No external component
24 Consumer Applications Power Management Network is complex Lots of domains, mix of Analog and digital Large variation in current needed Cascaded structure Large DC-DC supplying multiple LDO High efficiency with good performance Optimal efficiency for a given area LDOs with drop out to fit application DC-DC with good efficiency at mean load
25 Optimal IP for Application Web interface for configuration of IP Web interface Not forced into point solution Optimal area, power & cost Semi-Automatic Generation Rapid IP turn-around Changes close to Tape-out
26 Power Switches Switch sizing Design for 1% drop Area versus leakage Hard macro Region 4 Region 1 Avoid Failures Prevent transient spikes Avoid supply bounce Region 3 Hard macro Region 2 Implementation Daisy-chain many small switches and embed in logic Slew rate control of one large transistor
27 Agenda S3 Group View of Low Power Drivers Low Power Methodologies Architectural Considerations Implementation Considerations Power Management Network Future Directions & Conclusion
28 Potential Future Directions Single language for capturing power intent Si2, Power Forward, Accellera etc should agree on this IP delivered with checkers for power intent Mainstream power-aware ESL tools Drag and drop voltage domains in tool Standardized & integrated with EDA tools Standardized ESL power models Deliver power models with IP
29 Conclusion Big power reductions needed for all applications Need holistic power management Big gains from Voltage islands, gating and scaling Power management has a large impact Complicates architecture and implementation IP selection and power supply network Needs improvement to maximize benefits Need improvement in ESL tools Standardized power models and power intent
30 Questions? Copyright S3 Group, v3.0
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