White Paper. SiC MOSFET Gate Drive Optocouplers. Introduction. Advantages of SiC MOSFET. SiC MOSFET Market and Adoption

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1 SiC MOSFET Gate Drive Optocouplers White Paper By Robinson Law, Applications Engineer and Chun Keong Tee, Product Manager, Avago Technologies Introduction Silicon Carbide (SiC) power semiconductors are rapidly emerging into the commercial market delivering several benefits over conventional Silicon-based power semiconductors. SiC MOSFETs can improve overall system efficiency by more than 0% and the higher switching capability can reduce the overall system size and costs. The technical benefits coupled with lower costs have increased the fast adoption of SiC power semiconductors in applications like industrial motor control, induction heating and industrial power supplies and renewable energy. Avago Technologies gate drive optocouplers are used extensively in driving Silicon-based semiconductors like IGBT and Power MOSFETs. Optocouplers are used to provide reinforced galvanic insulation between the control circuits from the high voltages and the power semiconductors. The ability to reject high common mode noise (CMR) will prevent erroneous driving of the power semiconductors during high frequency switching. This paper will discuss how the next generation of gate drive optocouplers can be used to protect and drive SiC MOSFETs. Advantages of SiC MOSFET Silicon Carbide is a wide bandgap (. ev) compound made up of silicon and carbon. Wide-bandgap SiC, besides being able to operate at high voltage, frequency and temperature, exhibits on-resistance and gate charge by an order of magnitude lower than silicon material. In an evaluation conducted by CREE to compare the second generation 00V/0A SiC MOSFET with a silicon high speed 00V/0A H IGBT using a 0KW hard-switching interleaved Boost DC/DC converter. The results showed that even with five times the switching frequency, the SiC solution was able to achieve a maximum efficiency of.% at 00 KHz, reducing losses by 8% from the best efficiency of the IGBT solution at 0 KHz. CREE s recent release of the CM family of MOSFETs provide engineers a wide range of competitively priced 00V and 00V SiC MOSFETs for a wide range of applications. Cree has been able to bring the cost down significantly while providing improved switching performance and lower Rds (on). Increasing the switching frequency can significantly reduce the size of the inductor. The lower conduction and switching losses allow engineers to reduce the size of the heat sink or potentially remove fans and move to passive cooling solutions. The smaller inductor and heat sink can reduce the system size significantly. Although a SiC semiconductor costs more than Si, the overall system BOM costs can be lower than Si technology by 0%. SiC MOSFET Market and Adoption SiC technology is now widely recognized as a reliable alternative to silicon. More than 0 companies worldwide have established SiC technology manufacturing capability with related commercial and promotional activities. Many power module and power inverter manufacturers have included SiC in their roadmaps for future products. Solar inverter manufacturers and Server power supplies are the earliest adopters of SiC semiconductors as efficiency is critical in their technological ranking. In 0, Europe s top solar inverter makers, REFU, SMA and Delta announced a new model with SiC inside. Photon magazine evaluated SMA SiC inverters and efficiency increased from 8% to % and inverters physical weight reduced by 0% as compared to equivalent IGBT inverter. With the increases availability, higher voltage variety and lower costs, SiC semiconductor production volume will ramp resulting in more adoption in applications like motor drives, railway traction industrial UPS and even hybrid vehicles. Avago Technologies gate drive optocouplers have been used extensively in driving Silicon-based semiconductors like IGBT. This paper will discuss how the improvements in the next generation of gate drive optocouplers can also be replicated to drive and protect SiC MOSFET.

2 SiC MOSFET Gate Drive Optoocouplers Avago Technologies has been working closely with SiC market leader CREE Inc, to determine suitable gate drive optocouplers to fit SiC MOSFET operations. We have evaluated gate drive optocouplers ACPL-W and ACPL-J with CREE CM SiC MOSFET using an 8A SEPIC DC-DC converter at 00 khz. The gate driving capability of these optocouplers met CREE s efficiency requirement of 8% as indicated in figure..0% Avago Gate Driver & Cree Gen SiC MOSFET Efficiency 8A SEPIC (DC-DC) Converter, 00 khz 8.0%.0% EFFICIENCY.0%.0%.0%.0%.0% ACPL-J (8/-V) + SiC MOSFET ACPL-W (0/0V) + SiC MOSFET IGBT.0% MOSFET Blocking Voltage Figure. Achieving high efficiency with Avago gate drive optocouplers & CREE CM00800D SiC MOSFET To match the low switching loss of CREE SiC MOSFET, the gate driver must be able to deliver high output current and voltage with fast slew rate to overcome the gate capacitance of the SiC MOSFET. The scope capture in figure shows ACPL-W with a 0V, fast rise and fall times signal profile at the gate of the SiC MOSFET which is necessary to switch the SiC MOSFET efficiently. Figure. ACPL-W SiC MOSFET gate signal profile

3 The ACPL-W is a basic gate driver optocoupler used to isolate and drive the SiC MOSFET operating at high DC bus voltage. It has a rail-to-rail output with.a maximum output current. The unique feature of ACPL-W, is the speed and is the industry s fastest in its class. The maximum propagation delay is 0ns and typical rise and fall times are around 0ns. The very high CMR, common mode rejection of 0kV/µs is required to isolate high transient noise during the high frequency operation from causing erroneous outputs. ACPL-W when coupled with a bipolar current buffer stage provides fast switching high voltage and high driving current to turn-on and off the SiC MOSFET efficiently and reliably. Compared to the older reference designs which used dedicated MOSFET driver with proprietary circuitry, the ACPL- W and the generic off the shelf bipolar current buffer offer a cheaper and easy to implement gate drive solution. VCC HIGH VCC HIGH RTN X +VIN -VIN +VOUT COM +VCC +0V u C RP-C RTN JP (V Input total) VCC HIGH VCC HIGH RTN RTN R R 0 C NM X +VIN -VIN RP-0D U ANODE NC CATHODE ACPL-W +VOUT COM -VOUT -V J (shorted by default) VCC VOUT VEE +V u u 0u C C J +VCC C 0V (open by default) R 0 Source U +VCC,8 * PBSS0SPN ½W 0R//0R//0R R R ½W R//R//R JP 8 Primary/Secondary Isolation Line, Short if and only if U is not needed C 0n C 00n C8 0µ R k Source JP 0 Figure. ACPL-W and CREE SiC MOSFET reference design

4 Driving and Protecting SiC MOSFET The ACPL-J is a smart gate drive optocoupler that can isolate, drive and protect SiC MOSFET in a single chip solution. In the functional diagram figure, the integrated SiC MOSFET short circuit detection and faults feedback features are highlighted in blue. It has the industry s first dual-output gate drive optocoupler uniquely designed to support the MOSFET buffer in the area highlighted in red. The device has a minimum output peak current of A optimized for driving both high-side and low-side MOSFET buffer stage. It features an internal active timing control circuitry preventing cross conduction and minimizing switching losses in the MOSFET buffer stage. V CC UVLO_P ANODE CATHODE, LED D R I V E R Drive Logic & Overlap Protection V OUTP V E SHIELD UVLO_N V OUTN V CC FAULT LED V EE DESAT DESAT V GMOS V GND, 8 SHIELD Figure. Functional diagram of the ACPL-J The main reason for using MOSFET buffers, which are made PMOS and NMOS, is because they are voltage controlled devices. The output of the MOSFET is able to switch very fast once its input threshold voltage (typically V) is crossed. In this way, the MOSFET buffer s level switching speed is independent of the previous gate drive optocoupler stage s level switching speed as shown in figure. ACPL-J MOSFET BUFFER SiC MOSFET 0ns 0ns Figure. Achieving fast switching time with MOSFET buffer

5 The scope capture in figure shows ACPL-J with bi-directional, fast rise and fall times signal profile at the gate of the SiC MOSFET which is necessary to switch the SiC MOSFET efficiently. Figure. ACPL-J and MOSFET buffer SiC MOSFET gate signal profile JP Fault RTN VCC HIGH VCC HIGH RTN RTN GND S R R R Vcc C C k 0p 0p 0n GND C n 8 NC CATHODE ANODE CATHODE V GND V CC FAULT V GND X +VIN -VIN X LM8L0ACZX Vcc IN OUT GND C C RP-D X +VOUT COM ACPL-J -VOUT V E DESAT V GMOS V CC V OUTP V OUTN V LED V EE +8V Vcc u u -V 0 Vcc C0 C C + + C µ Tant 0V C8 0µ Tant V + D µ Tant 0V DFLS0L C R 8 (½W) R R (½W) 00p SiDP Si88BDP Q Q 00 R 0 R R R0 (W) R8 R(W) J Q D BYME R0 0 Si8 k (½W) D R V BZG0C0TR Desat JP 8 JP 0 Primary/Secondary Isolation Line 0n 00n 0µ C C C Source Figure. ACPL-J and CREE SiC MOSFET reference design

6 To execute the short circuit protection, the drain-source voltage of the SiC MOSFET is monitored by ACPL-J during normal operation. When a short circuit occurs, high current flows through the SiC MOSFET and causes drain source voltage to increase rapidly. Once it crosses the ACPL-J s threshold of 8V, a short circuit fault is registered and soft shutdown is triggered. The ACPL-J s V GMOS pin will switch on an external transistor to slowly discharge the gate of the SiC MOSFET to achieve the soft shut effect. The entire short circuit protection is completed by reporting the FAULT through the insolated feedback path to the controller. During short circuit, a high overload current together with any parasitic induced current can result in high overshoot voltage if the SiC MOSFET is shutdown abruptly, which could be exceeding the SiC MOSFET breakdown voltage. To minimize such damaging overshoot voltage, ACPL-J does a soft shutdown when short circuit is detected. SiC MOSFET gate voltage is slowly reduced to low level off-state. The rate of soft shutdown can be adjusted through external MOSFET and resistance (Q & R0 in Figure ) to reduce the overshoot voltage level. Figure 8 shows high overshoot and ringing across the drain-source of the SiC MOSFET when doing a hard (or abrupt) shutdown during short circuit. (A low BUS voltage is used to prevent excessive damage to the SiC MOSFET during the experiment.) Figure shows how the high overshoot can be suppressed when the short circuit detection is triggered and gate is shutdown softly. Figure 8. Hard shutdown causing excessive V DS ringing during high current short circuit Figure. Soft shutdown reduces V DS ringing during high current short circuit

7 References. Dr Scott Allen, Silicon Carbide MOSFETs for High Powered Modules, CREE InC., March, 0.. Jimmy Liu, Kin Lap Wong, Scott Allen, John Mookken, Performance Evaluations of Hard-Switching Interleaved DC/DC Boost Converter with NewGeneration Silicon Carbide MOSFETs, CREE InC.. SiC Market 0, I-Micronews, May 0.. Alexandre AVRON, Overview of Wide Band Gap semiconductors in power electronics, YOLE Développement, April, 0.. ACPL-P and ACPL-W. Amp Output Current Power & SiC MOSFET Gate Drive Optocoupler with Rail-to-Rail Output Voltage in Stretched SO Package, Avago Technologies, AV0-08EN.. ACPL-J Dual-Output Gate Drive Optocoupler Interface with Integrated DESAT Detection, FAULT and UVLO Status Feedback, Avago Technologies, AV0-8EN. For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 00-0 Avago Technologies. All rights reserved. AV0-8EN - May, 0