LT1122 Fast Settling, JFET Input Operational Amplifier APPLICATIONS TYPICAL APPLICATION

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1 Fast Settling, JFET Input Operational Amplifier FEATURES n % Tested Settling Time ns Typ to mv at Sum Node, V Step ns Max Tested with Fixed Feedback Capacitor n Slew Rate V/µs Min n Gain-Bandwidth Product MHz n Power Bandwidth (V P-P ). MHz n Unity-Gain Stable; Phase Margin n Input Offset Voltage µv Max n Input Bias Current C pa Max C pa Max Input Offset Current C pa Max C pa Max Low Distortion APPLICATIONS n Fast -Bit D/A Output Amplifiers n High Speed Buffers n Fast Sample-and-Hold Amplifiers n High Speed Integrators n Voltage to Frequency Converters n Active Filters n Log Amplifiers n Peak Detectors DESCRIPTION The LT JFET input operational amplifier combines high speed and precision performance. A unique poly-gate JFET process minimizes gate series resistance and gate-to-drain capacitance, facilitating wide bandwidth performance, without degrading JFET transistor matching. It slews at 8V/µs and settles in ns. The is internally compensated to be unity-gain stable, yet it has a bandwidth of MHz at a supply current of only ma. Its speed makes the an ideal choice for fast settling -bit data conversion and acquisition systems. The offset voltage of µv, and voltage gain of, also support the -bit accurate applications. The input bias current of pa and offset current of pa combined with its speed allow the to be used in such applications as high speed sample and hold amplifiers, peak detectors, and integrators. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and C-Load is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION -Bit Voltage Output D/A Converter Large-Scale Response C F ma TO ma OR ma VOUT V TO V V/DIV -BIT CURRENT OUTPUT D/A CONVERTER C F = pf TO pf (DEPENDING ON D/A CONVERTER USED) TA ns/div A V = TA For more information

2 ABSOLUTE MAXIMUM RATINGS Supply Voltage... ± V Differential Input Voltage... ± V Input Voltage... ± V Output Short Circuit Duration... Indefinite Lead Temperature (Soldering, sec.)... C PIN CONFIGURATION (Note ) Operating Temperature Range AM/BM/CM/DM (OBSOLETE).. C to C AC/BC/CC/DC/CS/DS... C to 8 C Storage Temperature Range All Devices... C to C TOP VIEW V OS TRIM IN IN V 8 N8 PACKAGE 8-LEAD PDIP T JMAX = C, θ JA = C/W OBSOLETE PACKAGE J8 PACKAGE 8-LEAD HERMETIC DIP T JMAX = C, θ JA = C/W SPEED BOOST/ OVERCOMP V OUT V OS TRIM V OS TRIM IN IN V TOP VIEW 8 S8 PACKAGE 8-LEAD PLASTIC SO T JMAX = C, θ JA = 9 C/W SPEED BOOST/ OVERCOMP V OUT V OS TRIM ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE ACN8#PBF ACN8#TRPBF ACN8 8-Lead Plastic DIP C to 8 C BCN8#PBF BCN8#TRPBF BCN8 8-Lead Plastic DIP C to 8 C CCN8#PBF CCN8#TRPBF CCN8 8-Lead Plastic DIP C to 8 C DCN8#PBF DCN8#TRPBF DCN8 8-Lead Plastic DIP C to 8 C CS8#PBF CS8#TRPBF C 8-Lead Plastic SO C to 8 C DS8#PBF DS8#TRPBF D 8-Lead Plastic SO C to 8 C OBSOLETE PACKAGE AMJ8#PBF AMJ8#TRPBF AMJ8 8-Lead Hermetic DIP C to C BMJ8#PBF BMJ8#TRPBF BMJ8 8-Lead Hermetic DIP C to C CMJ8#PBF CMJ8#TRPBF CMJ8 8-Lead Hermetic DIP C to C DMJ8#PBF DMJ8#TRPBF DMJ8 8-Lead Hermetic DIP C to C ACJ8#PBF ACJ8#TRPBF ACJ8 8-Lead Hermetic DIP C to 8 C BCJ8#PBF BCJ8#TRPBF BCJ8 8-Lead Hermetic DIP C to 8 C CCJ8#PBF CCJ8#TRPBF CCJ8 8-Lead Hermetic DIP C to 8 C DCJ8#PBF DCJ8#TRPBF DCJ8 8-Lead Hermetic DIP C to 8 C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part markings, go to: For more information on tape and reel specifications, go to: For more information

3 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at., V CM = V unless otherwise noted. (Note ) CM/DM AM/BM AC/BC CC/DC CS/DS SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS V OS Input Offset Voltage 9 µv I OS Input Offset Current pa I B Input Bias Current pa Input Resistance Differential Common Mode V CM = V to 8V V CM = 8V to V Input Capacitance pf SR Slew Rate A V = 8 V/µs Settling Time (Note ) V to V, V to V % Tested: A- and C-Grades to mv at Sum Node B- and D-Grades to mv at Sum Node All Grades to.mv at Sum Node 9 ns ns ns GBW Gain-Bandwidth Product Power Bandwidth V OUT = V P-P. A VOL Large-Signal Voltage Gain V OUT = ±V, R L = kω V OUT = ±V, R L = Ω 8. Ω Ω Ω MHz MHz V/mV V/mV CMRR Common-Mode Rejection Ratio V CM = ±V db Input Voltage Range (Note ) ±. ± ±. ± V PSRR Power Supply Rejection Ratio V S = ±V to ±8V 8 8 db Input Noise Voltage.Hz to Hz.. µv P-P Input Noise Voltage Density f O = Hz f O = khz nv/ Hz nv/ Hz Input Noise Current Density f O = Hz, f O = khz fa/ Hz V OUT Output Voltage Swing R L = kω R L = Ω I S Supply Current..8 ma Minimum Supply Voltage (Note ) ± ± V Offset Adjustment Range R POT k, Wiper to V ± ± ± ± mv ± ±. ±. ± ± ±. ±. ± V V For more information

4 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at C T A C., V CM = V. (Note ) SYMBOL PARAMETER CONDITIONS CC/DC AC/BC CS/DS MIN TYP MAX MIN TYP MAX V OS Input Offset Voltage l µv Average Temperature Coefficient of l 8 µv/ C Input Offset Voltage I OS Input Offset Current l pa IB Input Bias Current l pa A VOL Large-Signal Voltage Gain V OUT = ±V, R L kω l 8 V/mV CMRR Common-Mode Rejection Ratio V CM = ±V l db PSRR Power Supply Rejection Ratio V S = ±V to ±V l db Input Voltage Range l ± ±.8 ± ±.8 V V OUT Output Voltage Swing R L = kω l ±. ±. ±. ±. V SR Slew Rate A V = l V/µs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at C T A C., V CM = V. (Note ) AM/BM CS/DS SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS V OS Input Offset Voltage l 8 µv Average Temperature Coefficient of l 8 µv/ C Input Offset Voltage I OS Input Offset Current l.. 9 na I B Input Bias Current l na A VOL Large-Signal Voltage Gain V OUT = ±V, R L kω l V/mV CMRR Common-Mode Rejection Ratio V CM = ±V l db PSRR Power Supply Rejection Ratio V S = ±V to ±V l db Input Voltage Range l ± ±. ± ±. V V OUT Output Voltage Swing R L = kω l ±. ±. ±. ±. V SR Slew Rate A V = l V/µs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at C T A 8 C., V CM = V. (Note ) AM/BM CS/DS SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS V OS Input Offset Voltage l 9 µv Average Temperature Coefficient of l 8 µv/ C Input Offset Voltage I OS Input Offset Current l 9 pa I B Input Bias Current l pa A VOL Large-Signal Voltage Gain V OUT = ±V, R L kω l 9 8 V/mV CMRR Common-Mode Rejection Ratio V CM = ±V l db PSRR Power Supply Rejection Ratio V S = ±V to ±V l db Input Voltage Range l ± ±. ± ±. V V OUT Output Voltage Swing R L = kω l ±. ±. ±. ±. V SR Slew Rate A V = l V/µs UNITS For more information

5 ELECTRICAL CHARACTERISTICS Note : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note : The is measured in an automated tester in less than one second after application of power. Depending on the package used, power dissipation, heat sinking, and air flow conditions, the fully warmed up chip temperature can be C to C higher than the ambient temperature. Note : Settling time is % tested for A- and C-grades using the settling time test circuit shown. This test is not included in quality assurance sample testing. Note : Input voltage range functionality is assured by testing offset voltage at the input voltage range limits to a maximum of mv (A, B grades), to.mv (C, D grades). Note : Minimum supply voltage is tested by measuring offset voltage to mv maximum at ±V supplies. Note : The is not tested and not quality-assurance-sampled at C and at 8 C. These specifications are guaranteed by design, correlation and/or inference from C, C, C, C and/or C tests. Settling Time Test Fixture DEVICE UNDER TEST pf LS GROUND ALL OTHER INPUTS V (REGULATED) Ω HA V 8 Ω V k % V k % V.k*.k V IN % % (MEASURE INPUT PULSE HERE) TTL IN LTCA 8 9 V.µF V V (REGULATED) µf TANT TYPICAL SUPPLY BYPASSING FOR EACH AMP/BUFFER NO CONNECTION ON PINS,,,, AND SETTLING TIME OUTPUT ( TIMES SUM NODE OUTPUT) N k.k V LT V V Ω 8 V 9Ω HA Ω SUMMING NODE OUTPUT N.µF µf TANT *THIS RESISTOR CAN BE ADJUSTED TO NULL OUT ALL OFFSETS AT THE SETTLING TIME OUTPUT. THE AUTOMATED TESTER USES A SEPARATE AUTOZERO CIRCUIT. TA For more information

6 TYPICAL PERFORMANCE CHARACTERISTICS Settling Time (Input from V to V) Settling Time (Input from V to V) Settling Time (Input from V to V) mv/div AT SUM NODE mv/div AT SUM NODE mv/div AT SUM NODE ns/div G ns/div G ns/div G mv/div AT SUM NODE Settling Time (Input from V to V) ns/div G V/DIV Large-Signal Response A V = ns/div G PEAK-TO-PEAK OUTPUT SWING (V) Undistorted Output Swing vs Frequency k M M M TPC GAIN (db) Voltage Gain vs Frequency 8 k k k M M M GAIN (db) Gain, Phase vs Frequency C L = pf M M 8 M 8 PHASE SHIFT (DEGREES) COMMON-MODE REJECTION RATIO (db) 8 Common-Mode Rejection vs Frequency k k k M M M TPC TPC TPC For more information

7 TYPICAL PERFORMANCE CHARACTERISTICS NUMBER OF UNITS 8 Distribution of Input Offset Voltage 9 UNITS TESTED IN ALL PACKAGES (NOT WARMED UP) 9 INPUT BIAS AND OFFSET CURRENTS (pa) k k k Input Bias and Offset Currents Over Temperature k k V CM = V BIAS CURRENT OFFSET CURRENT INPUT BIAS AND OFFSET CURRENT (pa) 8 Bias and Offset Currents Over the Common-Mode Range (NOT-WARMED UP) OFFSET CURRENT BIAS CURRENT INPUT OFFSET VOLTAGE (µv) CHIP TEMPERATURE ( C) COMMON-MODE INPUT VOLTAGE (V) CHANGE IN OFFSET VOLTAGE (µv) TPC Warm-Up Drift Noise Spectrum.Hz to Hz Noise SO PACKAGE N PACKAGE J PACKAGE IN STILL AIR (SO PACKAGE SOLDERED ONTO BOARD) VOLTAGE NOISE DENSITY (nv/ Hz) TPC k k k NOISE VOLTAGE (µv/div) TPC 8 TOTAL HARMONIC DISTORTION NOISE (%).... TIME AFTER POWER ON (MINUTES) TPC8 Total Harmonic Distortion Noise vs Frequency Inverting Gain Z L = k//pf V O = V RMS A V = A V = A V = k k k TOTAL HARMONIC DISTORTION NOISE (%).... TPC9 Total Harmonic Distortion Noise vs Frequency Noninverting Gain A V = A V = A V = Z L = k//pf V O = V RMS k k k INTERMODULATION DISTORTION (IMD) (%).... k TIME (SECONDS) Intermodulation Distortion (CCIF Method) vs Frequency and LF* A V = V O = V RMS Z L = k//pf k LF TPC k TPC TPC For more information *SEE LT DATA SHEET FOR DEFINITION OF CCIF TESTING TPC

8 APPLICATIONS INFORMATION Settling Time Measurements Settling time test circuits shown on some competitive devices data sheets require:. A flat top pulse generator. Unfortunately, flat top pulse generators are not commercially available.. A variable feedback capacitor around the device under test. This capacitor varies over a four-to-one range. Presumably, as each op amp is measured for settling time, the capacitor is fine tuned to optimize settling time for that particular device.. A small inductor load to optimize settling. The s settling time is % tested in the test circuit shown. No flat top pulse generator is required. The test circuit can be readily constructed, using commercially available ICs. Of course, standard high frequency board construction techniques should be followed. All s are measured with a constant feedback capacitor. No fine tuning is required. Speed Boost/Overcompensation Terminal Pin 8 of the can be used to change the input stage operating current of the device. Shorting Pin 8 to the positive supply (Pin ) increases slew rate and bandwidth by about %, but at the expense of a reduction in phase margin by approximately 8 degrees. Unity-gain capacitive load handling decreases from typically pf to pf. Conversely, connecting a k resistor from Pin 8 to ground pulls ma out of Pin 8 (with V = V). This reduces slew rate and bandwidth by %. Phase margin and capacitive load handling improve; the latter typically increasing to 8pF. The power supply connections to the must maintain a low impedance to ground over a bandwidth of MHz. This is especially important when driving a significant resistive or capacitive load, since all current delivered to the load comes from the power supplies. Multiple high quality bypass capacitors are recommended for each power supply line in any critical application. A.µF ceramic and a µf electrolytic capacitor, as shown, placed as close as possible to the amplifier (with short lead lengths to power supply common) will assure adequate high frequency bypassing, in most applications. V V µf.µf µf.µf TA When the feedback around the op amp is resistive (R F ), a pole will be created with R F, the source resistance and capacitance (R S, C S ), and the amplifier input capacitance (C IN pf). In low closed-loop gain configurations and with R S and R F in the kilohm range, this pole can create excess phase shift and even oscillation. A small capacitor (C F ) in parallel with R F eliminates this problem. With R S (C S C IN ) = R F C F, the effect of the feedback pole is completely removed. C F R F High Speed Operation As with most high speed amplifiers, care should be taken with supply decoupling, lead dress and component placement. R S C S C IN OUTPUT TA 8 For more information

9 TYPICAL APPLICATIONS Quartz Stabilized Oscillator With 9ppm Distortion V OUTPUT.k LT.V khz J CUT k pf k k DISTORTION TRIM LT MOUNT IN CLOSE PROXIMITY.k k.k OUTPUT AMPLITUDE TRIM V LT µf W V / LTC k V Q N9 V M k GROUND CRYSTAL CASE = VACTEC VTLC OR CLAIREX CLM k = N8 TA For more information 9

10 PACKAGE DESCRIPTION Please refer to for the most recent package drawings. N Package 8-Lead PDIP (Narrow. Inch) (Reference LTC DWG # -8- Rev I).* (.) MAX 8. ±.* (. ±.8).. (. 8.).. (..). ±. (. ±.).8. (..8) ( ). (.) TYP. (.) BSC NOTE: INCHES. DIMENSIONS ARE MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED. INCH (.mm). (.8) MIN.8 ±. (. ±.). (.8) MIN N8 REV I For more information

11 PACKAGE DESCRIPTION Please refer to for the most recent package drawings. J8 Package -Lead CERDIP (Narrow. Inch, Hermetic) (Reference LTC DWG # -8-)..8 (..) FULL LEAD OPTION. BSC (. BSC) CORNER LEADS OPTION ( PLCS).. (.8.) HALF LEAD OPTION. (.) MIN. (.) RAD TYP. (.8) MAX 8.. (.88.8). (.8) MAX.. (.8.).8.8 (..) NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS.. (..).. (..) OBSOLETE PACKAGE. (.) BSC.. MIN J8 8 For more information

12 PACKAGE DESCRIPTION Please refer to for the most recent package drawings. S8 Package 8-Lead Plastic Small Outline (Narrow. Inch) (Reference LTC DWG # -8- Rev G). BSC. ± (.8.) NOTE 8. MIN. ±..8. (.9.9).. (.8.988) NOTE. ±. TYP RECOMMENDED SOLDER PAD LAYOUT.8. (..).. (..8) 8 TYP..9 (..).. (..).. (..) NOTE: INCHES. DIMENSIONS IN (MILLIMETERS)..9 (..8) TYP. DRAWING NOT TO SCALE. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED." (.mm). PIN CAN BE BEVEL EDGE OR A DIMPLE. (.) BSC SO8 REV G For more information

13 REVISION HISTORY (Revision history begins at Rev B) REV DATE DESCRIPTION PAGE NUMBER B / Updated data sheet to current standards. New Order Information Table, Package Descriptions, - Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection For more of its circuits information as described herein will not infringe on existing patent rights.

14 TYPICAL APPLICATION Wide-Band, Filtered, Full Wave Rectifier k % µf k % k V IN k % k % k % k E OUT DC OUTPUT DC = RMS VALUE OF INPUT BANDWIDTH WITH V P-P INPUT = MHz TA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT High Speed Precision JFET Op Amp V/µs Min Slew Rate, µv V OS LT/LT Precision High Speed JFET Op Amps V/µs Slew Rate, µv V OS LT MHz C-Load Stable JFET Op Amp Capacitive Loads Up to nf LTC MHz Low Noise CMOS Op Amp pa I B, µv Max V OS,.µV P-P,.Hz to Hz Noise Linear Technology Corporation McCarthy Blvd., Milpitas, CA 9- For more information (8) -9 FAX: (8) - LT REV B PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 99