( 214 (represen ed by flipping) (magnitude = -42) = = -42 (flip the bits and add 1)

Transcription

1 1. Express 42 (decimal) in 8-bit binary = = 42 NOTE: This document is not officially endorsed by the Department of Informatics, or the lecturers responsible for CS1. It is simply a record of how I would approach the CS1 exam, were I sitting it. Thus, I cannot guaran ee that every single element is correct: as with anything you read on the In ernet you should double-check it s not absolu e shit :-) 2. Express -42 (decimal) in 8-bit sign and magnitude Sign Express -42 (decimal) in 8-bit one s-complement form ( 214 (represen ed by flipping) (magnitude = -42) 4. Express -42 (decimal) in 8-bit two s-complement form = = -42 (flip the bits and add 1) 5. Express (binary) in hexadecimal digits F (split in o groups of 4, with 10 = A, 11 = B e c.) 6. Express (binary) in oc al digits (0) (adding an extra leading 0 o make groups of 3) 2 5 2

2 7. Convert the 8-bit sign-and-magnitude form o decimal Sign = = 42 + sign bit = Convert the 8-bit one s complement form o decimal (flip the bits) = = 85 (as was in one s complement) = Convert the 8-bit two s complement form o decimal = = Convert the fixed-point binary form o decimal Positive Negative spectrum (2^-n or halving) = /2 + 1/8 = Evalua e the binary sum (carry the additional 1s over) (No e that addition here is strictly in binary, so there is not 2 but 1 0, which must be carried). 12. Evalua e in 8-bit two s complement for (decimal) S ep 1. Flip the bits of the second number and add one o it, in order o reverse its sign = =

3 S ep 2. Add the two numbers ogether (64) (-31) (1) = = Multiply (binary) by 11 (binary) x 1 1 (multiply by each bit) (0) (add a 0 for each bit multiplied, ignoring the overflow) (then add) 14. Divide the unsigned in eger by 1 1 S ep 1. Line up the long division S ep 2. Ask if the dividend on the left fits in o each bit in turn (left o right) of the divisor, when it does wri e a one at the op and rewri e the number below it S ep 3. Now subtract the newly formed row (braces from square brackets) [1 1] {1 1} 0 0 S ep 4. Res art the process o see if the dividend will fit in o the result of the subtraction. If not, bring down information from above.

4 1 1 1 [1 1] {1 1} S ep 5. In this ins ance, 11 does not fit, so we wri e a zero at the op and continue the process of brining down numbers from above until it does [1 1] {1 1} S ep 6. The process can now be repea ed and once your calculation is comple e, the answer is across the op: [1 1] {1 1} 0 0 [1 1] {1 1} 0 0 [1 1] {1 1} NB: To check your answers, you can convert the numbers o decimal, perform the division, re-convert, and see if the answers ma ch. 15. Display the binary represen ation of (decimal) according o the IEEE-754 single precision s andard. S ep 1. Convert o binary = S ep 2. Normalise so there is a single leading 1. (NB. You can move the decimal point both left and right o achieve this) x 2^2 S ep 3. Add the bias (this is done o allow for the represen ation of negative numbers)

5 Biased exponent = 129 ( ) = S ep 3. Slot this information in o the IEEE754 single-precision format sign (1-bit) exponent (8-bit) mantissa (23-bit) 0 (because the number is positive (this information is additional)) sign (1-bit) exponent (8-bit) mantissa (23-bit) (copied directly) sign (1-bit) exponent (8-bit) mantissa (23-bit) (copied without the leading 1 which is implicit and padded with 0s) Final answer: How many by es (words) of RAM can be addressed using 16 bits No e the rule that with n bits, we can address 2^n locations. So we can address 2^16 = locations. 17. How many by es are needed o address 4GB of RAM? There are approxima ely 1 billion by es in a gigaby e. So 4 billion in 4 gigaby es. 2^32 is roughly 4 billion, so we will need 32 bits o address these by es. Thus, 32 / 8 = 4 by es o address these by es. 18. If a PC with a 4GHz clock can process an average of one machine instruction every 100 clock cycles, what is its average processing ra e in MIPS (millions of instructions per second)? 1Hz is 1 cycle of compu ation per second. If we can process 1 instruction every cycle, then in 1Hz we can do one instruction. If we imagine that in 1Hz we can do 1 instruction then in a mhz (1 million Hz) we can do 1,000,000 instructions (cycles). Similarly, in a ghz we (1 billion Hz) we can do 1 billion instructions; in 4ghZ we can do 4 billion instructions (cycles), per second.

6 By this reasoning, if it does not ake 1 cycle o comple e an instruction, but ins ead 100, then our millions of instructions per second is: 4,000,000,000 / 100 = 40 million (instructions per second) 19. Find the maximum relative error of IEEE-754 single precision represen ation. NB: Answers in square brackets are consis ent with January 2012, answers WITHOUT are consis ent with January 2010/2011. This requires clarification. Because we have a limi ed number of bits o represent numbers in the IEEE format, sometimes the results of operations are of a larger precision than the space we have o represent them. For example, the largest decimal precision we can represent in our mantissa in single precision IEEE-754 is 2-23 (23 bits) [plus the normalised bit, ] We therefore want o know what is the most information we can lose if a result of an operation is larger than 2-23 [2-24 ] i.e. if the result produces a number of size 23 [24] bits+. The answer, is simply 2-24 [2-25 ] because this captures the largest number by which the result could differ from what we want. Because [2-25 ] 2-26, 2-27 e c. onwards owards infinity will always be smaller, this is accura e. 20. Find the maximum value in the IEEE-754 single precision represen ation. Recall the division of single prevision as the following: sign (1-bit) exponent (8-bit) mantissa (23-bit) Because we have o add a bias, the maximum exponent we can represent before adding said bias is 255 (because we only have 8-bits, the maximum number that can be represen ed in this space is (2^n) - 1) = 128. The maximum mantissa we can represent is 2 - (2^-23) - why? Because we have 1 from our implicit normalised bit, added o a summation of the floating point numbers. So, for example:

7 = 1. [ e c e c ] which roughly equals which is roughly equal o 2. Our maximum mantissa is therefore 2.0 * 2^128 so 2^ What happens if the absolu e value of a single-precision number is grea er than this value? The number cannot be adequa ely represen ed in the space available so a floating point overflow exception occurs. Overflow can be indica ed when the sign of the result is incorrect. 22. Find the minimum positive value in the IEEE-754 single precision represen ation In a similar manner o the maximum represen ation, the minimum positive represen ation is the smallest positive floating point number which can be represen ed. Again, due o the bias, the smallest negative exponent we can represent is -127, because adding this exponent on will produce 0, which is the least we can represent in the exponent bits of the IEEE format. (000 (represen ed) ( aking off the bias) = - 127). Similarly, the minimum positive mantissa we can represent is 1.0, because we *have* o have the normalised 1, but can add o this nothing, by setting the entirety of the mantissa o What happens if the absolu e value of a single-precision number is smaller than this value? If the result of an arithmetic operation on a floating point number is less than the value we can represent (in this case it goes on o the negative spectrum), we underflow o 0, which means that we simply record the result as a negative number. This is ok, because it still sufficiently approxima es the result. 24. List the s eps that occur in the addition of two floating-point numbers x 2^ x 2^1

8 S ep 1. Shift the exponents so they are equal (we usually shift the smallest one up o the biggest) x 2^ x 2^4 S ep 2. Add (or subtract) the mantissa as normal x 2^4 S ep 3. Renormalise (if necessary) adjusting the exponent x 2^5 25. List the s eps that occur in the multiplication of two floating-point numbers (2.4 x 10^5) x (3.0 x 10^3) S ep 1. Subtract a bias from the exponent (if one exists) and then add the exponents ogether S ep 2. Multiply the mantissas ogether 7.2 x 10^8 S ep 3. Normalise the product if necessary, adjusting the exponent 26. Distinguish between carry and overflow Carry usually occurs in the addition of binary numbers and is the ins ance in which the sum of two numbers exceeds the available number of bits in the represen ation. In this case, the extra bits are passed up o the next higher magnitude position. If there is no higher magnitude position (i.e. nothing af er the MSB), then overflow occurs. 27. Distinguish between borrow and underflow Borrowing usually occurs in a binary subtraction and is the process by which a lower order bit must request a bit from a higher order one in order o comple e the compu ation. In the following example, the second 0 in the op row must borrow from the MSB in order o comple e the subtraction.

9 In this ins ance however, the MSB would then become 0, and the resulting subtraction would require 0-1. With nothing af er the MSB, no borrowing can ake place and we now have underflow. 28. Name four disk-scheduling algorithms and s a e which of these is likely o exhibit the best performance under high disk utilisation. When information is read from disk, the largest time over-head is the movement of the desired disk sec or under the read/wri e head. In erms of optimisation therefore, we seek o reduce this time in anyway way we can. One echnique o do this is o schedule the requests of processes o disk in an order which reduces disk movement. Under First come first serve, the requests by processes are at ended o in order. This is clearly the most ineffecient performance. The next most efficient echnique is shor est seek time first which orders requests so that the disk arm always moves o the request next in the queue closest o its current location. This, however, could result in disk tracks which are furthest away never being serviced. A more complex scheduling echnique is known as the eleva or algorithm or SCAN, which sweeps up and down the surface of the disk picking up areas o be read as it moves, similar o how a lift moves in a ower block. A variant of SCAN, C-SCAN, only reads in one direction, so, using the lift analogy, if it is moving upwards across the disk and there is information o be read below, it must first come back o the bot om and then move upwards again o read information. LOOK and C-LOOK al er this process by not going all the way up and down the disk, but only o those highest numbers o be read and those lowest numbers o be read. Under high disk utilisation, the performance of these echniques increases in ascending order. 29. Name four eviction stra egies for cache blocks or virtual memory pages and s a e which of these is likely o exhibit the best performance under high memory utilisation.

10 Under fully-associative cache, we do not have a direct mapping between main memory addresses genera ed by the CPU and cache, in fact, i ems from main memory can be placed anywhere in cache. In this ins ance, we need o decide on a victim block o remove from cache. These are known as replacement policies and can be of the following forms: random, where we simply randomly replace a block; first in first out, where we remove the block that has been in cache the longest; least recently used, where we remove the block with the oldest times amp; and least frequently used. These are lis ed in ascending order of performance under high memory utilisation. 30. De ermine the maximum speed-up over the sequential execution of (a) a pipelined instruction processing unit comprising six segments and (b) a pipelined floating-point addition unit comprising four segments. Pipelining is the process of at empting o speed up execution time for a ba ch of asks by running them in parallel. For example, we can run the Fe ch-decode-execu e cycle in parallel o process a number of instructions simul aneously. We can formalise this idea with the following equation: ( k x tp ) + ( n - 1 ) tp, where: k is the number of segments or s ages tp is the time per s age and n is the number of instructions or asks. Intuitively this equation says the following: k x tp ells us how long it akes for our first ask. If there are k s ages o the pipeline (k things o do as part of one instruction) then the minimum amount of time is going o be this value multiplied by tp. ( n - 1 ) tp ells us how many more time s eps we need for those parallel instructions which were not able o s art straight away; we say that each one emerges from the pipline, so we need ( n - 1 ) * tp time o do the extra processing which could not be done entirely sequentially. We can rearrange this formula o read as follows: (k + n - 1) tp Our speed up in this ins ance, is therefore our time WITHOUT any pipeline s ages divided by our new speed:

11 s = n x ( k x tp ) [k is 0 by default so n x tp ( asks by time)] divided by (k + n - 1) tp Assuming an infini e number of instructions passing through our pipeline, we actually find that (k + n - 1) ends o the value of n. Thus, we can cancel this, its replacement value of n and tp from the op and bot om our equations leaving just k. So speed up, is effectively EQUAL o the number of s ages in the pipeline. Thus for 6 segments we get 6 and for 4 segments we get Under a pipelined sys em, explain why maximum speed-up cannot be achieved in practice. Although it may appear that speed is entirely proportional o the number of extra s ages in a pipeline, there are several reasons why this is not entirely true. Firstly, there is a fixed overhead of moving da a from memory o regis ers (so-called pipeline s artup ) which cannot ever be comple ed reduced. Moreover, as we add more s ages, the amount of control logic o implement the pipeline increases. Particular pieces of code, such a branching or conditional s a ements, also cause issue with parallel execution. If several instructions are being decoded simul aneously, the conditions enforced by a branch s a ement may be circumven ed, executing code that should not be execu ed. To overcome this issue, pipeline sys ems may specula e about which code will be needed in the future in the form of speculative branching. 32. List the s eps of the Fe ch-execu e Cycle 1. The control unit in the CPU fe ches the next instruction from memory by using the program coun er o de ermine where this next instruction is loca ed. 2.This instruction is then decoded in o a language sui able for the ALU 3. Any da a complementing or required by the instructions are also fe ched from memory and s ored in regis ers 4.The ALU then execu es the instructions and places the results either back in o the regis ers or in o memory. 33. Why are compu ers of en provided with one or more cache memories?

12 As we are striving for the most efficient archi ectures, cache memory aims o address the disparity of speed between main memory on the CPU by providing a fast (yet size limi ed) most recently accessed s ore for da a and instructions. Once information is processed by the CPU it is s ored in the cache, along with information which may be relevant in the future. In this way, overall access time is reduced. 34. Why are compu ers of en provided with paged, virtual memory? The virtual address space which a programmer uses o construct their programs differs from the actual physical address space in which said program resides. Physical address space is not one continuous address but ins ead addresses spread over a number of different media. Main memory, for example, is of en oo small o hold the entirety of a program, so hard disk is used as an ex ension o RAM. To main ain order within this sys em, the units swapped in and out of main memory and the hard disk are s ored in fixed-size pages. Although such a sys em allows for an almost arbitrary ex ension of main memory, access o the hard disk is dramatically slower than o main memory.