CL2bm1 Atmel AVR CPU board: main features and combination with M4/E peripheral expansion

Transcription

1 GENIERIA CL2bm1 Atmel AVR CPU board: main features and combination with M4/E peripheral expansion Ing. Rafael Oliva - L&R Ingeniería 1. Introduction: CL2bm1 board is an evolutionary step from previous data-logging design (DLCy - based on the PSoC 1 architecture), seeking to meet requirements of greater data storage capacity using flash memory SD cards. This CPU board is based on 8-bit AVR controllers and the socket can be fitted with AtMega32 to ATMega1284P controllers in DIP40 formats, with up to 128KB of Flash. These boards have been used in rigorous climate, isolated systems applications for oil-industry and testing systems since october 2010, with very good results. Figure 1 shows a block diagram of the board. CL2_b Proto (AtMega32/644/1284) Rev5F-2010 (C) R.Oliva - L&R Ing. 2009/10 +B nr Fuente Lineal LM / 7805 (644P) PD.2:3 MAX232 RS232/COM1 USB USB LPF XTAL OSC E6 AVCC AVCC ATMega1284P ATMega644P ATMega32 PD.0:1 MAX232 PMOS 5V/3.3V 6P/10P ISP RS232/COM0 ANin X8 ANLG PA.0:7 SD_PWR +3V3 SD Socket SD CARD KBDin CTRL PD7 LCD_BL PB.0:3 PD select PD5 PB4:7 PC.0: RTC SD_STATUS JTAG DATA PC.2:7 PCA9538 EXTER. 8b I/O LCD CONN. 2X8 SD_STATUS 10x2 y 17x2 XTAL o TXCO 5XEXP SD_PWR Figure 1 - Block diagram of CL2bm1 CPU board 2010 version B 3V Current systems use mostly the ATMega1284P controller, with 128 KB of Flash, 16 KB of RAM, 2 KB of EEPROM and two serial ports, running at 14.4 MHz. Main components are: a) Power supply with LDO regulators for +5 y 3.3V, up to 16V input (8-12V recommended). b) Analog inputs for onboard 10-bit ADC c) 4 contact membrane keyboard interface ARGENTA L&R GENIERIA

2 GENIERIA d) Character LCD interface. e) expansion port and PCF8563 Real Time Clock with TXCO. f) SD card interface g) Serial RS232, and socketed USB module (FT232). h) PCA9538 I/O port bus communications are used to communicate with an auxiliary board based on PSoC-1 family of microcontrollers.this board also offers an I/O interface for the PCA9538 device. Figure 2 - CL2bm1 board assembly 2. Programming: The ATMega1284P controller on CL2bm1 can be programmed in C using compatible cross-compilers, typically CodevisionAVR from HPInfoTech [HPI,2012], or AVR Studio 6 from Atmel. Programs are compiled on a standard PC and downloaded to the board via a 6 pin ISP connector, using the low cost USB ATAVRISP2 interface from Atmel. Field upgrades and EEPROM saving are straightforward. Programming interface is as shown on Figure 3 (left). ADC channels are general purpuse 10- bit resolution, if greater resolution is required 3 13-bit ADC inputs are available on the M4/E. The serial COM0 port can be routed to the FT232/USB module or towards the half DS14C232 interface, COM1 can be routed to the other DS14C232 half or to an (DS3695) interface with optional hardware Driver Enable circuit. ARGENTA L&R GENIERIA

3 GENIERIA MAPA LOGICO E/S CL2bm1 / AtMega1284P L&R Ingeniería R.Oliva Rev Canales A/D PA.7 PA.6 PA.5 PA.4 PA.3 PA.2 PA.1 PA.0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 PB.7 PB.6 PB.5 PB.4 PB.3 PB.2 PB.1 PB.0 SD-CARD SCK/ MISO/ MOSI/ SD SD SD -CS /SD ABJ DER ARR IZQ TECLADO PC.7 PC.6 PC.5 PC.4 PC.3 PC.2 PC.1 PC.0 LCD DB7 DB6 DB5 DB4 R/-W RS SDA SCL PD.7 PD.6 PD.5 PD.4 PD.3 PD.2 PD.1 PD.0 OLED LCD_ BL_ OLED E TP PD4_ T TxD1 RxD1 TxD0 RxD0 SERIAL USB/RS232#0 USB/RS232#0 /RS232#1 /RS232#1 -T1/CK/IRQ_CK Figura 3 I/O logic from the CL2bm1 board, and compiler output of C CodevisionAVR from HPInfotech Although most applications are interrupt-based and use no underlying operating system, it is technically viable to use FreeRTOS on ATMega1284P with a very small footprint. 3. Aplications: A number of these boards have been used since end of 2010 in isolated systems in oil industry (Figure 4), to control hybrid wind/pv power systems for chemical dosification pumps in oil wells. Figura 4 CL2bm1 (left) in hybrid system for oil industry Paraje Boleadoras/Campo Indio () ARGENTA L&R GENIERIA

4 GENIERIA Others have been used for small wind turbine testing and certification, withing systems known as PWRC2. These use a CL2bm1 board, coupled to a TRIADC simultaneous 13bit-ADC module on the M4/E board to sample DC voltage and current. These systems also sample wind intensity, direction, temperature and barometric pressure, to statistically generate a small wind turbine power curve under IEC (2005) Annex H. An external METEO module, based on PSoC 1 communicates via with the CL2bm1 board. On Figure 5 recently installed PWRC2 systems for the Small Wind Testing facility from TI (National Industrial Technology Institute) in Cutral-Có / Neuquén, Argentina. Power supply is from a 24V DC UPS, a series of LM2576 modules bring down the voltage to 10.5V to supply the CL2bm1, M4E, sensor and external METEO module (Figure 6). An external Secondwind Nomad2 reference station is supplied with 14.4V from the same UPS. Figure 5: PWRC2 testing systems based on CL2bm1 and M4/E boards at TI Testing facility in Cutral-Có Neuquén. Top left - SCADA access using Modbus from each CL2bm1. ARGENTA L&R GENIERIA

5 GENIERIA Figura 6: METEO v1.1 (2012) and installation at TI Cutral-Có 4. Peripheral board M4/E with I/O using PSoC 1 as an slave: M4/E is used for analog and digital I/O with over-voltage protection. in communication with the main CL2bm1, based on Cypress PSoC I controllers working as -slaves. Typical installation is shown coupled to CL2bm1 (Figure 9), its block diagram appears in Figure 7, and programming model in Figure 8. A CL2B M4-EXPANSION - BOARD (C) R.Oliva - L&R Ing IO3 -IO3 RELAY K2 -> DRY CONTACT -IO4 -IO5 -IO6 -IO7 -IO4 -IO5 -IO6 -IO A CL2B -T SDA SCL +B = +14.4V Power Supply ANi1 ANLG V1 P0.7 P1.7 P V ANi2 ANi3 V2 V3 P0.5 P0.3 P0.4,6 VT(TC1047A) TEMP P P2.6 P2.4 P2.2 P2.0 PSoC P0.2 P0.0 RELAY KAUX -> DRY CONTACT P1.3 P2.1 P2.3 P2.5 P2.7 P1.2 P1.2 P1.2 0=PWR_OK 1=BUZZ 2 Figure 7: M4/E block diagram, connected auxiliary board for CL2bm1. ARGENTA L&R GENIERIA

6 GENIERIA 5. References: [HPI,2012] HP InfoTech S.R.L. [Oliva y Cortez, 2011] Oliva, R. y Cortez, N. Aspectos de implementación en una interfaz para controladores PSoC y AVR II Congreso de Microelectrónica Aplicada 2011, F.I. UNLP, 7 al 9 de setiembre de 2011, pp. 84, ISBN [PSoC 1, 2011] Cypress PSoC 1 architecture Figure8 : Logic I/O model for M4/E ARGENTA Figure 9 - M4/E board coupled to a CL2bm1 with. L&R GENIERIA