Carlos Villavieja, Nacho Navarro Arati Baliga, Liviu Iftode
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1 Continuous Monitoring using MultiCores Carlos Villavieja, Nacho Navarro Arati Baliga, Liviu Iftode
2 Motivation Intrusion detection Intruder gets privileged user Data coming from the network Exploit software flaws Access to the whole memory Not a Intrusion Detection System but an Observation Room Application level: control flow graph
3 Motivation Dynamic monitoring requires hardware support to reduce monitoring overhead and perturbation Detection of anomalous behaviour Not taken control flow paths (requires training?) Not enough information at compile time
4 Opportunity Chip Multiprocessors/MultiCore as opportunity to: 1. Parallelize applications to make them multithreaded 2.Use the extra computational power to make applications more reliable. (p.e: Continuous Monitoring) 3.Shared cache (next slide)
5 Computer Architecture Scenario Intel Core Duo Core1 Core2 Increasing number of cores. Bus 2 MB L2 Cache Niagara 2 (Dec-07) L2 or L3 shared cache Common memory bus Faster Inter Processor Interrupt
6 Common Application problems Bugs/Attacks change application behaviour Buffer Overflows Dangling pointers Uninitialized data Memory errors (soft errors) Control Flow Attack Code Injection Attacks (shellcodes)
7 Framework Architecture Application Observation Room 1 2 Medical Check Probe code: - Send - Stop - Resume Memory variables - Control Flow Graph - Value based Invariants - Trusted Code - Commit / Rollback? L2 CACHE OPERATING SYSTEM USER KERNEL MULTICORE HARDWARE
8 Framework Architecture CORE 0 CORE 1 Application Monitoring Threads 1 SHARED BUFFER 2 Binary Rewritten L1 CACHE L2 CACHE L1 CACHE - Inserted Probes - Memory pattern unchanged - Control Flow Graph available at runtime - Monitor: - Check variables values - Check code source - Check exe timing.
9 Idea: Continuous Monitoring DUAL CORE ARCHITECTURE CORE 0 = APPLICATION CORE (AC) CORE 1 = MONITORING CORE (MC) HOSPITAL!!!! AppThread Threads Monitoring Threads Memory access patterns (Observation room) Control Flow graph Same address space Assumption: Protected Domain
10 Monitoring Co-Scheduling Scheduling Rules - threads that make up a single process AppThreads (AT) + Monitoring Threads(MT) Affinity: Always schedule in the same core -MT always scheduled before AT - Useful for applications where performance severely degrades when any part of the application is not running. Threads often need to synchronize with each other Timing purposes Minimize detection time
11 Binary Rewriting tool: Inserting probes Source Code Compile Object Files Link Executable [*.c] [*.o] [*.exe] Application binary rewritten Available Information Executable [*.exe] - Relocation information - Application control flow graph: - Post link time optimizer - Built a Binary Rewriter fronted - basic blocks - function list
12 Proofs of concepts 1. Monitor Function Calls Return Address Monitor Threads checks return address for every function call 2. Monitor Basic Blocks EDGES Probe call/jmp edges to verify basic block entry & exit points
13 Case 1: Return address check
14 Case 1: Return address check int biggest(int *vector,int len) { int i=0,tmp=-1; for (i=0;i<len;i++) { if (vector[i]>tmp) tmp=vector[i]; } return tmp; } int main(int argc,char *argv[]) { int elements[n]; int result=0; generaterandom(elements); result=biggest(elements,n); printf( Biggest %d,result); return 1; }
15 Case 1: Return address check Monitoring Thread: Builds a Shadow Stack Function calls are binary rewritten (augmented with probes) Trusted libs: optional binary Main Module call graph rewritten
16 Case 2: Control Flow Integrity(CFI) Monitor application at a finer granularity: Basic Block Level (BBL)
17 Case 2: Control Flow Integrity Identify entry & exit points (instructions) at each BBL Trust begin and end of bbl Check ID ID Check ID ID_2
18 Observation Room Monitoring Threads Run in separate core Full access to application memory Processor Trusted Mode Security capabilities Hidden core (Example Cell SPU) Monitoring data remains secure Isolated memory from application
19 Evaluation Intel(R) Pentium(R) D CPU 3.73GHz, 1GbRam 2MB shared L2 Cache Linux kernel Diablo back-end (0.5)
20 Results: code size overhead PRELIMINARY RESULTS - 13,8% average increase because bin rewriter - 57% Code size reduced (Dead Code Elimination) 9.00E+005 Code Size Bin size 8.00E E E E E E E E+005 Gcc NoDeadCode MafMA 0.00E+000 Rawcaudi o Rawdaudi o Gzip Djpeg cjpeg wrjpgcom rdjpgcom jpegtran
21 Conclusions First tests - return address checks Control Flow Graph enforcement is viable Availability of CFG at runtime Synchronization is possible Where the bug came from? Co-Scheduling and L2 cache hit minimize the overhead
22 Future Work Further testing: Execution synchronization/overhead Evaluate Need of attack benchmark Full memory 'control' is the final goal Monitoring Thread protection mechanism Kernel can be tampered but neither should MT Detect? - Recover (Transactional system)
23 THANK YOU!! Questions?
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