A Multi-Core Pipelined Architecture for Parallel Computing
|
|
- Morris Byrd
- 8 years ago
- Views:
Transcription
1 Parallel & Cloud Coputing PCC Vol, Iss A Multi-Core Pipelined Architecture for Parallel Coputing Duoduo Liao *1, Sion Y Berkovich Coputing for Geospatial Research Institute Departent of Coputer Science, George Washington University 1 nd Street NW, Washington DC 5 USA *1 dliao@gwuedu; berkov@gwuedu Abstract- Parallel prograing on ulti-core processors has becoe the industry s biggest software challenge his paper proposes a novel parallel architecture for executing sequential progras using ulti-core pipelining based on progra slicing by a new eory/cache dynaic anageent technology he new architecture is very suitable for processing large geospatial data in parallel without parallel prograing his paper presents a new architecture for parallel coputation that addresses the proble of requiring to relocate data fro one eory hierarchy to another in a ulti-core environent A new eory anageent technology inserts a layer of abstraction between the processor and the eory hierarchy, allowing the data to stay in one place while the processor effectively igrates as tasks change he new architecture can ake full use of the pipeline and autoatically partition data then schedule the onto ulti-cores through the pipeline he ost iportant advantage of this architecture is that ost existing sequential progras can be directly used with nearly no change, unlike conventional parallel prograing which has to take into account scheduling, load balancing, and data distribution he new parallel architecture can also be successfully applied to other ulti-core/any-core architectures or heterogeneous systes In this paper, the design of the new ulti-core architecture is described in detail he tie coplexity and perforance analysis are discussed in depth he experiental results and perforance coparison with existing ulti-core architectures deonstrate the effectiveness, flexibility, and diversity of the new architecture, in particular, for Big Data parallel processing Keywords- Multi-Core Architecture; Pipelining; Sequential Progras; Progra Slicing; Crossbar Switching; Parallel Coputing; Big Data I INRODUCION As ulti-core architectures gain widespread use, it becoes increasingly iportant to be able to harness their additional processing to achieve higher perforance However, exp loit ing parallel cores to ip rove singleprogra perforance is difficult fro a prograer s perspective because ost existing prograing languages dictate a sequential ethod of execution Parallel prograing on ulti-core processors has becoe the industry s biggest software challenge Because ulti-core hardware architectures are changed to parallel structures, single-processor based software has to be optiized or even rewritten with uch work to eet the hardware constraints However, if we can change the hardware to eliinate the constraints, ost of existing single-processor software progras ay be directly used with iniu changes or even without any change For this purpose, this paper proposes a new parallel architecture using ulti-core pipelining based on progra slicing by crossbar switching and a new eory/cache dynaic anageent technology he new architecture can autoatically partit ion data and schedule the onto ult i- cores through the pipeline his architecture provides a siple and effective solution to the on-the-fly coputations by transferring the operating states fro core to core he ost iportant advantage is that it only requires practically the sae software as currently used based on singleprocessor syste, instead of conventional parallel coputing ethods, such as threading, load balancing, and scheduling he rest of this paper is organized as follows: Section gives a broad overview of the backgrounds and related work thus far Section 3 describes the detailed design of the new parallel architecture using ulti-core pipelining based on progra slicing by switch applied It contains crossbar switch based ulti-core eory and cache architecture, ulti-core pipeline organization, tiing diagra, and progra requireents Section gives the tie coplexity, perforance, and experiental analysis In particular, the exaples of large geospatial data processing, such as Digital Elevation Model (DEM) generation fro Light Detection and Ranging (LIDAR) dataset, are discussed Finally, the suary and advantages are concluded in Section 5 II BACKGROUNDS AND RELAED WORK A Conventional Parallel Coputing In general, there are three ajor approaches used for ultiprocessor processing [9] [1] : Data-parallel: partitions data and schedule the onto the ultiple processors, ask-parallel: Partitions a progra into functions/tasks and schedule the onto the ultiple processors, Pipeline-parallel: decoposes a progra and run each state siultaneously on sequential eleents of the data flow he first approach is suitable for the data-independent circustance However, the scheduling ay be coplicated depending on the application progras PCC Vol Iss, 13 PP 9-57 wwwvkingpubco 13 Aerican V-King Scientific Publishing 9
2 Parallel & Cloud Coputing PCC Vol, Iss For the second ethod, in practice, it is often difficult to divide a progra in such a way that separate CPUs can execute different portions without interfering with each other Furtherore, this type of parallel processing requires very sophisticated software For the third parallel coputing ethod, a pipeline is coon paradig for very high-speed coputation he pipeline parallelis allows for parallelization of a single task when there is a partial or total order in the dataset iplying the need for state and therefore preventing the use of data parallelis his approach is liited by the sequential decoposability of the task and the length of the longest stage In this paper, the new architecture uses a new parallel echanis in cobination with data-parallelis and pipeline-parallelis It can autoatically partition data and schedule the onto ulti-cores through a pipeline without changing original single-processor progra, instead of decoposing the entire progra as conventional pipelineparallel ethod does or scheduling as conventional dataparallel ethod needs B Multiprocessor Pipeline by Progra Slicing Another proising parallel coputing ethod is based on the ulti-processor pipeline architecture by dividing the progra in equal duration by forced interrupts as described in [] [] [5] his technology has US PAEN No 1571 issued in and owned by he George Washington University It can autoatically schedule the progra onto the ultiple processors he architecture processes an inforation flow progressively in a helicoidal pattern by relocating portions of incoing data his pattern ensures that the incoing data flow will not be interrupted he ulti-processor pipeline allows an arbitrary algorith to be perfored on-the-fly on a data chunk, given a sufficient nuber of processors If an algorith can be perfored by a conventional icroprocessor under static conditions, it can be perfored on the ultiprocessor pipeline Another advantage of this architecture is to use practically the sae software as a sequential coputer and to be able to continuously process the intensive inforation flows his ulti-processor pipeline is a siple and effective solution to the proble of continuous processing of intensive flows of inforation his technique has been proposed to be used for effectively processing the challenging proble of very intensive continuous flows of data [3] However, there are several liitations for soe applications Frequent data relocation especially for large data block applications like 3D graphics and iage processing can cause big overhead costs leading to the overall perforance decrease [1] he syste described in [] uses data overlapping to solve the proble of processed data chunks across the segentation iposed by the buffer size he aounts of eories of the processors have to be occupied by these duplicate (ie overlapped) data Moreover, to reduce the bus traffic, the data relocations, ie the loadings/unloadings, are arranged so that only one data chunk relocates in one shared bus at a particular tie Additionally, for the data required longer pipeline to process, the pipeline need special handling, such as overflow facility or accuulation and then sending back while the data strea ceases In this paper, the core difference between the new ultiprocessor pipeline and original one [] [5] is that the new pipeline is driven by crossbar switching instead of forced interrupts Hence, the novel crossbar-switching based ultiprocessor architecture with a new eory/cache anageent technology significantly overcoes all the above liitations of the original ultiprocessor pipeline C Multi-core Architectures and Prograing Currently ulti-core processor architectures are divided into two basic categories: generic ulti-core CPUs and Graphics Processor Units (GPUs) he Intel [11] and AMD [1] provide a large nuber of ulti-core CPUs in the arket Both of the released dual-core chips in 5 and quadcore chips in 7 However, GPUs were originally designed with special purpose for 3D graphics applications he hardware GPU architecture differs fro ulti-core CPUs significantly he latest Intel s ulti-core graphics chip, also known as Larrabee [15], is one of the boldest graphics projects in the world and offers full copatibility with graphics APIs as well as is capable to process the entire x instruction set that coes ipleented into odern processor architectures Currently, there are several ajor ulti-core prograing developent platfors RapidMind [1] s Multicore Developent Platfor supports ultiple processor architectures, including NVidia s GPUs, AI s GPUs, IBM s Cell BE, and Intel s and AMD s x CUDA (Copute Unified Device Architecture) [7, ] is a software platfor for assively parallel high-perforance coputing on the copany s powerful GPUs It does require prograers to exert soe anual effort and write soe explicit code OpenCL (Open Coputing Language) [13] is an open industry standard for general-purpose parallel prograing of heterogeneous systes However, all of the current ulti-core architectures need ulti-threading based parallel prograing In this paper, a copletely different way is proposed to design ulti-core CPU architectures without conventional parallel prograing D Crossbar-Based echnologies he crossbar switch [] has been used in any areas like telephone exchange As coputer technologies have iproved, crossbar switches have found uses in systes such as the ultistage interconnection networks that connect the various processing units in a Unifor Meory Access (UMA) parallel processor to the array of eory eleents Crossbar switches have been also designed to line entire coputer systes as well Crossbar-based eory architecture has been used on ainfrae coputers to increase eory bandwidth in PCC Vol Iss, 13 PP 9-57 wwwvkingpubco 13 Aerican V-King Scientific Publishing 5
3 Parallel & Cloud Coputing PCC Vol, Iss ulti-processor systes since decades he copanies such as Unisys, SGI, and Sun, have brought the technology down to the server and workstation platfors NVidia patented Light-speed Meory Architecture (LMA) [1] has eployed the use of a crossbar to axiize the efficiency of data transfer between the graphics processing unit and the graphics eory on the GPU A eory crossbar can eliinate bottlenecks associated with existing eory architecture as it replaces the conventional syste bus architecture Instead of sharing a bus, counication between the processor and the eory uses dedicated connections In this paper, a distinct dynaic eory/cache anageent technology using crossbar techniques is proposed for the new ulti-core architectures III A NEW PARALLEL ARCHIECURE A New Multi-Core Meory and Cache Architecture Based on Crossbar Switching he eory and cache anageent is very iportant for ulti-core systes A novel eory/cache anageent technology described in this section is one of core parts of this new architecture design It significantly iproves total perforance in both space and tie herefore, this part is introduced first Meory 1 Meory Meory n Cache 1 Cache Crossbar Switch *PSW : Progra Status W ords Cache n Controller 1 Controller Controller n Core1/PSW1 Core/PSW Coren/PSWn Fig 1 Crossbar switch based Multi-core eory and cache CPU architecture Since data blocks could be very large in the parallel applications, if DMA (Direct Meory Access) is used to ove big data blocks fro the eory in the previous processor to the next processor frequently at each tie, the accuulated overhead costs cannot be ignored o reduce the data relocation costs and bus liitations, the new architecture use a crossbar switch based dynaical anageent technique for both eories and caches to avoid relocating the data down the pipeline fro one processor to another processor he new eory and cache architecture for the technique is illustrated in Fig 1 Each processor/core does not have a fixed eory and cache as does an ordinary processor Instead, each of the will be assigned to connect to a given eory and cache at a given tie here is only one bus between such eory and cache Both of the can be regarded as a group he nuber of the groups is the sae as the nuber of cores Each core has its own controller, which is eployed to switch the entire eory and cache, ie one group, for the previous processor into the next processor he previous processor also passes the Progra Status Words (PSW) to the next processor to resue operations where the previous processor stopped Once the group of previous processors is igrated to the next processor, the current group of the previous processors needs to be cleared for use A crossbar switch is the key to carrying out this dynaic eory/cache anageent technology It oves two eory and cache groups between two processors at a given tie Correspondingly, the bus crossbar is used for connecting all the cores to all the groups to guarantee data transission between the at full speed and with no contention Although the crossbar used for this architecture is siilar to NVidia s LMA, they are different in principle he purpose of the crossbar in our architecture is ainly for eory and cache switch apart fro high-bandwidth data transission Furtherore, fro the view of cores, the N N connection relationship is for all cores and groups his architecture differs fro NVidia s LMA, in which one core has ultiple eory controllers connecting to their corresponding eory banks Actually, fro the view of cores, the 1 N connection relationship relates a given core to all its eory banks Additionally, the bus crossbar used in the new architecture can also reduce large bus traffic because each eory and cache group has a dedicated connection to one processor his not only reduces the bus traffic, but also eliinates the constraint that the data oveent has to be arranged at a particular tie as entioned before B New Multi-Core Pipeline Organization he new ulti-core pipeline architecture does not relocate the data down the pipeline as would be the case for the original ulti-core pipeline when a switch is applied Instead, it only switches the eory and cache group of the previous processor, where the data have been loaded and/or processed, into the group of the next processor hese data also contain the sall aount of the data of the operating state, such as Progra Status Word (PSW) and all registers with the progra counter, so that the next processor could resue operations where the previous processor stopped I N P U ie P1 P P3 Start S S S S S S G1 G1 G G3 G1 G G3 G1 G G1 G G3 G1 G G3 O U P U 1 1 G = Group (eory and cache) S = Switching (on/off for the connection between each processor and each group) P1 = Processor 1 P = Processor P3 = Processor 3 Fig New ulti-core pipeline organization PCC Vol Iss, 13 PP 9-57 wwwvkingpubco 13 Aerican V-King Scientific Publishing 51
4 Parallel & Cloud Coputing PCC Vol, Iss he new ulti-processor pipeline organization and data flow are depicted in Fig he ajor iproveent is to replace Unloading (U) with Switching (S) in the organization However, Loading (L), Processing (P), and Switching (S) do NO rotate in the coluns in the cycle: L P S L in a helicoidal pattern as does the above original pipeline Instead, the Switching (S) for all the processors occurs at the sae tie in the new ulti-processor pipeline Accordingly, Loading (L), Processing (P), and Switching (S) ay rotate in the coluns in the cycle: L P S, P P S, or P L S as shown in Fig 3 In Fig, the vertical orange dashed lines show the cycles Each sall rectangle represents one operation in one cycle All blocks and arrows with the sae colors describe the flows of the data chunks P1, P, and P3 describe the processors or cores In theory, there could be any nuber of processors, depending on the applications and user requireents Because the architecture does not specify a particular processor to perfor a particular operation, data-dependent branching of the algorith does not require special handling A processor working on a particular data chunk behaves just as a standard processor, resulting in variable-length processing ties for the data chunks If a chunk becoes fully processed before the end of the pipeline, the result can be withdrawn Data which require longer processing can be switched back to connect the first processor to continue processing his is totally different fro the original ultiprocessor pipeline [], which needs to send these data to soe sort of overflow processing facility, or accuulate the and send the back through the pipeline when the incoing data strea ceases his new ethod would be advantageous for highly variable data processing ties he next section also gives ore details to explain this using an exaple in Fig 3 P1 L L L P P S L L L P P S L L L P P S P P P P P P S P P P P P S P3 P P P P P S P1 L L L P P S P P P P P S P P P P P S P P P P P P S P P P P P S P P P P P S P3 P P P P P S P P L L L S P P P P P S L = Load (a new data chunk) P = Process S = Switch (on/off) C iing Diagra Fig 3 iing diagra of a 3-core pipeline Fig 3 shows the tiing diagra of an exaple of a 3- core pipeline It is assued that Switching (S) takes one cycle In fact, S ay take ore than one cycle or less than one cycle, which depend on hardware and software Because of the dynaic eory/cache anageent with the crossbar-based techniques, all the Switchings (S) occur at the sae tie hat is, all the processed data fro previous processors to next processors are switched at the sae tie In the Fig 3, each color block represents a data chunk being processed in different processors in different tie he sae color blocks indicate the data flow for one chunk A new data chunk can be loaded (L) by any one of the processors as long as the previous data chunk is finished processing In other word, any one of the processors can load the data as long as it is free he various lengths or processing tie of the data chunks can thus be autoatically scheduled onto the processors without considering any load balancing or scheduling issues In fact, one data chunk is always being processed within this eory and cache group although the core connected to this group is changed at every switching tie hat is to say, the data do not ove while the core or processor oves his is the ajor difference fro the original ultiprocessor pipeline, in which the data chunk has to be relocated when a switch is applied he new architecture is uch ore efficient in both space and tie he overall perforance can be iproved significantly his is totally different fro the ultiprocessor pipeline syste in [, 5], which allows only one data chunk relocation at a particular tie on one shared bus D Progra Requireents An iportant feature of this architecture is that it uses practically the sae software as a sequential coputer A progra for this syste can be developed on an ordinary sequential coputer Each processor is distributed with the sae application progra o run on the syste, the progra would just have to incorporate soe interrupts he interrupt is triggered by the crossbar switching A processor working on a particular piece of data, upon crossbar switching, will ove its eory to the next processor he processor will also pass the PSW so that the next processor could resue operations where the previous processor stopped he foration of the PSW in the syste is siilar to the routine procedure of foratting the PSW for interrupts in ordinary icroprocessors IV PERFORMANCE AND EXPERIMENAL ANALYSIS A Perforance Clearly, the tie coplexity of the algorith based on the new ulti-core pipelined architecture will only affect the total length of the pipeline including the overhead of the eory and cache group switches between processors after switching Let e analyse how this new ulti-core pipelined architecture iproves the overall perforance for parallel coputing he principle of the N-core pipeline is descried in Fig PCC Vol Iss, 13 PP 9-57 wwwvkingpubco 13 Aerican V-King Scientific Publishing 5
5 Speedup Parallel & Cloud Coputing PCC Vol, Iss Fig he principle of the N-core pipeline For the ulti-core pipeline syste as shown in Fig, to better explain the perforance, the pattern of the syste operations is assued to be discretized into cycles with each cycle, C In fact, it can be discretized into uch saller tie unit in odern architectures so that the architectures can be prograable Let us consider a progra to process a dataset containing data chunks with equal or various sizes Processing the entire dataset requires K cycles On a conventional processor, the execution t ie of a progra,, can be expressed by c KC (1) In Fig, let N be the nuber of processors/cores If the entire dataset can be processed on all N cores, on the average, the nuber of cycles on each processor/core, n, can be given by K n () N hus, the total tie spent on the conventional processor can also be described in cobination with above two c P1 P P3 equations as ie S S S S S (Cycles) n L p P1 = Processor 1 P = Processor P3 = Processor 3 S = Switching c nnc (3) For the N-core pipeline, let be the nuber of cycles for each interval of the equal duration in the pipeline hus, the length of the N-core pipeline for processing of data, L p, can be described by L p n ( N 1) () Let q be the nuber of the internals for the entire pipeline, it can be L p q (5) n ( N 1) Since switching by crossbar ay take soe extra tie, let d be the nuber of cycles of processing and delays or latencies for each switching based on hardware he total nuber of cycles of the overhead of the context switching in the N-core pipeline, can be expressed as H ( q 1) d n ( N ) d c () hus, in the N-core pipeline syste, the total length of the pipeline, noted by L, to process the sae size of the data including the overhead of content switching, can be described by L Lp H (7) n n ( N 1) ( N ) d he total tie spent on this ulti-core pipelined syste can be obtained by LC () Let s first calculate the speed-up of the execution tie on the new N-core pipeline syste copared to the tie on one conventional processor Cobined with Equation (1), Equation (3), Equation (7), and Equation (), the speed-up is given by Speedup B Siulation Analysis c nn n n ( N 1) ( N ) d We developed a tool to evaluate this new architecture In this section, soe experiental results are reported based on this architecture with various overheads taken into account In the first four experients as shown in Fig 5, Fig, Fig 7, and Fig, we assue the total execution of a given sequential progra takes K = 1, cycles and one-tie switching overhead d takes cycles he Perforance for Different Intervals Nuber of Cycles of the Interval Fig 5 he perforance for different Intervals Fig 5 shows the perforance increases with interval tie increasing for fixed nuber of cores, N (N=1), and switching tie, d, and reaches the axiu then decreases slowly his is because the pipeline will becoe longer if becoes bigger he perforance is affected by the length of the pipeline Fig shows the perforance increases with nuber of cores increasing for fixed interval tie, ( =), and switching tie, d, and reaches the axiu, then decreases slowly his is also because the pipeline ay increase (9) PCC Vol Iss, 13 PP 9-57 wwwvkingpubco 13 Aerican V-King Scientific Publishing 53
6 Nuber of Cycles of Interval Speedup & Interval ie (Cycle) Speedup Speedup Parallel & Cloud Coputing PCC Vol, Iss slowly while the nuber of cores becoes big hat is to say, for a given progra with fixed interval tie,, and switching tie, d, the perforance ay not reach the axiu for soe nubers of cores Put another way, if given an appropriate interval tie and switching tie, d, the perforance can reach the axiu speedup In practice, since d is usually fixed for such a ulti-core syste due to the crossbar switch, the axiu speedup can be obtained with an appropriate ties of nuber of cores, which is the axiu perforance for any ulti-core syste in theory 5 Perforance for Different Dataset Size with Different Nuber of Cores K = 1, K = 1, K = 1,, K = 1,, K = 1,, he Perforance for Different Nuber of Cores Nuber of Cores Fig he perforance for different nuber of cores Maxiu Perforance for Different Switching ie 1 Interval Cycle Nuber Maxiu Speedup 1 5 Nuber of Cores Fig he perforance for different dataset size with different nuber of cores Fig 9 shows the best interval tie, b, to reach the axiu perforance decreases and then becoe stable with the increase of the nuber of cores Furtherore, all the best interval tie, b, for different size of the application progras is close to each other when the nuber of cores increases his iplies that the ost appropriate interval tie,, can be chosen to axiize the perforance for all the application progras on a ulti-core syste with the certain aount of cores his is a trade-off for a ulti-core syste to ensure the best perforance for all the applications Maxiu Perforance for Different Interval and Nuber of Cores K = 1, K = 1, K = 1,, K = 1,, K = 1,, Nuber of Cycles of Switching ie 5 Fig 7 Maxiu perforance for different switching tie Fig 7 shows the axiu perforance for different switching tie, d In the figure, the blue line shows the interval tie,, and the red line shows the axiu perforance, ax_speedup For a given progra and fixed nuber of cores, N (N=1), with the increase of the switching tie, d, the best interval tie, b, to reach the axiu perforance, ax_speedup, increases when the switching tie, d, increases However, the ax_speedup decreases slowly accordingly his clearly indicates the pipeline length increases with the increase of both interval tie and overhead of content switching (ie and d) Accordingly, the perforance decreases Fig shows the perforance Speedup increases with increasing the nuber of cores and the size of the data Note that the Speedup is the axiu, ax_speedup, in this experient he figure clearly indicates when the application progra becoes larger, the Speedup increases linearly with the nuber of cores hat is, the Speedup is alost close to the nuber of cores for the large-size applications his indicates the perforance increases the Nuber of Cores Fig 9 Maxiu perforance for different intervals and nuber of cores In suary, with the increase of the nuber of cores, the perforance increases totally However, choosing the best interval tie, b, is the key to ake full use of all the cores to axiize the perforance for all the application progras Such a possible b can be found for all the application progras based on the analysis of Fig 9 In addition to selecting one fixed best interval tie, b, for the entire syste, the dynaical best interval tie, b, can also be autoatically assigned to each application progra according to the total application and data size, the nuber of cores, and the switching tie on a ulti-core syste while the progra is copiled C Experiental Results and Perforance Coparison 3 We developed a function siulator to evaluate this PCC Vol Iss, 13 PP 9-57 wwwvkingpubco 13 Aerican V-King Scientific Publishing 5
7 Speedup DM Generating ie (s) Parallel & Cloud Coputing PCC Vol, Iss ulti-core pipelined parallel syste and copare it with existing ulti-core systes he testing ulti-core progras are based on the algoriths of DEM generation fro LIDAR dataset designed and developed by e before (a) (b) Fig 1 1 stripes of the LIDAR data he tests were run on a Dell PC with Pentiu (R) D a single processor 3GHZ and GB RAM equipped with a GPU, NVidia GeForce GX featured with 19 CUDA cores he LIDAR dataset contains 1,5 points in (x, y, z, value) In order to test it on the ulti-core architectures, it is divided into 1 stripes along Y-direction as shown in Fig 1 (a) he DEM generation algorith is eployed for each LIDAR stripe he size of each DEM stripe is 53 by he experiental results are reported in the Figs 1-13 Fig 1 and Fig 13 show the experiental results on the single-processor syste using the algoriths to generate a DEM based on LIDAR data Fig 1 indicates the tie spent on the DEM generation for all LIDAR stripes fro 1 to 1 Obviously, the processing tie for each LIDAR stripe is different Fig 13 shows the coparison of the new ulti-core pipelined GPUs and existing ulti-core GPUs to generate the sae DEM fro the 1 LIDAR stripes with the size of 53x It obviously indicates the perforance of new ulti-core GPU architecture is better than existing ones his is because data partition and load balancing and scheduling need be considered for existing ulti-core GPU syste Moreover, these conventional parallel ethods cannot be done easily on current ulti-core systes he perforance ay be affected by different data partition or load balancing and scheduling ethods However, the new ulti-core syste can directly use original sequential progra for parallel coputing hus, it does not need to take into account the data distribution and load balancing and scheduling issues All of the data can be autoatically partitioned and scheduled onto the different cores through the pipeline Furtherore, with the increase of the nuber of cores, the perforance of the new architecture increases uch ore than the existing ones with the sae nuber of cores 9 ie Spent on Each LIDAR Stripe (a) Slice Nuber Fig 1 ie spent on each LIDAR stripe Coparison of the Multi-core Pipelined Architecture and Conventional Multi-core Archteture 1 Speedup of Multi-Core Pipelined Architecture Speedup of Conventional Multi-Core Architecture 1 1 (b) Fig 11 (a) LIDAR atches the generated DEM in 3D space; (b) Generated DEM rendering in color raps Fig 1 (b) shows the corresponding rendering effects of the cobined DEM with 1 pieces Fig 11 (a) shows the generated DEM atches the original LIDAR data very well in 3D space he 3D terrain based on the DEM is rendered in color raping as indicated in Fig 11 (b) 1 1 Nuber of Cores Fig 13 Coparison of the new ulti-core pipelined architecture and existing ulti-core architectures PCC Vol Iss, 13 PP 9-57 wwwvkingpubco 13 Aerican V-King Scientific Publishing 55
8 Parallel & Cloud Coputing PCC Vol, Iss V CONCLUSIONS AND FUURE WORK his paper presents a new ulti-core pipelined architecture based on core crossbar switching driven ultiprocessor pipelining and dynaic eory and cache anageent techniques he new architecture is very suitable for processing large data in parallel without parallel prograing in geospatial doain as well as other high perforance coputing areas he proposed architecture provides a siple and effect ive ipleentation for on-thefly parallel coputing by switching the entire data fro core to core through the crossbar switch his architecture akes full use of the pipeline It can autoatically partition data and schedule the onto ulti-cores through the pipeline It does not need conventional coplicated parallel coputing ethods, such as load balancing, scheduling, and data distribution his is exactly the advantage of this proposed architecture Obviously, the new ulti-core pipeline architecture significantly overcoes all these liitations of the original ultiprocessor pipeline as described in Section Especially, the core difference of these two ultiprocessor architectures is the new architecture relocates the cores instead of oving the data in the original one More specifically, the new pipeline advantages over the original pipeline liitations are suarized as follows: No data relocation Content switching is eployed to iniize big overhead costs due to data relocation while a switch is eployed No data overlapping Due to content switching, no processed data chunks across the segentation All the Switches (S) are forced by the crossbar switching control at a regular tie All the data are switched to their corresponding processors However, the original ultiproces sor pipeline only allows one data relocation at a particular tie due to one shared bus No special handling for the data required longer pipeline to process he new architecture does not need special handing for the data required longer pipeline to process But, the original ultiprocessor pipeline need overflow facility or accuulation and sending back while the data strea ceases Additionally, ore specific advantages for the new switch-based dynaic eory and cache-anageent technology in the new architecture are ephasized as follows: avoids oving the data fro one eory to another eory allows ore than one Switching operation at a tie; all the Switchings occur at the sae tie reduces bus liitations and large bus traffic using the bus crossbar iproves perforance in both space and tie Finally, to suarize, there are several overall advantages of this new ulti-core pipelined architecture as follows: provides the continuous data processing of intensive inforation flows requires essentially the sae software as ordinary sequential algorith avoids load balancing and scheduling avoids the need for synchronization aong the processors avoids busy waiting of processors on a spin-lock avoids the duplication for incoing data strea be suitable for highly variable data processing tie Another advantage worth entioning is that this core ultiprocessor/ulti-core pipelining technology provides an iportant solution to processing the continuous intensive inforation flows without liitation by size Consequently, this would be very helpful to real-tie assive data processing, especially geospatial coputing REFERENCES [1] AMD Corporation, White Paper: AMD Multi-core Processors AMD Corporation [] S Berkovich, Z Kitov, A Meltzer: On-the-fly processing of continuous data streas with a pipeline of icroprocessors In Proceedings of the International Conference on Databases, Parallel Architectures, and heir Applications (PARBASE- 9), IEEE Coputer Society, Maiai Beach, Florida, March 199, pp 5-97 [3] S Berkovich, M Loew, and M Zaghloul: On-Line Processing and Archiving of Continous Data Flows In IEEE Proceedings of 35th Midwest Syposiu on Circuits and Systes Washington DC, Aug 199, pp [] E Berkovich, S Berkovich, M Loew: A Multi-Layer Conveyor for Processing Intensive Inforation Flows he echnical Report, GWU-IIS-9-13, he George Washington University, 199 [5] S Berkovich, E Berkovich, and M Loew, Multi- Layer Multi-Processor Inforation Conveyor with Periodic ransferring of Processor s States for On-he-Fly ransforation of Continuous Inforation Flows and Operating Method herefor, US PAEN No 1571, owned by George Washington University Date issued - Noveber 7, [] Crossbar Switch on Wikipedia [7] NVidia NVIDIA CUDA Copute Unified Device Architecture Prograing Guide (Version 1 Beta), Oct [] NVidia NVIDIA CUDA Copute Unified Device Architecture Reference Manual (Version 1 Beta), Nov [9] D Culler, JP Singh, Anoop Gupta, Parallel Coputer Architecture: A Hardware/Software Approach, Morgan Kaufann, 199 ISBN [1] Ananth Graa, Anshul Gupta, George Karypis, Vipin Kuar, PCC Vol Iss, 13 PP 9-57 wwwvkingpubco 13 Aerican V-King Scientific Publishing 5
9 Parallel & Cloud Coputing PCC Vol, Iss An Introduction to Parallel Coputing, Design and Analysis of Algoriths: /e, Addison-Wesley, 3 ISBN [11] Intel Corporation, White Paper: Intel Multi-Core Processor Architecture Developent Backgrounder Intel Corporation [1] NVidia Corporation, echnical Brief: GeForce3: Lightspeed Meory Architecture Nvidia Corporation 1 [13] Aaftab Munshi, he OpenCL Specification (Version 1) Khronos OpenCL Working Group Dec [1] RapidMind Easily build applications for ulti-core [15] Seiler, L, Carean, D, Sprangle, E, Forsyth,, Abrash, M, Dubey, P, Junkins, S, Lake, A, Sugeran, J, Cavin, R, Espasa, R, Grochowski, E, Juan,, and Hanrahan, P Larrabee: a any-core x architecture for visual coputing In ACM SIGGRAPH Papers (Los Angeles, California, August 11-15, ) SIGGRAPH ' ACM, New York, NY, 1-15 [1] Stopel, A, Ma, K, Lu, EB, Ahrens, J, and Patchett, J 3 SLIC: Scheduled Linear Iage Copositing for Parallel Volue Rendering In Proceedings of the 3 IEEE Syposiu on Parallel and Large-Data Visualization and Graphics (October - 1, 3) Parallel and large-data visualization and graphics IEEE Coputer Society, Washington, DC, Sion Y Berkovich earned a MS in Applied Physics fro Moscow Physical-echnical Institute and a PhD in Coputer Science fro the Institute of Precision Mechanics and Coputer echnology of the USSR Acadey of Sciences He is a Professor of School of Engineering and Applied Science at George Washington University Prof Berkovich played a leading role in a nuber of research and developent projects on the design of advanced hardware and software systes hose projects include construction of superconductive associative eory, developent of large inforation systes for econoics, investigation of coputer counications for ultiprocessor systes, and enhanceent of inforation retrieval procedures Prof Berkovich has several hundred professional publications in various areas of physics, electronics, coputer science, and biological cybernetics He is an author of six books and holds 3 patents Aong his inventions is a ethod for dynaic file construction that later becoe known as B-tree and extendible hashing In, he was elected a eber of the European Acadey of Sciences for an outstanding contribution to coputer science and the developent of fundaental coputational algoriths Duoduo Liao earned a PhD and a MS in Coputer Science fro George Washington University and Purdue University in USA, respectively Since, she has worked for the federal governent agencies and universities on PC-clustered highway driving siulator systes, 3D graphics & visualization, virtual reality, GIS, traffic siulation, air traffic anageent, ulti-core architectures, heterogeneous coputing, etc She ever worked at ESRI and developed the first version of Stereo Viewer for ArcGIS in 1 In 199, she pioneered the product developent of the PC-based high-resolution quad-buffered 3D stereographic accelerators using the earliest PC graphics chips invented by 3D Labs Dr Liao has authorized ore than technical publications and two professional books on GPU-based research and OpenGL prograing She has been invited to give the talks by the federal governents, leading industries, and universities She was an adjunct professor at George Mason University She is a eber of ACM and IEEE, and serves the conference chairs, editorial boards, and coittees of several international conferences PCC Vol Iss, 13 PP 9-57 wwwvkingpubco 13 Aerican V-King Scientific Publishing 57
Analyzing Spatiotemporal Characteristics of Education Network Traffic with Flexible Multiscale Entropy
Vol. 9, No. 5 (2016), pp.303-312 http://dx.doi.org/10.14257/ijgdc.2016.9.5.26 Analyzing Spatioteporal Characteristics of Education Network Traffic with Flexible Multiscale Entropy Chen Yang, Renjie Zhou
More informationAn Innovate Dynamic Load Balancing Algorithm Based on Task
An Innovate Dynaic Load Balancing Algorith Based on Task Classification Hong-bin Wang,,a, Zhi-yi Fang, b, Guan-nan Qu,*,c, Xiao-dan Ren,d College of Coputer Science and Technology, Jilin University, Changchun
More informationModeling Parallel Applications Performance on Heterogeneous Systems
Modeling Parallel Applications Perforance on Heterogeneous Systes Jaeela Al-Jaroodi, Nader Mohaed, Hong Jiang and David Swanson Departent of Coputer Science and Engineering University of Nebraska Lincoln
More informationSoftware Quality Characteristics Tested For Mobile Application Development
Thesis no: MGSE-2015-02 Software Quality Characteristics Tested For Mobile Application Developent Literature Review and Epirical Survey WALEED ANWAR Faculty of Coputing Blekinge Institute of Technology
More informationExtended-Horizon Analysis of Pressure Sensitivities for Leak Detection in Water Distribution Networks: Application to the Barcelona Network
2013 European Control Conference (ECC) July 17-19, 2013, Zürich, Switzerland. Extended-Horizon Analysis of Pressure Sensitivities for Leak Detection in Water Distribution Networks: Application to the Barcelona
More informationExploiting Hardware Heterogeneity within the Same Instance Type of Amazon EC2
Exploiting Hardware Heterogeneity within the Sae Instance Type of Aazon EC2 Zhonghong Ou, Hao Zhuang, Jukka K. Nurinen, Antti Ylä-Jääski, Pan Hui Aalto University, Finland; Deutsch Teleko Laboratories,
More informationApproximately-Perfect Hashing: Improving Network Throughput through Efficient Off-chip Routing Table Lookup
Approxiately-Perfect ing: Iproving Network Throughput through Efficient Off-chip Routing Table Lookup Zhuo Huang, Jih-Kwon Peir, Shigang Chen Departent of Coputer & Inforation Science & Engineering, University
More informationApplying Multiple Neural Networks on Large Scale Data
0 International Conference on Inforation and Electronics Engineering IPCSIT vol6 (0) (0) IACSIT Press, Singapore Applying Multiple Neural Networks on Large Scale Data Kritsanatt Boonkiatpong and Sukree
More informationThe Benefit of SMT in the Multi-Core Era: Flexibility towards Degrees of Thread-Level Parallelism
The enefit of SMT in the Multi-Core Era: Flexibility towards Degrees of Thread-Level Parallelis Stijn Eyeran Lieven Eeckhout Ghent University, elgiu Stijn.Eyeran@elis.UGent.be, Lieven.Eeckhout@elis.UGent.be
More informationCPU Animation. Introduction. CPU skinning. CPUSkin Scalar:
CPU Aniation Introduction The iportance of real-tie character aniation has greatly increased in odern gaes. Aniating eshes ia 'skinning' can be perfored on both a general purpose CPU and a ore specialized
More informationDynamic Placement for Clustered Web Applications
Dynaic laceent for Clustered Web Applications A. Karve, T. Kibrel, G. acifici, M. Spreitzer, M. Steinder, M. Sviridenko, and A. Tantawi IBM T.J. Watson Research Center {karve,kibrel,giovanni,spreitz,steinder,sviri,tantawi}@us.ib.co
More informationA framework for performance monitoring, load balancing, adaptive timeouts and quality of service in digital libraries
Int J Digit Libr (2000) 3: 9 35 INTERNATIONAL JOURNAL ON Digital Libraries Springer-Verlag 2000 A fraework for perforance onitoring, load balancing, adaptive tieouts and quality of service in digital libraries
More informationManaging Complex Network Operation with Predictive Analytics
Managing Coplex Network Operation with Predictive Analytics Zhenyu Huang, Pak Chung Wong, Patrick Mackey, Yousu Chen, Jian Ma, Kevin Schneider, and Frank L. Greitzer Pacific Northwest National Laboratory
More informationAn Improved Decision-making Model of Human Resource Outsourcing Based on Internet Collaboration
International Journal of Hybrid Inforation Technology, pp. 339-350 http://dx.doi.org/10.14257/hit.2016.9.4.28 An Iproved Decision-aking Model of Huan Resource Outsourcing Based on Internet Collaboration
More informationImplementation of Active Queue Management in a Combined Input and Output Queued Switch
pleentation of Active Queue Manageent in a obined nput and Output Queued Switch Bartek Wydrowski and Moshe Zukeran AR Special Research entre for Ultra-Broadband nforation Networks, EEE Departent, The University
More informationHigh Performance Chinese/English Mixed OCR with Character Level Language Identification
2009 0th International Conference on Docuent Analysis and Recognition High Perforance Chinese/English Mixed OCR with Character Level Language Identification Kai Wang Institute of Machine Intelligence,
More informationPERFORMANCE METRICS FOR THE IT SERVICES PORTFOLIO
Bulletin of the Transilvania University of Braşov Series I: Engineering Sciences Vol. 4 (53) No. - 0 PERFORMANCE METRICS FOR THE IT SERVICES PORTFOLIO V. CAZACU I. SZÉKELY F. SANDU 3 T. BĂLAN Abstract:
More informationThe Research of Measuring Approach and Energy Efficiency for Hadoop Periodic Jobs
Send Orders for Reprints to reprints@benthascience.ae 206 The Open Fuels & Energy Science Journal, 2015, 8, 206-210 Open Access The Research of Measuring Approach and Energy Efficiency for Hadoop Periodic
More informationASIC Design Project Management Supported by Multi Agent Simulation
ASIC Design Project Manageent Supported by Multi Agent Siulation Jana Blaschke, Christian Sebeke, Wolfgang Rosenstiel Abstract The coplexity of Application Specific Integrated Circuits (ASICs) is continuously
More informationEvaluating Inventory Management Performance: a Preliminary Desk-Simulation Study Based on IOC Model
Evaluating Inventory Manageent Perforance: a Preliinary Desk-Siulation Study Based on IOC Model Flora Bernardel, Roberto Panizzolo, and Davide Martinazzo Abstract The focus of this study is on preliinary
More informationREQUIREMENTS FOR A COMPUTER SCIENCE CURRICULUM EMPHASIZING INFORMATION TECHNOLOGY SUBJECT AREA: CURRICULUM ISSUES
REQUIREMENTS FOR A COMPUTER SCIENCE CURRICULUM EMPHASIZING INFORMATION TECHNOLOGY SUBJECT AREA: CURRICULUM ISSUES Charles Reynolds Christopher Fox reynolds @cs.ju.edu fox@cs.ju.edu Departent of Coputer
More informationFuzzy Sets in HR Management
Acta Polytechnica Hungarica Vol. 8, No. 3, 2011 Fuzzy Sets in HR Manageent Blanka Zeková AXIOM SW, s.r.o., 760 01 Zlín, Czech Republic blanka.zekova@sezna.cz Jana Talašová Faculty of Science, Palacký Univerzity,
More informationReal Time Target Tracking with Binary Sensor Networks and Parallel Computing
Real Tie Target Tracking with Binary Sensor Networks and Parallel Coputing Hong Lin, John Rushing, Sara J. Graves, Steve Tanner, and Evans Criswell Abstract A parallel real tie data fusion and target tracking
More informationRECURSIVE DYNAMIC PROGRAMMING: HEURISTIC RULES, BOUNDING AND STATE SPACE REDUCTION. Henrik Kure
RECURSIVE DYNAMIC PROGRAMMING: HEURISTIC RULES, BOUNDING AND STATE SPACE REDUCTION Henrik Kure Dina, Danish Inforatics Network In the Agricultural Sciences Royal Veterinary and Agricultural University
More informationUse of extrapolation to forecast the working capital in the mechanical engineering companies
ECONTECHMOD. AN INTERNATIONAL QUARTERLY JOURNAL 2014. Vol. 1. No. 1. 23 28 Use of extrapolation to forecast the working capital in the echanical engineering copanies A. Cherep, Y. Shvets Departent of finance
More informationRed Hat Enterprise Linux: Creating a Scalable Open Source Storage Infrastructure
Red Hat Enterprise Linux: Creating a Scalable Open Source Storage Infrastructure By Alan Radding and Nick Carr Abstract This paper discusses the issues related to storage design and anageent when an IT
More informationSearching strategy for multi-target discovery in wireless networks
Searching strategy for ulti-target discovery in wireless networks Zhao Cheng, Wendi B. Heinzelan Departent of Electrical and Coputer Engineering University of Rochester Rochester, NY 467 (585) 75-{878,
More informationDesign of Model Reference Self Tuning Mechanism for PID like Fuzzy Controller
Research Article International Journal of Current Engineering and Technology EISSN 77 46, PISSN 347 56 4 INPRESSCO, All Rights Reserved Available at http://inpressco.co/category/ijcet Design of Model Reference
More informationConstruction Economics & Finance. Module 3 Lecture-1
Depreciation:- Construction Econoics & Finance Module 3 Lecture- It represents the reduction in arket value of an asset due to age, wear and tear and obsolescence. The physical deterioration of the asset
More informationImpact of Processing Costs on Service Chain Placement in Network Functions Virtualization
Ipact of Processing Costs on Service Chain Placeent in Network Functions Virtualization Marco Savi, Massio Tornatore, Giacoo Verticale Dipartiento di Elettronica, Inforazione e Bioingegneria, Politecnico
More informationAn online sulfur monitoring system can improve process balance sheets
Originally appeared in: February 2007, pgs 109-116. Used with perission. An online sulfur onitoring syste can iprove process balance sheets A Canadian gas processor used this technology to eet environental
More informationEfficient Key Management for Secure Group Communications with Bursty Behavior
Efficient Key Manageent for Secure Group Counications with Bursty Behavior Xukai Zou, Byrav Raaurthy Departent of Coputer Science and Engineering University of Nebraska-Lincoln Lincoln, NE68588, USA Eail:
More informationEnergy Efficient VM Scheduling for Cloud Data Centers: Exact allocation and migration algorithms
Energy Efficient VM Scheduling for Cloud Data Centers: Exact allocation and igration algoriths Chaia Ghribi, Makhlouf Hadji and Djaal Zeghlache Institut Mines-Téléco, Téléco SudParis UMR CNRS 5157 9, Rue
More informationINTEGRATED ENVIRONMENT FOR STORING AND HANDLING INFORMATION IN TASKS OF INDUCTIVE MODELLING FOR BUSINESS INTELLIGENCE SYSTEMS
Artificial Intelligence Methods and Techniques for Business and Engineering Applications 210 INTEGRATED ENVIRONMENT FOR STORING AND HANDLING INFORMATION IN TASKS OF INDUCTIVE MODELLING FOR BUSINESS INTELLIGENCE
More informationAn Optimal Task Allocation Model for System Cost Analysis in Heterogeneous Distributed Computing Systems: A Heuristic Approach
An Optial Tas Allocation Model for Syste Cost Analysis in Heterogeneous Distributed Coputing Systes: A Heuristic Approach P. K. Yadav Central Building Research Institute, Rooree- 247667, Uttarahand (INDIA)
More informationCooperative Caching for Adaptive Bit Rate Streaming in Content Delivery Networks
Cooperative Caching for Adaptive Bit Rate Streaing in Content Delivery Networs Phuong Luu Vo Departent of Coputer Science and Engineering, International University - VNUHCM, Vietna vtlphuong@hciu.edu.vn
More informationPreference-based Search and Multi-criteria Optimization
Fro: AAAI-02 Proceedings. Copyright 2002, AAAI (www.aaai.org). All rights reserved. Preference-based Search and Multi-criteria Optiization Ulrich Junker ILOG 1681, route des Dolines F-06560 Valbonne ujunker@ilog.fr
More informationInternational Journal of Management & Information Systems First Quarter 2012 Volume 16, Number 1
International Journal of Manageent & Inforation Systes First Quarter 2012 Volue 16, Nuber 1 Proposal And Effectiveness Of A Highly Copelling Direct Mail Method - Establishent And Deployent Of PMOS-DM Hisatoshi
More informationThis paper studies a rental firm that offers reusable products to price- and quality-of-service sensitive
MANUFACTURING & SERVICE OPERATIONS MANAGEMENT Vol., No. 3, Suer 28, pp. 429 447 issn 523-464 eissn 526-5498 8 3 429 infors doi.287/so.7.8 28 INFORMS INFORMS holds copyright to this article and distributed
More informationResource Allocation in Wireless Networks with Multiple Relays
Resource Allocation in Wireless Networks with Multiple Relays Kağan Bakanoğlu, Stefano Toasin, Elza Erkip Departent of Electrical and Coputer Engineering, Polytechnic Institute of NYU, Brooklyn, NY, 0
More informationMethod of supply chain optimization in E-commerce
MPRA Munich Personal RePEc Archive Method of supply chain optiization in E-coerce Petr Suchánek and Robert Bucki Silesian University - School of Business Adinistration, The College of Inforatics and Manageent
More informationResearch Article Performance Evaluation of Human Resource Outsourcing in Food Processing Enterprises
Advance Journal of Food Science and Technology 9(2): 964-969, 205 ISSN: 2042-4868; e-issn: 2042-4876 205 Maxwell Scientific Publication Corp. Subitted: August 0, 205 Accepted: Septeber 3, 205 Published:
More informationA Scalable Application Placement Controller for Enterprise Data Centers
W WWW 7 / Track: Perforance and Scalability A Scalable Application Placeent Controller for Enterprise Data Centers Chunqiang Tang, Malgorzata Steinder, Michael Spreitzer, and Giovanni Pacifici IBM T.J.
More informationOption B: Credit Card Processing
Attachent B Option B: Credit Card Processing Request for Proposal Nuber 4404 Z1 Bidders are required coplete all fors provided in this attachent if bidding on Option B: Credit Card Processing. Note: If
More informationUS 20100077068A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2010/0077068 A1 Saha et al. (43) Pub. Date: Mar.
US 20100077068A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2010/0077068 A1 Saha et al. (43) Pub. Date: Mar. 25, 2010 (54) PROCESSING OF SERVICE-ORIENTED Publication Classi?cation
More informationMarkov Models and Their Use for Calculations of Important Traffic Parameters of Contact Center
Markov Models and Their Use for Calculations of Iportant Traffic Paraeters of Contact Center ERIK CHROMY, JAN DIEZKA, MATEJ KAVACKY Institute of Telecounications Slovak University of Technology Bratislava
More informationAn Integrated Approach for Monitoring Service Level Parameters of Software-Defined Networking
International Journal of Future Generation Counication and Networking Vol. 8, No. 6 (15), pp. 197-4 http://d.doi.org/1.1457/ijfgcn.15.8.6.19 An Integrated Approach for Monitoring Service Level Paraeters
More informationA Study on the Chain Restaurants Dynamic Negotiation Games of the Optimization of Joint Procurement of Food Materials
International Journal of Coputer Science & Inforation Technology (IJCSIT) Vol 6, No 1, February 2014 A Study on the Chain estaurants Dynaic Negotiation aes of the Optiization of Joint Procureent of Food
More informationProtecting Small Keys in Authentication Protocols for Wireless Sensor Networks
Protecting Sall Keys in Authentication Protocols for Wireless Sensor Networks Kalvinder Singh Australia Developent Laboratory, IBM and School of Inforation and Counication Technology, Griffith University
More informationSAMPLING METHODS LEARNING OBJECTIVES
6 SAMPLING METHODS 6 Using Statistics 6-6 2 Nonprobability Sapling and Bias 6-6 Stratified Rando Sapling 6-2 6 4 Cluster Sapling 6-4 6 5 Systeatic Sapling 6-9 6 6 Nonresponse 6-2 6 7 Suary and Review of
More informationCreating Opportunity:
THE APPALACHIAN SAVINGS PROJECT Creating Opportunity: The Ipact of Matched Savings for Childcare Workers WISER WOMEN S INSTITUTE FOR A SECURE RETIREMENT Anita, a childcare worker and participant in the
More informationThe Application of Bandwidth Optimization Technique in SLA Negotiation Process
The Application of Bandwidth Optiization Technique in SLA egotiation Process Srecko Krile University of Dubrovnik Departent of Electrical Engineering and Coputing Cira Carica 4, 20000 Dubrovnik, Croatia
More informationAdaptive Modulation and Coding for Unmanned Aerial Vehicle (UAV) Radio Channel
Recent Advances in Counications Adaptive odulation and Coding for Unanned Aerial Vehicle (UAV) Radio Channel Airhossein Fereidountabar,Gian Carlo Cardarilli, Rocco Fazzolari,Luca Di Nunzio Abstract In
More informationOnline Bagging and Boosting
Abstract Bagging and boosting are two of the ost well-known enseble learning ethods due to their theoretical perforance guarantees and strong experiental results. However, these algoriths have been used
More informationThe AGA Evaluating Model of Customer Loyalty Based on E-commerce Environment
6 JOURNAL OF SOFTWARE, VOL. 4, NO. 3, MAY 009 The AGA Evaluating Model of Custoer Loyalty Based on E-coerce Environent Shaoei Yang Econoics and Manageent Departent, North China Electric Power University,
More informationMedia Adaptation Framework in Biofeedback System for Stroke Patient Rehabilitation
Media Adaptation Fraework in Biofeedback Syste for Stroke Patient Rehabilitation Yinpeng Chen, Weiwei Xu, Hari Sundara, Thanassis Rikakis, Sheng-Min Liu Arts, Media and Engineering Progra Arizona State
More informationReliability Constrained Packet-sizing for Linear Multi-hop Wireless Networks
Reliability Constrained acket-sizing for inear Multi-hop Wireless Networks Ning Wen, and Randall A. Berry Departent of Electrical Engineering and Coputer Science Northwestern University, Evanston, Illinois
More informationCRM FACTORS ASSESSMENT USING ANALYTIC HIERARCHY PROCESS
641 CRM FACTORS ASSESSMENT USING ANALYTIC HIERARCHY PROCESS Marketa Zajarosova 1* *Ph.D. VSB - Technical University of Ostrava, THE CZECH REPUBLIC arketa.zajarosova@vsb.cz Abstract Custoer relationship
More informationMachine Learning Applications in Grid Computing
Machine Learning Applications in Grid Coputing George Cybenko, Guofei Jiang and Daniel Bilar Thayer School of Engineering Dartouth College Hanover, NH 03755, USA gvc@dartouth.edu, guofei.jiang@dartouth.edu
More informationAn Approach to Combating Free-riding in Peer-to-Peer Networks
An Approach to Cobating Free-riding in Peer-to-Peer Networks Victor Ponce, Jie Wu, and Xiuqi Li Departent of Coputer Science and Engineering Florida Atlantic University Boca Raton, FL 33431 April 7, 2008
More informationGenerating Certification Authority Authenticated Public Keys in Ad Hoc Networks
SECURITY AND COMMUNICATION NETWORKS Published online in Wiley InterScience (www.interscience.wiley.co). Generating Certification Authority Authenticated Public Keys in Ad Hoc Networks G. Kounga 1, C. J.
More informationON SELF-ROUTING IN CLOS CONNECTION NETWORKS. BARRY G. DOUGLASS Electrical Engineering Department Texas A&M University College Station, TX 77843-3128
ON SELF-ROUTING IN CLOS CONNECTION NETWORKS BARRY G. DOUGLASS Electrical Engineering Departent Texas A&M University College Station, TX 778-8 A. YAVUZ ORUÇ Electrical Engineering Departent and Institute
More informationHow To Balance Over Redundant Wireless Sensor Networks Based On Diffluent
Load balancing over redundant wireless sensor networks based on diffluent Abstract Xikui Gao Yan ai Yun Ju School of Control and Coputer Engineering North China Electric ower University 02206 China Received
More informationPartitioned Elias-Fano Indexes
Partitioned Elias-ano Indexes Giuseppe Ottaviano ISTI-CNR, Pisa giuseppe.ottaviano@isti.cnr.it Rossano Venturini Dept. of Coputer Science, University of Pisa rossano@di.unipi.it ABSTRACT The Elias-ano
More informationLoad Control for Overloaded MPLS/DiffServ Networks during SLA Negotiation
Int J Counications, Network and Syste Sciences, 29, 5, 422-432 doi:14236/ijcns292547 Published Online August 29 (http://wwwscirporg/journal/ijcns/) Load Control for Overloaded MPLS/DiffServ Networks during
More informationThe individual neurons are complicated. They have a myriad of parts, subsystems and control mechanisms. They convey information via a host of
CHAPTER 4 ARTIFICIAL NEURAL NETWORKS 4. INTRODUCTION Artificial Neural Networks (ANNs) are relatively crude electronic odels based on the neural structure of the brain. The brain learns fro experience.
More informationLocal Area Network Management
Technology Guidelines for School Coputer-based Technologies Local Area Network Manageent Local Area Network Manageent Introduction This docuent discusses the tasks associated with anageent of Local Area
More informationPresentation Safety Legislation and Standards
levels in different discrete levels corresponding for each one to a probability of dangerous failure per hour: > > The table below gives the relationship between the perforance level (PL) and the Safety
More informationAn Application Research on the Workflow-based Large-scale Hospital Information System Integration
106 JOURNAL OF COMPUTERS, VOL. 6, NO. 1, JANUARY 2011 An Application Research on the Workflow-based Large-scale Hospital Inforation Syste Integration Yang Guojun School of Coputer, Neijiang Noral University,
More informationADJUSTING FOR QUALITY CHANGE
ADJUSTING FOR QUALITY CHANGE 7 Introduction 7.1 The easureent of changes in the level of consuer prices is coplicated by the appearance and disappearance of new and old goods and services, as well as changes
More informationSUPPORTING YOUR HIPAA COMPLIANCE EFFORTS
WHITE PAPER SUPPORTING YOUR HIPAA COMPLIANCE EFFORTS Quanti Solutions. Advancing HIM through Innovation HEALTHCARE SUPPORTING YOUR HIPAA COMPLIANCE EFFORTS Quanti Solutions. Advancing HIM through Innovation
More informationStudy on the development of statistical data on the European security technological and industrial base
Study on the developent of statistical data on the European security technological and industrial base Security Sector Survey Analysis: France Client: European Coission DG Migration and Hoe Affairs Brussels,
More informationEntity Search Engine: Towards Agile Best-Effort Information Integration over the Web
Entity Search Engine: Towards Agile Best-Effort Inforation Integration over the Web Tao Cheng, Kevin Chen-Chuan Chang University of Illinois at Urbana-Chapaign {tcheng3, kcchang}@cs.uiuc.edu. INTRODUCTION
More informationOptimal Resource-Constraint Project Scheduling with Overlapping Modes
Optial Resource-Constraint Proect Scheduling with Overlapping Modes François Berthaut Lucas Grèze Robert Pellerin Nathalie Perrier Adnène Hai February 20 CIRRELT-20-09 Bureaux de Montréal : Bureaux de
More information- 265 - Part C. Property and Casualty Insurance Companies
Part C. Property and Casualty Insurance Copanies This Part discusses proposals to curtail favorable tax rules for property and casualty ("P&C") insurance copanies. The syste of reserves for unpaid losses
More informationCLOSED-LOOP SUPPLY CHAIN NETWORK OPTIMIZATION FOR HONG KONG CARTRIDGE RECYCLING INDUSTRY
CLOSED-LOOP SUPPLY CHAIN NETWORK OPTIMIZATION FOR HONG KONG CARTRIDGE RECYCLING INDUSTRY Y. T. Chen Departent of Industrial and Systes Engineering Hong Kong Polytechnic University, Hong Kong yongtong.chen@connect.polyu.hk
More informationFuzzy Evaluation on Network Security Based on the New Algorithm of Membership Degree Transformation M(1,2,3)
324 JOURNAL OF NETWORKS, VOL. 4, NO. 5, JULY 29 Fuzzy Evaluation on Networ Security Based on the New Algorith of Mebership Degree Transforation M(,2,3) Hua Jiang School of Econoics and Manageent, Hebei
More informationModeling Cooperative Gene Regulation Using Fast Orthogonal Search
8 The Open Bioinforatics Journal, 28, 2, 8-89 Open Access odeling Cooperative Gene Regulation Using Fast Orthogonal Search Ian inz* and ichael J. Korenberg* Departent of Electrical and Coputer Engineering,
More informationStandards and Protocols for the Collection and Dissemination of Graduating Student Initial Career Outcomes Information For Undergraduates
National Association of Colleges and Eployers Standards and Protocols for the Collection and Disseination of Graduating Student Initial Career Outcoes Inforation For Undergraduates Developed by the NACE
More informationPREDICTION OF POSSIBLE CONGESTIONS IN SLA CREATION PROCESS
PREDICTIO OF POSSIBLE COGESTIOS I SLA CREATIO PROCESS Srećko Krile University of Dubrovnik Departent of Electrical Engineering and Coputing Cira Carica 4, 20000 Dubrovnik, Croatia Tel +385 20 445-739,
More informationDon t Run With Your Retirement Money
Don t Run With Your Retireent Money Understanding Your Resources and How Best to Use The A joint project of The Actuarial Foundation and WISER, the Woen s Institute for a Secure Retireent WISER THE WOMEN
More informationA quantum secret ballot. Abstract
A quantu secret ballot Shahar Dolev and Itaar Pitowsky The Edelstein Center, Levi Building, The Hebrerw University, Givat Ra, Jerusale, Israel Boaz Tair arxiv:quant-ph/060087v 8 Mar 006 Departent of Philosophy
More informationEnergy Proportionality for Disk Storage Using Replication
Energy Proportionality for Disk Storage Using Replication Jinoh Ki and Doron Rote Lawrence Berkeley National Laboratory University of California, Berkeley, CA 94720 {jinohki,d rote}@lbl.gov Abstract Energy
More informationMarkovian inventory policy with application to the paper industry
Coputers and Cheical Engineering 26 (2002) 1399 1413 www.elsevier.co/locate/copcheeng Markovian inventory policy with application to the paper industry K. Karen Yin a, *, Hu Liu a,1, Neil E. Johnson b,2
More informationStoring and Accessing Live Mashup Content in the Cloud
Storing and Accessing Live Mashup Content in the Cloud Krzysztof Ostrowski Cornell University Ithaca, NY 14853, USA krzys@cs.cornell.edu Ken Biran Cornell University Ithaca, NY 14853, USA ken@cs.cornell.edu
More informationIEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS, ACCEPTED FOR PUBLICATION 1. Secure Wireless Multicast for Delay-Sensitive Data via Network Coding
IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS, ACCEPTED FOR PUBLICATION 1 Secure Wireless Multicast for Delay-Sensitive Data via Network Coding Tuan T. Tran, Meber, IEEE, Hongxiang Li, Senior Meber, IEEE,
More informationStudy on the development of statistical data on the European security technological and industrial base
Study on the developent of statistical data on the European security technological and industrial base Security Sector Survey Analysis: Poland Client: European Coission DG Migration and Hoe Affairs Brussels,
More informationImage restoration for a rectangular poor-pixels detector
Iage restoration for a rectangular poor-pixels detector Pengcheng Wen 1, Xiangjun Wang 1, Hong Wei 2 1 State Key Laboratory of Precision Measuring Technology and Instruents, Tianjin University, China 2
More informationSensors as a Service Oriented Architecture: Middleware for Sensor Networks
Sensors as a Service Oriented Architecture: Middleware for Sensor Networks John Ibbotson, Christopher Gibson, Joel Wright, Peter Waggett, IBM U.K Ltd, Petros Zerfos, IBM Research, Boleslaw K. Szyanski,
More informationQuality evaluation of the model-based forecasts of implied volatility index
Quality evaluation of the odel-based forecasts of iplied volatility index Katarzyna Łęczycka 1 Abstract Influence of volatility on financial arket forecasts is very high. It appears as a specific factor
More informationEquivalent Tapped Delay Line Channel Responses with Reduced Taps
Equivalent Tapped Delay Line Channel Responses with Reduced Taps Shweta Sagari, Wade Trappe, Larry Greenstein {shsagari, trappe, ljg}@winlab.rutgers.edu WINLAB, Rutgers University, North Brunswick, NJ
More informationIntroduction to Unit Conversion: the SI
The Matheatics 11 Copetency Test Introduction to Unit Conversion: the SI In this the next docuent in this series is presented illustrated an effective reliable approach to carryin out unit conversions
More informationA Soft Real-time Scheduling Server on the Windows NT
A Soft Real-tie Scheduling Server on the Windows NT Chih-han Lin, Hao-hua Chu, Klara Nahrstedt Departent of Coputer Science University of Illinois at Urbana Chapaign clin2, h-chu3, klara@cs.uiuc.edu Abstract
More informationIdentification and Analysis of hard disk drive in digital forensic
Identification and Analysis of hard disk drive in digital forensic Kailash Kuar Dr. Sanjeev Sofat Dr. Naveen Aggarwal Phd(CSE) Student Prof. and Head CSE Deptt. Asst. Prof. CSE Deptt. PEC University of
More informationUsing Bloom Filters to Refine Web Search Results
Using Bloo Filters to Refine Web Search Results Navendu Jain Departent of Coputer Sciences University of Texas at Austin Austin, TX, 78712 nav@cs.utexas.edu Mike Dahlin Departent of Coputer Sciences University
More informationPhysics 211: Lab Oscillations. Simple Harmonic Motion.
Physics 11: Lab Oscillations. Siple Haronic Motion. Reading Assignent: Chapter 15 Introduction: As we learned in class, physical systes will undergo an oscillatory otion, when displaced fro a stable equilibriu.
More informationHow To Get A Loan From A Bank For Free
Finance 111 Finance We have to work with oney every day. While balancing your checkbook or calculating your onthly expenditures on espresso requires only arithetic, when we start saving, planning for retireent,
More informationA Fast Algorithm for Online Placement and Reorganization of Replicated Data
A Fast Algorith for Online Placeent and Reorganization of Replicated Data R. J. Honicky Storage Systes Research Center University of California, Santa Cruz Ethan L. Miller Storage Systes Research Center
More informationReconnect 04 Solving Integer Programs with Branch and Bound (and Branch and Cut)
Sandia is a ultiprogra laboratory operated by Sandia Corporation, a Lockheed Martin Copany, Reconnect 04 Solving Integer Progras with Branch and Bound (and Branch and Cut) Cynthia Phillips (Sandia National
More information6. Time (or Space) Series Analysis
ATM 55 otes: Tie Series Analysis - Section 6a Page 8 6. Tie (or Space) Series Analysis In this chapter we will consider soe coon aspects of tie series analysis including autocorrelation, statistical prediction,
More information