8-bit MCU HR7P201. Datasheet. SHANGHAI EASTSOFT MICROELECTRONICS Co., LTD

Transcription

1 8-bit MCU HR7P201 Datasheet Brief Datasheet Specifications SHANGHAI EASTSOFT MICROELECTRONICS Co., LTD V1.0 1/138

2 Application Notes Power On/Off Sequence Eastsoft MCUs are designed with separate power pins. If a MCU is applied in a system which has multiple power supplies, the MCU should be powered on first or at the same time together with other devices involved in the system. Conversely, the MCU should be powered off after all other devices are powered off. Reversed steps may cause excessive voltage or current on the MCU internal components, which is very likely to cause malfunction and weaken components performances. For details, please refer to the datasheet. Reset Eastsoft MCUs provide an internal power-on reset circuit, which could possibly be invalid in different fast/slow power on/off systems. To ensure a proper reset function, the following resets are recommended: external reset, brown-out reset, watchdog reset, etc. The triode reset or the RC reset is recommended when the external reset circuit is used; otherwise, it is suggested to connect the reset pin to power supply with a resistor or to use other protection circuits if necessary. For details, please refer to the datasheet. Clock Eastsoft MCUs offer internal and external clock sources. The internal clock frequency may experience a variation due to unstable temperature or voltage, which may affect the accuracy of the clock source. When a ceramic or crystal oscillator circuit is used as an external clock source, it is suggested to enable the oscillator start-up timer. When a RC oscillator circuit is used, it is suggested to take account of the capacitor matching and resistor matching. When an external active oscillator or external clock input is used, consider to input a high-voltage or low-voltage. For details, please refer to the datasheet Initialization For different application systems, it is necessary to initialize registers, memories and function modules, especially the multiplexed I/O pins, in order to avoid the unknown status of I/O pins when MCU is powered on. Pins Eastsoft MCUs are designed with wide-range input voltage. It is suggested that the input high-level voltage should be higher than V IHMIN, the input low-level voltage should be lower than V ILMAX. To avoid the noise entering into MCU, the input voltage should not be set between V IHMIN and V ILMAX. The unused I/O pins are suggested to be set to input mode, and should be connected to VDD via pull-up resistors or to GND via pull-down resistors. Alternatively, set unused pins to output mode with fixed voltage and leave them floating. How to handle unused pins varies from application to application and it is important to follow the specific application specification and instructions. ESD Protection Eastsoft MCUs have industrial ESD standard protection circuit. It is suggested to take proper protection measures depending on application/storage environment to prevent MCUs from static electricity. Special attention should be paid to the humidity of application environment. Do not use the insulators which could cause static electricity. Use anti-static-electricity container/shields or conductive materials to store and transport the MCUs. Ground all the testing tools, measuring tools, including the workbench. Use anti-static-electricity belts or gloves, and do not touch the MCU with fingers directly. EFT Protection Eastsoft MCUs have industrial EFT standard protection circuit.. When MCUs are used in PCB systems, the related design requests should be satisfied, including wiring of VDD or GND (i.e. separation of digital/analog power supply, single-point/multi-point grounding and so on), protection circuits for reset pins, decoupling capacitors between VDD and GND, separate processing of high/low frequency circuits, selection of single-layer/multi-layer board and V1.0 2/138

3 so on. Development Environment Eastsoft MCUs have a complete software/hardware development environment with protected intellectual property. When using the development tools, such as assembler, compiler, burner and firmware emulator of Shanghai Eastsoft IC Co, Ltd. or by the appointed third party, please follow the related specifications and instructions. Note: For any questions arising from product development, please contact us through the sales department or other ways V1.0 3/138

4 Ordering Information Part No. Program Memory Data Memory Package HR7P201FHD* DIP20 HR7P201FHS Flash: SRAM:1K Bytes SOP20 HR7P201FHS3 16K Words Data Flash: 2K Words SOP16 HR7P201FHS4 SOP14 Note*: This product is no longer available. HR 7P No. X X X Package: D-DIP20; S-SOP20/16/14 ROM Size:H 16K Words ( 32K Bytes ) ROM Type: F- FLASH ROM 201:MCU Model 7P:8-bit MCU Serial number : 5 th Floor, Building2A, Tianhua Information Science and Technology Park, Zip Code: No.299 Longcao Road, Shanghai, P.R.CHINA support@essemi.com Tel : Fax : Website : / Copyright SHANGHAI EASTSOFT MICROELECTRONICS CO., LTD. ALL RIGHTS RESERVED. The information in this document is believed to be accurate in all respects based on the existing data provided by Shanghai Eastsoft Microelectronics Co., Ltd.The examples in this document are subject to correct use and standard operations. Please take full considerations of external conditions when using the examples. Shanghai Eastsoft Microelectronics Co., Ltd makes no warranty, representations or guarantee regarding the suitability, fitness or completeness for these applications. Shanghai Eastsoft Microelectronics Co., Ltd does not bear any legal responsibility for any risk or consequence arising from the use of the information. Shanghai Eastsoft Microelectronics Co., Ltd reserves the rights to make modifications without further notice. For the latest information, please contact us using the above contact information. V1.0 4/138

5 Revision History Date Change Initial version, based on HR7P201_datasheet_c_V1.8 Note: Should you have any questions, please refer to the corresponding version of HR7P201_datasheet_c. V1.0 5/138

6 Contents Chapter1 Introduction Overview Applications Block Diagram Pin Diagrams Pin Pin Pin Pin Descriptions Pin Allocation Pin Multiplexing Chapter2 CPU Characteristics Overview System Clock and Machine Cycle Instruction Set Hardware Multiplier Hardware Divider Special Function Register Chapter3 Memory Program Memory Overview Program Counter (PC) Hardware Stack Program Memory Look-up Table Operation Overview Flash Data Memory Look-up Table Operation Overview Page Update Flowchart Reference Example Special Function Registers Data Memory Overview ing Modes Direct ing GPR Special ing Indirect ing Special Function Registers Allocation Special Function Registers Chapter4 I/O Ports Overview Block Diagram Weak Pull-up/ Pull-down V1.0 6/138

7 4. 4 Drive Strength Open Drain Output External Key Interrupt (KIN) External Port Interrupt (PINT) Special Function Registers Chapter5 Peripherals Timer/ Counter bit Timer/ Counter T8N Overview Block Diagram Operating Mode Prescaler Interrupt Flag Special Function Registers bit Time-based Timers (T8P1/T8P2/T8P3) Overview Block Diagram Prescaler and Postscaler Operating Mode Timer Mode PWM Mode Enhanced PWM Mode EPWM Auto Shutdown and Restart Start-of-AD Conversion by PWM Output Special Function Registers Touch Key Control (TK) Overview Block Diagram Touch Key Scan Principles Touch Key Port Touch Key Scan Flowchart Analog Comparator ACP Internal Reference Voltage Special Function Registers Universal Asynchronous Receiver Transmitter (UART) Overview Block Diagram Baud Rate Configuration Data Format Asynchronous Transmitter Asynchronous Receiver Special Function Registers I2C Slave Overview V1.0 7/138

8 I2C Port Configuration Communication Protocol Data Transfer Format Interrupt and Halt Special Function Registers Analog-to-Digital Converter ADC Overview Block Diagram AD Channel Selection AD Conversion Timing Reference Example Special Function Registers Chapter6 Special Functions and Operations System Clock and Oscillator Overview Crystal/ Ceramic Resonator Modes (HS/XT Mode) Internal Clock (INTOSC and INTOSCIO Mode) Special Function Registers Watchdog Timer (WDT) Overview Block Diagram Special Function Registers Reset Module Overview Reset Timing Diagram N_MRST Reset Reference Circuit Special Function Registers Interrupt Handler Overview Interrupt Mode Configuration Interrupt Logic Table Vectored Interrupt Mode Interrupt Vector Allocation Table Interrupt Vector Groups Interrupt Enable Configuration Special Function Registers Low Power Mode MCU Low Power Mode Low Power Mode Configuration Wake-up Sources Wake-up Time Special Function Registers Configuration Word Chapter7 Packaging Information V1.0 8/138

9 Pin Package Drawing Pin Packaging Drawing Pin Packaging Drawing Appendix1 Instruction Set Appendix1. 1 Overview Appendix1. 2 Register Instruction Appendix1. 3 Program Control Instruction Appendix1. 4 Arithmetic/Logical Operation Instructions Appendix2 Special Function Register Summary Appendix3 Electrical Characteristics Appendix3. 1 Parameter Characteristics Appendix3. 2 Characteristic Graphs V1.0 9/138

10 List of Figures Figure 1-1 HR7P201 Block Diagram Figure 1-2 HR7P201 (DIP20/SOP20) Top view Figure 1-3 HR7P201 (SOP16) Top view Figure 1-4 HR7P201 (SOP14) Top view Figure 2-1 Hardware Multiplier Block Diagram Figure 2-2 Hardware Divider Block Diagram Figure 3-1 Program Memory Map and Stack Figure 3-2 Page Update Reference Flowchart Figure 3-3 Direct ing Diagram Figure 3-4 GPR Special ing Diagram Figure 3-5 Indirect ing Block Diagram Figure 4-1 Input/Output Block Diagram Figure 5-1 T8N Block Diagram Figure 5-2 T8Px Block Diagram Figure 5-3 Standard PWM Mode Diagram Figure 5-4 Standard PWM Output Diagram Figure 5-5 EPWM Single Bridge Output Diagram Figure 5-6 EPWM Half Bridge Output Diagram Figure 5-7 EPWM Shutdown and Auto Restart (PRESNx=1) Figure 5-8 EPWM Shutdown and Restart (PRESNx=0) Figure 5-9 Touch Key Block Diagram Figure 5-10 No Touch State Diagram Figure 5-11 Touch State Diagram Figure 5-12 Touch Key Operation Flowchart Figure 5-13 UART Block Diagram Figure 5-14 UART Data Format Diagram Figure 5-15 UART Asynchronous Transmission Flowchart Figure 5-16 UART Asynchronous Reception Flowchart Figure 5-17 I2C Bus Communication Protocol Figure 5-18 Master Device Writing to Slave Device Figure 5-19 Master Device Reading from Slave Device Figure 5-20 ADC Block Diagram Figure 5-21 AD Channel Configuration Figure 5-22 ADC Conversion Timing (SMPS=1) Figure 6-1 System Clock Block Diagram Figure 6-2 Crystal / Ceramic Resonator mode (HS/XT mode) Figure 6-3 WDT Block Diagram Figure 6-4 Reset Block Diagram Figure 6-5 POR Timing Diagram Figure 6-6 BOR Timing Diagram Figure 6-7 N_MRST Reset Reference Circuit Figure 6-8 N_MRST Reset Reference Circuit Figure 6-9 Interrupt Control Logic V1.0 10/138

11 List of Tables Table 1-1 Pin Allocation Table 1-2 Pins Multiplexing Table 3-1 Flash Data Memory Table Table 3-2 Data Memory Map Table 4-1 IO Ports Weak Pull-Up Table 4-2 I/O Ports Weak Pull-Down Table 4-3 I/O Ports High Drive Table 4-4 I/O Ports Open Drain Output Table 4-5 External Key Interrupt Table 4-6 External Port Interrupt Table 5-1 T8N Operating Mode Configuration Table 5-2 T8N Prescaler Configuration Table 5-3 T8Px Postscaler Configuration Table 5-4 T8Px Prescaler Configuration Table 5-5 T8Px Operating Mode Configuration Table Table 5-6 UART Baud Rate Configuration Table 5-7 AD Channel Configuration Table 6-1 Crystal Oscillator Capacitor Parameter Table 6-2 Interrupt Mode Configuration Table 6-3 Interrupt Logic Table (Default Interrupt Mode) Table 6-4 Interrupt vector configuration table Table 6-5 Interrupt Vector Groups Table 6-6 Vectored Interrupt Mode Enable Configuration Table 6-7 Low Power Mode Configuration Table 6-8 Wake Up Configuration Table 6-9 Wake Up Time Calculation V1.0 11/138

12 Chapter1 Introduction 1. 1 Overview CPU HR7P RISC CPU 79 RISC Maximum Operating Frequency up to 16MHz Instruction cycle : 2 system clock cycles Reset Vector located at 0000 H, Interrupt Vector located at 0004 H Supports Interrupt Handler, Interrupt Priority and Interrupt Vector Table Memory 16K Words Flash Program Memory 8-level Program Stack 2K Words Flash Data Memory - Total of 4 pages, supports page erase - Timer module remains active while erasing and programming - Interrupt handler not supported while erasing and programming 1K Bytes SRAM Data Memory Program memory supports Direct ing, Relative ing and Look-Up Table Read Operation Data Memory supports Direct ing, GPR Special ing and Indirect ing I/O Ports Up to 17 I/Os - Port A (PA0~PA1,PA3~PA7) - Port B (PB0~PB7) - Port C (PC0~PC1) 2 External Port Interrupts PINT(PINT0~ PINT1 are inputs) 4 External Key Interrupts KINT(KIN0~KIN3 are inputs) Individually configurable internal weak pull-up/pull-down - ±5% matching accuracy of pull-up/pull-down resistors - Supports17 input ports with individually configurable weak pull-up/pull-down 7 ports with individually configurable high drive Resets and Clocks Power On Reset POR Brown Out Reset BOR External Reset V1.0 12/138

13 Independent hardware Watchdog Timer External HS/XT Oscillator Internal 16MHz high frequency RC Oscillator - ±2% calibration accuracy (at 25 ) Peripherals 8-Bit Timer T8N - Timer Mode (F OSC )/Counter Mode (External counter clock input) - Configurable Prescaler - Interrupt capability 8-Bit PWM Timer T8P1/T8P2/T8P3 - Timer Mode(F OSC ) - Configurable Prescaler and Postscaler - 3 complementary enhanced PWM (EPWM) with dead zone - EPWM output shutdown by external ports - EPWM output shutdown by analog comparator output - EPWM Auto-Restart - Interrupt capability Analog to Digital Convertor (ADC) - 12-Bit resolution - 15 analog input channels - Selectable reference voltage - Internal reference voltage calibration with ±2% accuracy at 25 - Interrupt capability Touch Key Function Module(TK) - Up to 14 Touch Keys - Operating frequency 4MHz, 2MHz, 1MHz and 500KHz - Selectable reference Voltages - Supports touch key scan interrupt High-Speed Universal Asynchronous Receiver/Transmitter (UART) - Asynchronous full duplex - 8-Bit/9-Bit data length - Data order with LSB first - Interrupt capability I2C Bus - Slave mode only - Supports standard I2C bus protocol, data rate up to 400KBit/s - 7-bit addressing - Interrupt capability Analog Comparator - Interrupt capability - Selectable input voltage source High Precision Reference Voltage Source V1.0 13/138

14 - Calibration accuracy within ±2% (Room temperature, 25 ) - 2.5V calibrated voltage output - Two reference voltage outputs - Multiple reference voltages Low Power Consumption Idle current - 16uA@3.0V,25,typical Dynamic current - 2mA@ Internal 16MHz,5.0V,25,typical Program and Debug Interface In System Program (ISP) Interface In Circuit Debugger (ICD) Program code encryption Design and Packages Low power, high speed Flash, CMOS technology DIP20 /SOP20 (HR7P201FHD/S) SOP16 (HR7P201FHS3) SOP14 (HR7P201FHS4) Operating Conditions 1. 2 Applications Operating Voltage: 3.0V ~ 5.5V The HR7P201 is an ideal solution for small home appliances, touch keys and etc. V1.0 14/138

15 1. 3 Block Diagram Program Memory 16K Words FLASH ROM FLASH Program Memory Access Controller HR7P201 Oscillator Program Bus Interface 8-Level Program Stack ALU CPU PC Instruction Fetch & Decode Module SRAM Access Controller 1K Bytes SRAM Special Function Interface Data Bus Interface Reset Controller WDT Interrupt Controller Special Function IO/IO MUX T8N T8P1/T8P2/T8P3 ACP/VREF UART IIC External Peripherals N_MRST PA<1:0> PA<7:3> PB<7:0> PC<1:0> FLASH Data Memory Access Controller 2K Words Data FLASH TK ADC Figure 1-1 HR7P201 Block Diagram 1. 4 Pin Diagrams Pin VSS 1 20 VDD PA0/OSC2/AIN0/TK0/CKO 2 19 PC1/SCL/TX/ISPCK/PINT1 PA1/OSC1/CKI/AIN1/TK1/PWM10 N_MRST PA3/AIN2/TK2/N_EPAS PA4/AIN3/TK3/T8NCKI/VREFN PA5/AIN4/TK4/PWM HR7P201FHD/S PC0/SDA/RX/ISPDAT/PINT0 PB7/VREF/VOUT/CMP/TKCX/KIN3/VREFP PB6/AIN13/TK13/KIN PB5/AIN12/TK12/KIN1 PB4/AIN11/TK11/KIN0/ADV PA6/AIN5/TK5/PWM PB3/AIN10/TK10/PWM21 PA7/AIN6/TK6/PWM PB2/AIN9/TK9/PWM31 PB0/AIN7/TK7/PWM PB1/AIN8/TK8/PWM21 Figure 1-2 HR7P201 (DIP20/SOP20) Top view V1.0 15/138

16 Pin VSS 1 16 VDD PA0/OSC2/AIN0/TK0/CKO 2 15 PC1/SCL/TX/ISPCK/PINT1 PA1/OSC1/CKI/AIN1/TK1/PWM10 N_MRST PA3/AIN2/TK2/N_EPAS PA4/AIN3/TK3/T8NCKI/VREFN PA5/AIN4/TK4/PWM HR7P201FHS PC0/SDA/RX/ISPDAT/PINT0 PB7/VREF/VOUT/CMP/TKCX/KIN3/VREFP PB6/AIN13/TK13/KIN PB5/AIN12/TK12/KIN1 PB4/AIN11/TK11/KIN0/ADV PA6/AIN5/TK5/PWM PB3/AIN10/TK10/PWM21 Figure 1-3 HR7P201 (SOP16) Top view Pin VSS 1 14 VDD PA0/OSC2/AIN0/TK0/CKO PA1/OSC1/CKI/AIN1/TK1/PWM10 N_MRST PA3/AIN2/TK2/N_EPAS PA4/AIN3/TK3/T8NCKI /VREFN HR7P201FHS PC1/SCL/TX/ISPCK/PINT1 PC0/SDA/RX/ISPDAT/PINT0 PB7/VREF/VOUT/CMP/TKCX/KIN3/VREFP PB6/AIN13/TK13/KIN2 6 9 PB5/AIN12/TK12/KIN1 PA5/AIN4/TK4/PWM PB4/AIN11/TK11/KIN0/ADV Figure 1-4 HR7P201 (SOP14) Top view Note1: N_MRST and N_EPAS0 are active-low. Note2: PWM20 and PWM21 of T8P2 can be configured by software. Note3: If the pin count on the product package is less than the maximum pin count, the unpackaged pins and unused pin should be set to output low. Otherwise, it might cause irregular power consumption behavior, and the product stability might also be affected by outside interference. V1.0 16/138

17 1. 5 Pin Descriptions Pin Allocation Pin HR7P201 20pin 16pin 14pin PA0/AIN0/OSC2/TK0/CKO PA1/AIN1/OSC1/CKI/TK1/PWM PA3/AIN2/TK2/N_EPAS PA4/AIN3/TK3/T8NCKI/VREFN PA5/AIN4/TK4/PWM PA6/AIN5/TK5/PWM / PA7/AIN6/TK6/PWM30 9 / / PB0/AIN7/TK7/PWM20 10 / / PB1/AIN8/TK8/PWM21 11 / / PB2/AIN9/TK9/PWM31 12 / / PB3/AIN10/TK10/PWM / PB4/AIN11/TK11/KIN0/ADV PB5/AIN12/TK12/KIN PB6/AIN13/TK13/KIN PB7/VREF/VOUT/CMP/TKCX/KIN3/VREFP PC0/SDA/RX/ISPDAT/PINT PC1/SCL/TX/ISPCK/PINT N_MRST VDD VSS Table 1-1 Pin Allocation V1.0 17/138

18 Pin Multiplexing Pin Name Multiplexing A/ D Port Description PA0 D General purpose I/O AIN0 A ADC analog channel 0 input PA0/AIN0/OSC2/TK0/CKO OSC2 A Crystal / Resonator pin 2 TK0 A Touch key input 0 CKO D Fosc/16 reference clock output PA1 D General purpose I/O AIN1 A ADC analog channel 1 input Crystal / Resonator OSC1 A PA1/AIN1/OSC1/CKI/TK1/ pin 1 PWM10 A/ CKI D System clock input TK1 A Touch key input 1 PWM10 D T8P1 extended PWM output N_MRST N_MRST - External reset input (active low) Notes Supports large current / weak pull-up/pull-do wn and open drain output Supports large current / weak pull-up/pull-do wn and open drain output Weak pull -up enable PA3/AIN2/TK2/N_EPAS PA4/AIN3/TK3/T8NCKI/ VREFN PA3 D General purpose I/O Supports large ADC analog channel 2 AIN2 A current / input weak TK2 A Touch key input 2 pull-up/pull-do N_EPAS D Shutdown event input wn and open drain output PA4 D General purpose I/O AIN3 A ADC analog channel 4 input Supports large TK3 A Touch key input 3 current / T8NCKI D T8N external clock weak pull-up/ input pull-down and ADC external open drain VREFN A reference voltage output negative input V1.0 18/138

19 Pin Name Multiplexing A/ D Port Description Notes PA5/AIN4/TK4/PWM11 PA6/AIN5/TK5/PWM20 PA7/AIN6/TK6/PWM30 PB0/AIN7/TK7/PWM20 PA5 D General purpose I/O Supports large ADC analog channel 4 AIN4 A current / input weak TK4 A Touch key input 4 pull-up/pull-do PWM11 D T8P1 complementary PWM output wn and open drain output PA6 D General purpose I/O Supports large ADC analog channel 5 AIN5 A current / input weak TK5 A Touch key input 5 pull-up/pull-do PWM20 D T8P2 PWM output wn and open drain output PA7 D General purpose I/O Supports large ADC analog channel 6 AIN6 A current / input weak pull-up/ TK6 A Touch key input 6 pull-down and PWM30 D T8P3 PWM output open drain output PB0 D General purpose I/O Supports weak ADC analog channel 7 AIN7 A pull-up/pull-do input wn and open TK7 A Touch key input 7 drain output PWM20 D T8P2 PWM output PB1/AIN8/TK8/PWM21 PB1 D General purpose I/O AIN8 A ADC analog channel 8 input TK8 A Touch key input 8 PWM21 D T8P2 PWM output PB2 D General purpose I/O Supports weak pull-up/pull-do wn and open drain output PB2/AIN9/TK9/PWM31 PB3/AIN10/TK10/PWM21 AIN9 A ADC analog channel 9 input Supports weak pull-up/pull-do TK9 A Touch key input 9 wn and open drain output T8P3 complementary PWM31 D PWM output PB3 D General purpose I/O Supports weak AIN10 A ADC analog channel pull-up/pull-do V1.0 19/138

20 Pin Name Multiplexing A/ D Port Description Notes 10 input wn and open TK10 A Touch key input 10 drain output PWM21 D T8P2 complementary PWM output PB4/AIN11/TK11/KIN0 /ADV PB4 D General purpose I/O AIN11 A ADC analog channel 11 input TK11 A Touch key input 11 KIN0 D External key interrupt 0 input Supports weak pull-up/pull-do wn and open drain output ADV A ADC reference voltage output PB5/AIN12/TK12/KIN1 PB6/AIN13/TK13/KIN2 PB5 D General purpose I/O AIN12 A ADC analog channel 12 input TK12 A Touch key input 12 KIN1 D External key interrupt 1 input PB6 D General purpose I/O AIN13 A ADC analog channel 13 input TK13 A Touch key input 13 KIN2 D External key Interrupt 2 input PB7 D General purpose I/O Supports weak pull-up/pull-do wn and open drain output Supports weak pull-up/pull-do wn and open drain output VREF A External reference voltage input PB7/VREF/VOUT/CM P/TKCX/KIN3/VREFP VOUT CMP D A Internal reference voltage output Comparator common input port Supports weak pull-up/pull-do wn and open drain output TKCX A TK external capacitor CX input KIN3 D External keys Interrupt 3 input V1.0 20/138

21 Pin Name Multiplexing A/ D Port Description Notes VREFP A ADC reference voltage positive input PC0/SDA/RX/ISPDAT/ PINT0 PC1/SCL/TX/ISPCK/ PINT1 PC0 D General purpose I/O SDA D I2C data input / output RX D UART receive input ISPDAT D ISP serial data input / output PINT0 D External port Interrupt 0 input PC1 D General purpose I/O SCL D I2C clock input TX D UART transmitter output ISPCKI D ISP serial clock input PINT1 D External port Interrupt 1 input Supports weak pull-up/pull-do wn and open drain output Supports weak pull-up/pull-do wn and open drain output VDD VDD - Power Supply VSS VSS - GND,0V Reference Table 1-2 Pins Multiplexing Note1: A= Analog, D = Digital Note2: N_MRST and N_EPAS0 are active-low. Note3: PWM20 and PWM21 of T8P2 can be configured by software. V1.0 21/138

22 Chapter2 CPU Characteristics 2. 1 Overview CPU Features HR7P RISC CPU 79 RISC Maximum operating frequency up to 16MHz Machine cycle :2 system clock cycles Supports interrupt handler and interrupt vector table, total 7 interrupt sources 2. 2 System Clock and Machine Cycle The system clock of HR7P201 operates up to max. 16MHz. The on-chip clock generator divides the input clock into two non-overlapping orthogonal clocks termed as phase1 (p1) and phase2 (p2), which compose one machine cycle 2. 3 Instruction Set HR7P201 uses 79 RISC instructions of HR7P series. Most of the instructions are executed within a single machine cycle, except the instructions of some conditional jumps and program control operations, whose executions take two machine cycles. One single machine cycle is 500ns if the system clock frequency is 4 MHz. For details, please refer to Appendix Instruction Set Hardware Multiplier System Clock Bus Read Bus Write Bus Bus Interface MULA MULB MULL Multiplier Control Bus MULH MUL Figure 2-1 Hardware Multiplier Block Diagram Hardware Multiplier: [8-Bit Multiplicator A] x [8-Bit Multiplicator B] = 16Bit Product. The multiplicators A and B are set respectively by register MULA and MULB. These two registers are write-only. The product is stored in registers MULH and MULL, which are read-only. MULA and MULL V1.0 22/138

23 share the same register address and MULB and MULH also share the same register address. The result of multiplication is available for read-out in the next instruction cycle after MULA and MULB are written Hardware Divider System Clock DIVEL Bus DIVEH Read Bus Write Bus Control Bus Bus Interface DIVS DIVQL DIVQH Divider DIVR DIV Figure 2-2 Hardware Divider Block Diagram Hardware Divider: 16-Bit Dividend / 8-Bit Divisor= 16-Bit Quotient and 8-Bit Remainder. The dividend is set by DIVEH and DIVEL and the divisor is set by DIVS. These three registers are write-only. The quotient is stored to DIVQH and DIVQL and the remainder is stored to DIVR. These three registers are read-only. DIVEL and DIVQL share the same register address, so does DIVEH and DIVQH, and DIVS and DIVR. After divider and dividend are set, 2 NOP instructions are to be executed before reading out the quotient and remainder. The quotient is 0xFFFF and the remainder 0xFF if divisor is 0, which indicates an overflow of calculation. V1.0 23/138

24 2. 6 Special Function Register Program Status Word Register(PSW) FF84 H Reset value x00x xxxx C bit0 R/W Carry /Borrow Bit 0:No carry or one borrow 1:One carry or no Borrow DC bit1 R/W Half Carry /Half Borrow Bit 0:No carry or one borrow on lower 4 bits 1:One carry or no borrow on lower 4 bits Z bit2 R/W Zero flag bit 0:The result of an arithmetical or logical operation is not zero 1:The result of an arithmetical or logical operation is zero OV bit3 R/W Overflow flag bit 0:No overflow of signed arithmetic operations 1:Overflow N bit4 R/W Negative flag bit 0:The result of an arithmetical or logical operation is positive 1:The result is negative OF bit5 R Program stack overflow flag bit 0:No overflow occurred 1:Overflow occurred UF bit6 R Program stack underflow flag bit 0:No underflow occurred 1:Underrflow occurred - bit7 - - Note1: Only some instructions can actually write PSW register, which are JDEC, JINC, SWAP, BCC, BSS, BTT, MOVA and SETR. Other instructions can only affect the flag bits according to the operation results. Note2: OF and UF flags are read-only and can only reset by power on reset, reset instruction and N_MRST. Other reset operations do not affect OF or UF. Accumulator Register (AREG) FF85 H Reset value xxxx xxxx A<7:0> bit7-0 R/W Register A<7:0> V1.0 24/138

25 Program Counter Register Low Byte (PCRL) FF86 H Reset value PCRL<7:0> bit7-0 R/W Program counter low byte Program Counter Register High Byte (PCRH) FF87 H Reset value PCRH<5:0> Bit5-0 R/W Program counter higher 6 bits - Bit7-6 - Multiplier A register (MULA)/ Product Register Low Byte (MULL) FF88 H Reset value xxxx xxxx MULA<7:0> W Multiplicator A bit7-0 MULL<7:0> R Product low byte Multiplier B register (MULB)/ Product Register High Byte (MULH) FF89 H Reset value xxxx xxxx MULB<7:0> W Multiplicator B bit7-0 MULH<7:0> R Product high byte Dividend Register Low Byte (DIVEL)/ Quotient Register Low Byte (DIVQL) FF8A H Reset value xxxx xxxx DIVEL<7:0> W Dividend low byte bit7-0 DIVQL<7:0> R Quotient low byte Dividend Register High Byte (DIVEH)/ Quotient Register High Byte (DIVQH) FF8B H Reset value xxxx xxxx DIVEH<7:0> W Dividend high byte bit7-0 DIVQH<7:0> R Quotient high byte Divisor Register (DIVS)/ Remainder Register (DIVR) FF8C H Reset value xxxx xxxx DIVS<7:0> W Divisor bit7-0 DIVR<7:0> R Remainder V1.0 25/138

26 Chapter3 Memory 3. 1 Program Memory Overview The program memory of HR7P201 is 16K words Flash memory, with address range 0000 H to 3FFF H. Accessing a location beyond the above range will cause PC to repeatedly addressing in the address range. The reset vector is located at 0000 H, and the default interrupt vector is located at 0004 H H Reset Vector Program Counter(PC) User Program Memory 0004 H 3FFF H Interrupt Vector 8-level Stack Stack Control Figure 3-1 Program Memory Map and Stack Program Counter (PC) HR7P201 has a 14-bit program counter PC<13:0> and the program memory capacity is 16K Words, in the range 0000 H to 3FFF H. Accessing a location beyond that range will cause a PC overflow.(pc returns to 0000H). Low byte of PC<7:0> can be read and written directly through PCRL, while PC higher 6 bits cannot be directly read or written and can only be assigned by register PCRH indirectly. After reset, PCRL, PCRH and PC are cleared. PC hardware stack operations do not affect the value of PCRH. How PC is affected by different instructions: 1. When directly modifying PC value through instructions, if PCRL is the destination register, it can be directly modified by PC<7:0>=PCRL<7:0>; at the same time, it will execute PC<13:8>=PCRH<5:0>. Thus, when modifying PC value, PCRH<5:0> should be modified first then PCRL<7:0>. 2. When executing RCALL instruction, PC<7:0> is the value of register R and PC<13:8>=PCRH<5:0> 3. When executing CALL and GOTO, the lower 11 bits of PC<10:0> is the 11-bit immediate of the instruction and PC<13:12> =PCRH<5:4>. 4. LCALL instruction is a double-word instruction, which has 16-bit immediate (operand). PC<11:0> will be modified to the lower 14 bits of the 16-bit immediate and PCRH<5:0> will be modified to the value of I<13:8> 5. AJMP instruction is also a double-word instruction, which has 16-bit immediate. PC<13:0> will be modified to the lower 14 bits of the 16-Bit immediate and PCRH<5:0> will be modified to I<13:8>. V1.0 26/138

27 6. When executing PAGE instruction, PCRH<5:3> will be replaced with the immediate I<2:0> of the instruction. 7. When executing other instructions, the PC value will automatically increase by Hardware Stack The device has an 8-level hardware stack, whose width is the same as PC, and the stack is used for push and pop instructions. When executing CALL, LCALL and RCALL instructions or responding interrupt, the PC is automatically pushed onto stack for protection. When executing RET, RETIA or RETIE instructions, the stack restores the most recent value to PC. The stack only saves the latest 8 pushed values. If the stack has been pushed for 8 times, the 9th push will cause the first push value to be overwritten. Likewise, the 9th pop may make the program out of control Program Memory Look-up Table Operation Overview Only read operation is supported by program memory. Look-up-table read operation reads a word, which is pointed by instruction FRA (FRAH, FRAL), into ROMD (ROMDH, ROMDL) Flash Data Memory Look-up Table Operation Overview The Flash data memory has total 4 pages with 1K bytes per page and supports Look-up table read, write and erase. The address range is from 4000 H to 47FF H. Look-up table read operation reads one word in the memory location which is pointed by FRA (FRAH, FRAL) into ROMD (ROMDH, ROMDL) through look-up table read instruction. Erase operation is accomplished by look-up table read instruction and memory control registers (ROMCH, ROMCL), including three basic operations, data backup, page erase and word programming. When users are performing erase in program memory, the Flash data memory is also erased. The Flash data memory is erased in a page by page fashion. The page which is pointed by FRAH is erased via memory control register (ROMCH, ROMCL). Performing a page erase takes at least 2ms. Word programming writes the 16-bit value of ROMD (ROMDH, ROMDL) into the memory location pointed by FRA. Single address programming takes at least 20us. The configuration word register CFG_WD<9> (FREN) is the enable bit for Look-up table operation. If FREN is 1, page erase and word programming are allowed otherwise the erase and write operations are ignored. V1.0 27/138

28 Before performing erase and write in Flash data memory, disable the WDT timer function to avoid chip reset. Page Memory Capacity (Byte) range 1 1K 4000 H ~41FF H 2 1K 4200 H ~43FF H 3 1K 4400 H ~45FF H 4 1K 4600 H ~47FF H Table 3-1 Flash Data Memory Table Page Update Flowchart Start Backup the entire page data to RAM Update required RAM data Perform page erase operation Write RAM data to ROM Perform word programming FRA + 1 Next address? Y N Error Check correct End Figure 3-2 Page Update Reference Flowchart V1.0 28/138

29 Steps for one update: 1. Backup the page data to data memory space through look-up table. ( 512 x 2 x 8bit memory size is required for one page data) 1. Update the required data in the backup data memory space 2. Perform page erase by configuring ROMCL and ROMCH registers and it is necessary to follow the routine. 3. Configure the required address by FRAL / FRAH registers and the required data by ROMDL / ROMDH registers. 4. Write the content of ROMDL and ROMDH to the address pointed by FRA through ROMCL and ROMCH and it is necessary to follow the routine. 5. Repeat step 4 and 5 until the entire page programming is done 6. Check the updated data through look-up table Reference Example Application Example1: Look-up table read operation in data memory. MOVI 0x05 ; Read data from 4105H in Flash data memory MOVA FRAL MOVI 0x41 MOVA FRAH TBR ; Execute Look-up table read instruction to read data to ; the ROMDH/ROMDL MOV ROMDH, 0 MOV ROMDL, 0 V1.0 29/138

30 Application Example2: Page Erase in data memory. During erasing, the program will stop running except for Timer/Counter, and will recover automatically after erasing is completed. MOVI 0X40 ; Erase the first page (Page address range ; from 4000 H to 41FF H ) MOVA FRAH MOVI 0X00 MOVA FRAL BSS ROMCL, FPEE ; Select the erase operation BSS ROMCL, WREN ; Enable erase/programming operation BCC INTG, GIE ; Disable global interrupt to avoid affecting the routine below MOVI MOVA MOVI MOVA BSS NOP 0X55 ROMCH 0xAA ROMCH ROMCL, WR ; 8 NOP instructions, or wait for 8 instruction cycles ; 8 NOP instructions, or wait for 8 instruction cycles V1.0 30/138

31 Application Example3:write the data buffer into data memory. During erasing, the program will stop running except for Timer /Counter, and will recover automatically after erasing is completed. MOVI 0x40 ; Write to the first address in the first page MOVA MOVI MOVA MOVI MOVA MOVI FRAH 0x00 FRAL 0x12 ROMDH 0x34 ; of the Flash data memory MOVA ROMDL ; Write data 1234 H BCC ROMCL, FPEE ; Select programming BSS ROMCL, WREN ; Enable Flash erase/programming BCC INTG, GIE ; Disable global interrupt to avoid affecting the routine below MOVI 0x55 MOVA ROMCH ; 8 NOP instructions, or wait for 8 instruction cycles MOVI 0xAA MOVA ROMCH ; 8 NOP instructions, or wait for 8 instruction cycles BSS ROMCL, WR NOP Note: The program in the box is a fixed routine and users should not modify it. V1.0 31/138

32 Special Function Registers Reg.Name Reset value Flash Read Register Low Byte (FRAL) FF90 H xxxx xxxx FRAL<7:0> bit7-0 R/W Program memory look-up-table address low byte Reg.Name Reset value Flash Read Register High Byte (FRAH) FF91 H xxxx xxxx FRAH<7:0> bit7-0 R/W Program memory look-up-table address high byte Reg.Name Reset value ROM Date Register Low Byte (ROMDL) FF92 H xxxx xxxx ROMDL<7:0> bit7-0 R/W Program memory look-up-table data register low byte Reg.Name Reset value ROM Date Register High Byte (ROMDH) FF93 H xxxx xxxx ROMDH<7:0> bit7-0 R/W Program memory look-up-table data register high byte Reg.Name ROM Control Register Low Byte (ROMCL) FF94 H Reset value bit0 - - WR bit1 R/W Program memory erase / program trigger bit 0: Not activated or completed 1: Erase / programming in progress (cleared by hardware automatically) WREN bit2 R/W Program memory page erase / program enable bit 0: Disabled 1: Enabled FPEE bit3 R/W Program memory page erase / program select bit 0: Programming 1: Erase - bit V1.0 32/138

33 Reg.Name ROM Control Register Low Byte (ROMCH) FF95 H Reset value ROMCH<7:0> bit7-0 R/W Program memory erase / program control word Note: ROMCH is a virtual register and always read as 0. V1.0 33/138

34 3. 2 Data Memory Overview Data memory consists of two parts, including general purpose registers GPR and special function registers SFR. GPRs is divided into 8 sections, section 0~7, in the range of 0000 H ~03FF H. There are 128 special function registers in the range of FF80 H ~FFFF H. Data memory supports three addressing modes: direct addressing, GPR special addressing and indirect addressing. Range Data Memory 0000 H ~ 007F H GPR Section H ~ 00FF H GPR Section H ~ 017F H GPR Section H ~ 01FF H GPR Section H ~ 027F H GPR Section H ~ 02FF H GPR Section H ~ 037F H GPR Section H ~ 03FF H GPR Section 7 Table 3-2 Data Memory Map ing Modes Direct ing Direct addressing includes two parts, BKSR bit and 8-Bit address information in instruction. BKSR bit is used for memory section selection, and 8-bit address information in instruction is used for addressing in selected section. When the 8-bit address information is greater than or equal to 80 H, the SFR mapping area is directly accessed without BKSR. V1.0 34/138

35 R<7:0> (< 80H) { ( 80H) GPR SECTION0 GPR SECTION1 } } BKSR GPR Map GPR SECTION7 } Reserved SFR SFR Figure 3-3 Direct ing Diagram GPR Special ing MOVAR and MOVRA instructions are used for read/write operations on GPR special addressing. These two instructions support 10-bit address information R<9:0>, so they can access 1K bytes address space without switching between sections. MOVAR and MOVRA instructions cannot access SFR. R<9:0> GPR SECTION0~7 Reserved Figure 3-4 GPR Special ing Diagram V1.0 35/138

36 Indirect ing 8-bit IAAH and 8-bit IAAL constitute a 16-Bit indirect addressing address register, and the addressing space is 0000 H ~FFFF H. Indirect addressing can be completed through the IAD register read/write operation. Register IAD has the physical address at FF80 H, which suggests the register could also be indirectly addressed. However, reading IAD itself using indirect addressing always gets 00 H, writing IAD register indirectly is regarded as a NOP operation (Status bits may be affected). ISTEP instruction is used to calculate the offset for indirect addressing address register IAAH/IAAL. This instruction supports 8-bit signed immediate operand, and the offset range is -128~127. The ISTEP instruction is a 16-bit calculation for IAA (IAAL and IAAH), although there is only one 8-bit immediate operand. The result of calculation is stored in IAAL and IAAH. ISTEP I<7:0> 0000 H GPR Bank 0 (0000 H ~007F H ) GPR Bank 1 (0080 H ~00FF H ) IAA<15:0>+I<7:0> IAD<7:0> 03FF H GPR Bank 7 (0380 H ~03FF H ) Reserved FF80 H IAD Indirect addressing data register FF81 H IAAL Indirect addressing address register<7:0> FFFF H - Reserved Figure 3-5 Indirect ing Block Diagram V1.0 36/138

37 Special Function Registers Allocation Function Description Note FF80 H IAD Indirect ing Data Register FF81 H IAAL Indirect ing Register Low Byte FF82 H IAAH Indirect ing Register High Byte FF83 H BKSR Memory Section Register FF84 H PSW Program Status Word Register FF85 H AREG Accumulator Register FF86 H PCRL Program Counter Low Byte FF87 H PCRH Program Counter High Byte FF88 H MULA/MULL Multiplier A Register / Product Register Low Byte FF89 H MULB/MULH Multiplier B Register / Product Register High Byte FF8A H DIVEL/DIVQL Dividend Register Low Byte / Quotient Register Low Byte FF8B H DIVEH/DIVQH Dividend Register High Byte / Quotient Register High Byte FF8C H DIVS/DIVR Divisor Register / Remainder Register Low Byte FF8D H - - CPU Control Area FF8E H - - FF8F H - - FF90 H FRAL Flash Read Register Low Byte FF91 H FRAH Flash Read Register High Byte FF92 H ROMDL ROM Data Register Low Byte ROM Control Area FF93 H ROMDH ROM Data Register High Byte FF94 H ROMCL ROM Control Register Low Byte FF95 H ROMCH ROM Control Register High Byte FF96 H INTG Interrupt Global Register FF97 H INTP Interrupt Priority Register FF98 H INTC0 Interrupt Control Register 0 FF99 H - - FF9A H INTE0 Interrupt Enable Register 0 FF9B H INTF0 Interrupt Flag Register 0 FF9C H INTE1 Interrupt Enable Register 1 Interrupt Control Area FF9D H INTF1 Interrupt Flag Register 1 FF9E H INTE2 Interrupt Enable Register 2 FF9F H INTF2 Interrupt Flag Register 2 FFA0 H - Reserved V1.0 37/138

38 Function Description Note FFA1 H - Reserved FFA2 H VREFCAL Internal Reference Voltage Calibration Register FFA3 H WDTCAL WDT Clock Calibration Control Register FFA4 H OSCCALL Internal 16MHz Clock Calibration Register Low Byte FFA5 H OSCCALH internal 16MHz Clock Calibration Register High Byte FFA6 H PWRC Power Control Register Special Function Control Area FFA7 H WDTC WDT Control Register FFA8 H WKDC Wake-up Delay Control Register FFA9 H PWEN Power Enable Register FFAA H PA Port A Register FFAB H PAT Port A Tristate Register FFAC H PB Port B Register FFAD H PBT Port B Tristate Register FFAE H PC Port C Register FFAF H PCT Port C Tristate Register FFB0 H PAPU Port A Pull-up Register FFB1 H PBPU Port B Pull-up Register FFB2 H PCPU Port C Pull-up Register FFB3 H PALC Port A Large Current Register I / O control Area FFB4 H PAOD Port A Open Drain Register FFB5 H PBOD Port B Open Drain Register FFB6 H PCOD Port C Open Drain Register FFB7 H PAPD Port A Pull-down Register FFB8 H PBPD Port B Pull-down Register FFB9 H PCPD Port C Pull-down Register FFBA H - - FFBB H T8N T8N Counter FFBC H T8NC T8N Control Register FFBD H T8P1 T8P1 Counter FFBE H T8P1C T8P1 Control Register FFBF H T8P1P T8P1 Period Register FFC0 H T8P1RL T8P1 Resolution Register FFC1 H T8P1RH T8P1 Resolution Buffer Register FFC2 H T8P1OC EPWM1 Output Control Register Peripheral Control Area FFC3 H T8P2 T8P2 Counter FFC4 H T8P2C T8P2 Control Register FFC5 H T8P2P T8P2 Period Register FFC6 H T8P2RL T8P2 Resolution Register V1.0 38/138

39 Function Description Note FFC7 H T8P2RH T8P2 Resolution Buffer Register FFC8 H T8P2OC EPWM2 Output Control Register FFC9 H T8P3 T8P3 Counter FFCA H T8P3C T8P3 Control Register FFCB H T8P3P T8P3 Period Register FFCC H T8P3RL T8P3 Resolution Register FFCD H T8P3RH T8P3 Resolution Buffer Register FFCE H T8P3OC EPWM3 Output Control Register FFCF H EPWM1C EPWM1 Configuration Register 1 FFD0 H EPWM2C EPWM2 Configuration Register 2 FFD1 H EPWM3C EPWM3 Configuration Register 3 FFD2 H PDD1C EPWM1 Dead-zone Delay Control Register 1 FFD3 H PDD2C EPWM2 Dead-zone Delay Control Register 2 FFD4 H PDD3C EPWM3 Dead-zone Delay Control Register 3 FFD5 H TE1AS EPWM1 Auto Shutdown Register 1 FFD6 H TE2AS EPWM2 Auto Shutdown f Register 2 FFD7 H TE3AS EPWM3 Auto Shutdown Register 3 FFD8 H TMRADC PWM Edge Detect Delay Register FFD9 H ADCTST ADC Parameter Register FFDA H ADCRL ADC Result Register Low Byte FFDB H ADCRH ADC Result Register High Byte FFDC H ADCCL ADC Control Register Low Byte FFDD H ADCCH ADC Control Register High Byte FFDE H ANSL Analog Select Register Low Byte FFDF H ANSH Analog Select Register High Byte FFE0 H RXB UART Receive Buffer Register FFE1 H RXC UART Receive Control Register FFE2 H TXB UART Transmit Buffer Register FFE3 H TXC UART Transmit Control Register FFE4 H BRR UART Baud Rate Register FFE5 H TKSEL Touch Key Select Register FFE6 H TKTUN Touch Key Tune Register FFE7 H TKCTL Touch Key Control Register FFE8 H TKDAL Touch Key Data Register Low Byte FFE9 H TKDAM Touch Key Data Register Middle Byte FFEA H TKDAH Touch Key Data Register High Byte FFEB H TKMODL Amplification Factor Register FFEC H TKMODM Amplification Factor Register FFED H TKMODH Amplification factor Register FFEE H TKMODU Amplification Factor Register FFEF H I2CX16 I2C Sample Filter Register V1.0 39/138

40 Function Description Note FFF0 H I2CC I2C Control Register FFF1 H I2CSA I2C Slave Register FFF2 H I2CTB I2C Transmit Buffer Register FFF3 H I2CRB I2C Receive Buffer Register FFF4 H I2CIEC I2C Interrupt Enable Register FFF5 H I2CIFC I2C Interrupt Flag Register FFF6 H - - FFF7 H - - FFF8 H - - FFF9 H ACPC Analog Comparator Control Register FFFA H - - FFFB H VRC1 Internal Reference Voltage Control Register FFFC H - - FFFD H - - FFFE H - - FFFF H - - V1.0 40/138

41 Special Function Registers Indirect ing Data Register (IAD) FF80 H Reset Value IAD<7:0> bit7-0 R/W Indirect addressing data Indirect ing Register Low Byte (IAAL) FF81 H Reset Value IAAL<7:0> bit7-0 R/W Indirect addressing address low byte Indirect ing Register High Byte (IAAH) FF82 H Reset Value IAAH<7:0> bit7-0 R/W Indirect addressing address high byte Section Select Register (BKSR) FF83 H Reset Value BKSR<2:0> bit2-0 R/W Section select bits 000: Section 0 001: Section 1 010: Section 2 011: Section 3 100: Section 4 101: Section 5 110: Section 6 111: Section 7 - bit V1.0 41/138

42 Chapter4 I/O Ports 4. 1 Overview All I/O ports are TTL/SMT driven input and CMOS output. Each port is associated with a related register PxT for input/output control. When PxT is set, the related I/O t works in input mode, on the contrary, when PxT is cleared, the related I/O port works in output mode. All I/O ports have independent internal weak pull-up/down control registers, disabled if the enable bit is cleared, and is enabled if it is set. Internal weak pull-up/down is disabled automatically when an I/O is configured to output mode, external crystal input mode or analog input mode. Each I/O port has an independent open-drain output control register. Port A supports large current. When an I/O is configured to external oscillator input mode or analog input mode, large current and open-drain output are automatically disabled. When an I/O port is set to analog mode, the corresponding PxT should be set to input direction. For details please refer to Chapter 4.8 Special Function Registers. When an I/O port is multiplexed with other functions, the pin level is determined by the specific function. For details please refer to Chapter 1.5 Pin Descriptions Block Diagram VDD System Clock Bus Read Bus Write Bus Control Bus I/O Logic I/O Ouput I/O Control I/O Input Weak Pull-Up/ Down Open-Drain Control Drive Capability I/O MUX Analog Port VDD VDD Px.n Peripheral Enable Peripheral Output Peripheral Input Digital Input Digital/Analog Mode Select Analog Input Analog Output Figure 4-1 Input/Output Block Diagram V1.0 42/138

43 4. 3 Weak Pull-up/ Pull-down PA, PB, PC can be individually configured for weak pull-up / pull-down by software. Pin PA Y Y - Y Y Y Y Y PB Y Y Y Y Y Y Y Y PC Y Y Table 4-1 IO Ports Weak Pull-Up Pin PA Y Y - Y Y Y Y Y PB Y Y Y Y Y Y Y Y PC Y Y Table 4-2 I/O Ports Weak Pull-Down 4. 4 Drive Strength PA can be individually configured to have 2 drive strengths (normal and high) by software. The default setting is normal. Pin PA Y Y - Y Y Y Y Y PB PC Table 4-3 I/O Ports High Drive 4. 5 Open Drain Output PA, PB, PC can be individually configured for open drain output by software. Pin PA Y Y - Y Y Y Y Y PB Y Y Y Y Y Y Y Y PC Y Y Table 4-4 I/O Ports Open Drain Output 4. 6 External Key Interrupt (KIN) The device support 1 external key interrupt with up to 4 key inputs (KIN<3:0>). Each input can be masked by the corresponding INTC0<3:0>. Any change of any key input can assert the interrupt flag bit KIF. Change of input level can cause interrupt. With interrupt-on-change enabled, compare the last value of input with the latch value. If the two values do not match, the interrupt flag bit V1.0 43/138

44 will be set and this interrupt can wake up the device from idle mode. The interrupt flag KIF can be cleared by software in interrupt service routine, the steps are as follows: 1. Perform read or write operation on port registers, clear the mismatch condition between the port level and the latch value. 2. Clear interrupt flag by software. Before enabling the interrupt (KMSKx=1, KIE=1), it is necessary to read/write all the port registers and clear KIF to avoid generating unexpected interrupts. Pin Port Input Key Mask PB4 KIN0 KMSK0 PB5 KIN1 KMSK1 PB6 KIN2 KMSK2 PB7 KIN3 KMSK3 Interrupt Interrupt Interrupt Name Enable Flag KINT KIE KIF Table 4-5 External Key Interrupt 4. 7 External Port Interrupt (PINT) 2 external port interrupts are available with two input ports PINT1-0. External port interrupts are enabled by PIE1-0 (INTE0<7:6>), and the trigger edge is selected by PEG1-0 (INTC0<7:6>) as rising or falling. A generated interrupt can assert the interrupt flag PIF. Pin Port Input Trigger Interrupt Interrupt Interrupt Edge Select Name Enable Flag PC0 PINT0 PEG0 PINT0 PIE0 PIF0 PC1 PINT1 PEG1 PINT1 PIE1 PIF1 Table 4-6 External Port Interrupt V1.0 44/138

45 4. 8 Special Function Registers Reset value PA<7:0> bit7-0 R/W Port A Register (PA) FFAA H xxxx xxxx Port A voltage level 0: Low level 1: High level Port A Tristate Register (PAT) FFAB H Reset value PAT<7:0> bit0 R/W Port A input/ output mode select bit 0: Output mode 1: Input mode Reset value PB<7:0> bit7-0 R/W Port B Register (PB) FFAC H xxxx xxxx Port B voltage level 0:Low level 1:High level Port B Tristate Register (PBT) FFAD H Reset value PBT<7:0> bit7-0 R/W Port B input/ output mode select bit 0: Output mode 1: Input mode Port C Register (PC) FFAE H Reset value xxxx xxxx PC<1:0> bit1-0 R/W Port C voltage level 0:Low level 1:High level - bit V1.0 45/138

46 Port C Tristate Register (PCT) FFAF H Reset value PCT<1:0> bit1-0 R/W Port C input/ output mode select bit 0: Output mode 1: Input mode - bit Port A Pull-up Register (PAPU) FFB0 H Reset value PAPU<7:0> bit7-0 R/W Port A internal weak pull-up enable bits 0: Disabled 1: Enabled Port B Pull-up Register (PBPU) FFB1 H Reset value PBPU<7:0> bit7-0 R/W Port B internal weak pull-up enable bits 0: Disabled 1: Enabled Port C Pull-up Register (PCPU) FFB2 H Reset value PCPU<1:0> bit1-0 R/W Port C internal weak pull-up enable bits 0: Disabled 1: Enabled - bit Port A Pull-down Register (PAPD) FFB7 H Reset value PAPD<7:0> bit7-0 R/W Port A internal weak pull-down enable bits 0: Disabled 1: Enabled V1.0 46/138

47 Port B Pull-down Register (PBPD) FFB8 H Reset value PBPD<7:0> bit7-0 R/W Port B internal weak pull-down enable bits 0: Disabled 1: Enabled Port C Pull-down Register (PCPD) FFB9 H Reset value PCPD<1:0> bit1-0 R/W Port C internal weak pull-down enable bits 0: Disabled 1: Enabled - bit Port A Open Drain Output Register (PAOD) FFB4 H Reset value PAOD<7:0> bit7-0 R/W Port A open drain output enable bits 0: Disabled 1: Enabled Port B Open Drain Output Register (PBOD) FFB5 H Reset value PBOD<7:0> bit7-0 R/W Port B open drain output enable bits 0: Disabled 1: Enabled Port C Open Drain Output Register (PCOD) FFB6 H Reset value PCOD<1:0> bit1-0 R/W Port C open drain output enable bits 0: Disabled 1: Enabled - bit V1.0 47/138

48 Port A Large Current Register (PALC) FFB3 H Reset value PALC<1:0> bit1-0 R/W Port A large current bits 0: Disabled 1: Enabled - bit2 - - PALC<7:3> bit7-3 R/W Port A large current bits 0: Disabled 1: Enabled Note: For detailed descriptions on drive strength, please refer to Appendix 3 Electrical Characteristics. V1.0 48/138

49 Chapter5 Peripherals 5. 1 Timer/ Counter The HR7P201 features one 8-bit timer/ counter T8N, three 8-bit complementary enhanced PWM timers with dead zone T8P1/T8P2/T8P bit Timer/ Counter T8N Overview 8-bit timer/counter module Timer mode (Clock source: Fosc/2 or WDT RC clock) Counter mode (Clock source: external input clock T8NCKI) One 8-bit configurable prescaler (T8NPRS) One 8-bit counter register (T8N) One 8-bit control register (T8NC) Overflow interrupt flag (T8NIF) T8N does not operate in low power mode Block Diagram System Clock Bus Write Bus Read Bus Control Bus T8NCKI Bus Interface Frequency Division Controller Prescaler Mode Selector Edge Detect T8N Counter T8NIF Figure 5-1 T8N Block Diagram V1.0 49/138

50 Operating Mode Operating Mode T8NM Timer Mode 0 Synchronous Counter Mode 1 Table 5-1 T8N Operating Mode Configuration Note: T8N Operating Mode Configuration 1. When T8N is configured as a timer and prescaler is not used, T8N counter clock is clocked by 2 (Fosc/2); when prescaler is used, T8N counter is clocked by prescaled frequency of Fosc/2. 2. When T8N is configured as a counter, T8N is clocked by the external input clock T8NCKI, and T8NCKI is synchronized with the internal phase clock p2. The high voltage level or low voltage level of T8NCKI should maintain for at least one machine cycle. Counting on every rising or falling edge of the external clock is determined by T8NEG (T8NC<4>). External counter mode also supports prescaler. Additionally, the IO port associated with T8NCKI must be configured to input mode Prescaler T8N Timer Frequency T8NPRE T8NPRS<2:0> T8N_CLK 0 - T8N_CLK / T8N_CLK / T8N_CLK / T8N_CLK / T8N_CLK / T8N_CLK / T8N_CLK / T8N_CLK / Table 5-2 T8N Prescaler Configuration Note1: When T8NPRE=1, T8N prescaler is enabled. In this case, any write operation to T8N counter will clear prescaler, but will not affect prescaler ratio. The prescaler counter value is not read/write accessible. Note2: T8N is clocked by Fosc/2 in timer mode and by the external counter clock T8NCKI in counter mode Interrupt Flag When T8N counter is incremented from FF H to 00 H, T8N counter overflows and T8NIF is set. If T8NIE bit and global interrupt GIE bit are both enabled, T8N can generate an interrupt on overflow, otherwise the interrupt will not be serviced. Before re-enabling the interrupt, clear the T8NIF by software to avoid unexpected interrupts. T8N does not work when CPU enters idle mode, therefore, no interrupt will be triggered. Note: For details of T8NIE/T8NIF please refer to Chapter 6.4 Interrupt Handler. V1.0 50/138

51 Special Function Registers T8N Counter Register (T8N) FFBB H Reset Value T8N<7:0> bit7-0 R/W T8N Counter 00 H ~ FF H T8N Control Register (T8NC) FFBC H Reset Value T8NPRS<2:0> bit2-0 R/W Prescaler ratio select bits 000: 1:2 001: 1:4 010: 1:8 011: 1:16 100: 1:32 101: 1:64 110: 1: : 1:256 T8NPRE bit3 R/W Prescaler enable bit 0:Disabled 1:Enabled T8NEG bit4 R/W T8NCKI counting edge select bit 0: Rising edge 1: Falling edge T8NM bit5 R/W T8N mode select bit 0: Timer mode, clocked by Fosc/2 1: Counter mode, clocked by T8NCKI T8NCLK bit6 R/W T8N timer clocked by WDT RC clock enable bit (when T8NPRE=1) 0: Disabled 1: Enabled T8NEN bit7 R/W T8N enable bit 0: Disabled 1: Enabled V1.0 51/138

52 bit Time-based Timers (T8P1/T8P2/T8P3) Overview T8Px supports 2 operating modes: Timer mode, EPWM mode Clock source: Fosc/2 3 x 8-bit complementary EPWMs with dead zone. Programmable dead-zone delay One configurable prescaler and one configurable postscaler T8Px includes 8-bit counter (T8Px), resolution register (T8PxRL), resolution buffer register (T8PxRH) and period register(t8pxp) Programmable reload value Interrupt flag T8PxIF (having different functions in different operating modes, must be cleared by software) T8Px stops operating in low power mode EPWM auto shutdown and restart Start-of-AD conversion by EPWM edge Block Diagram T8PxIF System Clock Bus Read Bus Write Bus Control Bus Bus Interface Frequency Division Controller Prescaler T8Px Counter T8PxP Period Value Postscaler Comparator Interrupt Generator T8Px Output Figure 5-2 T8Px Block Diagram V1.0 52/138

53 Prescaler and Postscaler T8Px Match Interrupt T8PxPOS<3:0> Counter and Period Register match 1 time 0000 Counter and Period Register match 2 times 0001 Counter and Period Register match 3 times 0010 Counter and Period Register match 4 times 0011 Counter and Period Register match 5 times 0100 Counter and Period Register match 6 times 0101 Counter and Period Register match 7 times 0110 Counter and Period Register match 8 times 0111 Counter and Period Register match 9 times 1000 Counter and Period Register match 10 times 1001 Counter and Period Register match 11 times 1010 Counter and Period Register match 12 times 1011 Counter and Period Register match 13 times 1100 Counter and Period Register match 14 times 1101 Counter and Period Register match 15 times 1110 Counter and Period Register match 16 times 1111 Table 5-3 T8Px Postscaler Configuration T8Px Timer Frequency T8PxPRS<1:0> Fosc/2 00 Fosc/8 01 Fosc/32 1x Table 5-4 T8Px Prescaler Configuration Note: T8Px has one configurable prescaler and one postscaler. The counter value of prescaler and postscaler cannot be read or written. Modifications of T8PxC control register or T8Px counter will clear prescaler and postscaler Operating Mode Operating Mode T8PxM Timer Mode 0 PWM Output Mode 1 Table 5-5 T8Px Operating Mode Configuration Table Timer Mode When T8PxM=0, T8Px is configured in timer mode. T8Px Counter is clocked by Fosc/2. The prescaler can be used for timer clock division. T8Px is an incremental counter. When counter value increments to T8PxP, T8Px is cleared and restart counting. Meanwhile the postscaler is increased by 1. When the postscaler value is equal to the postscaler ratio, the postscaler is reset and the interrupt V1.0 53/138

54 flag T8PxIF is set which needs to be cleared by software. If T8PxIF is 1 and the interrupt enable bit T8PxIE and global interrupt enable bit GIE are both enabled, the T8Px interrupt will occur; otherwise, the interrupt will not be serviced. T8PxIF bit must be cleared before re-enabling the interrupt to avoid unexpected interrupts. T8Px stops working when CPU enters idle mode PWM Mode When T8PxM=1, T8Px works in PWM mode. If the corresponding PXT is configured to output mode and T8Px<1:0> is set, the Px port outputs PWM waveform. After PWM mode is enabled, the counter begins with a start cycle, then the PWM cycles are repeated. Start Cycle In the start cycle, T8Px starts counting from the reload value until the counter value equals to the value of T8PxP. At this point, the value of T8PxRL is loaded into T8PxRH, and T8PxIF is set. In start cycle, PWM output is always 1. PWM Period After the start cycle, the T8Px recounts from zero, and holds the PWM output as 1. When T8Px value is equal to T8PxRH, PWM output changes to 0, and T8Px continues to count up. The next time when T8Px counter value is equal to T8PxP, PWM output returns to 1, meanwhile, current T8PxRL value is loaded to T8PxRH, and T8PxIF interrupt flag is set. T8Px is then cleared and restart counting all over again. T8PxRH is read only in PWM output mode. Specially, if the value of T8PxRH is 0, PWM will output 0 in the current PWM cycle. If the value of T8PxRH is larger than T8PxP, PWM will output 1 in the current PWM cycle. In PWM output mode, the T8Px is clocked by Fosc/2, and the prescaler is supported. And in this mode, the postscaler setting do not affect PWM output period or duty cycle; it only affects the T8PxIF, for details please refer to Table 5-3 T8Px postscaler configuration. The waveforms of PWM output are as follows: T8PxM 1 T8Px X X+1 X+2... P 00H 01H 02H... A A+1... P 00H... T8PxP P T8PxRL A B T8PxRH A B PWM T8PxIF Start cycle Pulse width PWM period Figure 5-3 Standard PWM Mode Diagram V1.0 54/138

55 Period Pulse width T8Px =T8PxP Figure 5-4 Standard PWM Output Diagram PWM calculation formula is as follow: PWM Period = [(T8PxP)+1] 2 Tosc (T8Px prescaler value) PWM Frequency = 1/ (PWM Period) PWM Pulse Width = T8PxRL 2 Tosc (T8Px prescaler value) PWM Duty Cycle = [PWM Width] / [PWM Period] PWM Resolution: Note: Tosc = 1/Fosc, Fpwm = 1/ (PWM Period), Fckps is T8px prescaler value Enhanced PWM Mode 3 pairs of complementary EPWM outputs are available with single bridge output and half bridge output options. Single bridge output is a standard PWM output and has been introduced in PWM Mode. In half bridge output mode, 2 ports used as output drivers for push-pull load. One of the modulated signals is output to PWMx0 port, and its complementary signal is output to PWMx1 port to drive the load. A programmable dead zone delay can be inserted between the two output signals, to prevent the short connection of half-bridge power devices, which may cause irreversible damage to the half-bridge power devices. Dead-zone delay Tdelay can be determined by the system clock and dead-zone delay control register PDDxC. If the system clock frequency is fixed, dead-zone delay can be configured by PDDx<6:0>, Tdelay = 2 * Tosc * (PDDxC<6:0>). Note that, dead-zone delay Tdelay must be less than PWM work period; otherwise, PWM output will be invalid. V1.0 55/138

56 0 T8PxP+1 Work period Period PWMx0 Modulation (active high) PWMx1 Modulation (active low) Figure 5-5 EPWM Single Bridge Output Diagram 0 T8PxP+1 Work period Period Dead zone delay PWMx0 modulation PWMx0 /PWMx1both active high Dead zone delay PWMx1 modulation PWMx0 modulation Dead zone delay PWMx0 /PWMx1both active low PWMx1 modulation Dead zone delay Dead zone delay PWMx0 modulation PWMx0 active high, PWMx1 active low PWMx1 modulation Dead zone delay PWMx0 modulation PWMx0 active low, PWMx1 active high PWMx1 modulation Dead zone delay Dead zone delay Figure 5-6 EPWM Half Bridge Output Diagram V1.0 56/138

57 EPWM Auto Shutdown and Restart This chip supports 1 shutoff event, PA3/N_EPAS pin input shutoff event. When auto-shutoff bit EPWMxAS0 is enabled and PA3/N_EPAS pin input is 0, auto-shutoff event occurs. When shutoff event has occurred, EPWM output port is in shutoff state. The shutoff state can be controlled by lower 4 bits of TExAS, EWPM output ports can be set to 1 / 0 / high impedance (tristate). In shutoff state, shutoff event flag EPWMxASF (EPWMxAS<7>) is set. If shutoff event holds, the shutoff event flag cannot be cleared. In shutoff state, if EPWM restart control bit PRSENx (PDDxC<7>) is set, shutoff event flag EPWMxASF is automatically cleared by hardware to restart EPWM function after shutoff event ends. If EPWM restart control bit PRSENx (PDDxC<7>) is 0, shutoff event flag EPWMxASF should be cleared by software to restart EPWM function after shutoff event ends. After EPWM is restarted, EPWM waveform will be output normally in the next PWM cycle. Auto restart PRSENx Shutdown event EPWMxASF bit EPWM waveform EPWM cycle start point Normal operation PWM cycle Shutdown event Clear shutdown event EPWM auto restart Figure 5-7 EPWM Shutdown and Auto Restart (PRESNx=1) V1.0 57/138

58 Auto restart bit PRSENx Shutdown event EPWMxASF bit EPWM waveform EPWM cycle start point Normal operation PWM cycle Shutdown event Clear shutdown event EPWM restart Clear to 0 by software Figure 5-8 EPWM Shutdown and Restart (PRESNx=0) Note1: EPWM x C <1:0> bits can be used to select active output for each EPWM output port. To prevent damage to application circuits, changing output polarity when EPWM port is in output mode is not recommended Note2: Set the I/O associated with PWMx0/PWMx1 to output mode after EPWM module initialization is done Start-of-AD Conversion by PWM Output AD conversion can be activated by PWM output. To make sure the conversion triggered by an active edge, a configurable delay filter circuit is added after the PWM output. When ADC and PWMADEN are both set, PWMADS is configured to select the trigger edge through software-configured delay timer TMRADS. When PWMADS is 0, the counter starts counting on every rising edge of PWM. While PWMADS is 1, the counter starts counting at every falling edge of PWM. At the point that the counter value is greater than TMRADC, an AD conversion trigger signal is generated. Before the AD conversion is complete, any other trigger signals are considered invalid. The counter clock of the delay counter is the system clock. When the system enters idle mode, the AD conversion will not be activated by any edge of PWM. To enable the AD conversion by PWM output edge, the SMPS bit must be set and AD sampling mode setup must be controlled by hardware. V1.0 58/138

59 Special Function Registers T8Px Counter (T8Px) T8P1:FFBD H T8P2:FFC3 H T8P3:FFC9 H Reset Value T8Px<7:0> bit7-0 R/W T8Px Counter 00 H ~ FF H T8Px Control Registe r(t8pxc) T8P1C:FFBE H T8P2C:FFC4 H T8P3C:FFCA H Reset Value T8PxPRS<1:0> bit1-0 R/W T8PxE bit2 R/W T8PxPOS<3:0> bit6-3 R/W T8PxM bit7 R/W T8Px prescaler ratio select bits 00: 1:1 01: 1:4 1x: 1:16 T8Px enable bit 0: Disable T8P1 1: Enable T8P1 T8Px Postscaler ratio select bits 0000: 1:1 0001: 1:2 0010: 1:3 1111: 1:16 T8Px Operating mode select bit 0: Timer mode 1: PWM mode T8Px Period Register (T8PxP) T8P1P:FFBF H T8P2P:FFC5 H T8P3P:FFCB H Reset Value T8PxP<7:0> bit7-0 R/W T8Px Period Register 00 H ~ FF H V1.0 59/138

60 T8Px Resolution Register (T8PxRL) T8P1RL:FFC0 H T8P2RL:FFC6 H T8P3RL:FFCC H Reset Value T8PxRL<7:0> bit7-0 R/W 8-Bit Resolution Register 00 H ~ FF H T8Px Resolution Buffer Register (T8PxRH) T8P1RH:FFC1 H T8P2RH:FFC7 H T8P3RH:FFCD H Reset Value T8PxRH<7:0> bit7-0 R/W 8-Bit Resolution Buffer Register (cannot be written in PWM mode) 00 H ~ FF H EPWM Output Control Register (T8PxOC) T8P1OC:FFC2 H T8P2OC:FFC8 H T8P3OC:FFCE H Reset Value PWMx0EN bit0 R/W PWMx0 port enable bit 0: General purpose I/O 1: PWMx0 output PWMx1EN bit1 R/W PWMx1 port enable bit 0: General purpose I/O 1: PWMx1 output - bit EPWM Configuration Register (EPWMxC) EPWM1C:FFCF H EPWM2C:FFD0 H EPWM3C:FFD1 H Reset Value EPWMxM<1:0> bit1-0 R/W EPWM output polarity select bits 00: PWMx0 and PWMx1 both active high 01: PWMx0 active high, PWMx1 active low 10: PWMx0 active low, PWMx1 active high 11: PWMx0 and PWMx1 both active low EPWM2OS bit2 R/W PWM20, PWM21 output port select bit 0:PWM20 and PWM21 respectively output from PA6 and PB3 V1.0 60/138

61 1:PWM20 and PWM21 respectively output from PB0 and PB1 PWMxADS bit3 R/W AD Conversion trigger edge select bit 0: PWM rising edge 1: PWM falling edge - bit P1Mx bit6 R/W T8PxM=1, EPWM output port select bit 0: Single bridge output. PWMx0 and PWMx1 are 6 PWM output ports 1: Half bridge outputs. PWMx0 and PWMx1 are 3 pairs of complementary EPWM output ports with dead zone delay PWMxADEN bit7 R/W AD conversion by PWM edge enable bit 0: Disabled 1: Enabled EPWM Dead-zone Delay Control Register (PDDxC) PDD1C:FFD2 H PDD2C:FFD3 H PDD3C:FFD4 H Reset Value PDDxC<6:0> bit6-0 R/W PRSENx bit7 R/W EPWM dead zone delay counter 00 H ~ 7F H EPWM restart bit 0: After auto shutdown event ceased, the auto shutdown event flag bit must be cleared by software to restart EPWM. 1: After auto shutdown event ceased, auto shutdown event flag bit can be automatically cleared by hardware and EPWM restarts automatically. EPWM Auto Shutdown Register (TExAS) TE1AS:FFD5 H TE2AS:FFD6 H TE3AS:FFD7 H Reset Value PSSxBD<1:0> bit1-0 R/W PWMx0 and PWMx1 shutdown status bits 00: Outputs 0 01: Outputs 1 1x: Tristate - bit V1.0 61/138

62 EPWMxAS0 bit4 R/W EPWM auto shutdown bit 0 0: N_EPAS port does not affect EPWM 1: Shutdown event occurs when N_EPAS inputs 0 - Bit bit6 - - EPWMxASF bit7 R/W EPWM auto shutdown event flag bit 0: No shutdown event occurred 1: Shutdown event occurred PWM Edge Detect Delay Register (TMRADC) FFD8 H Reset Value TMRADC<7:0> bit7-0 R/W PWM edge detect delay 00 H ~ FF H V1.0 62/138

63 5. 2 Touch Key Control (TK) Overview Up to 14 touch keys Operating frequency: 4MHz, 2MHz, 1MHz and 500KHz Multiple reference voltage options Touch key scan interrupt One analog comparator ACP4 Two high-precision internal reference voltages Comparator interrupt Block Diagram Cp Cx... S1 S2 sw1 sw2 S3 CX_DISCH System Clock Divided Clock Charging Timer Calculation Result Idle Discharging Timer Calculate Discharge + ACP4 - COUT Reference Voltage VREF Filter Scan Figure 5-9 Touch Key Block Diagram Touch Key Scan Principles This device realizes a detection of capacitive sensing key, using the principle of capacitor charge transfer. In the diagram above, the switch S1 is controlled by the key select register; the switch S2 is controlled by divided system clock signal after PWM modulation; the switch S3 is controlled by the complementary signal of the divided system clock signal after PWM modulation. When a key is touched by fingers, it is equivalent to add a capacitance Cf which is connected to earth and the actual capacitance becomes Cp+Cf. Compared to the moment before touching, the charging time of the capacitor Cx will be shortened, as shown in the following touch state diagram. The touch key scan procedure depends on the charging time of the capacitor Cx. Specific operating principle is as follows: 1. Close S1 and S2 and disconnect S3 so that the system begins to charge the capacitor Cp. V1.0 63/138

64 2. Close S1 and S3 and disconnect S2 so that capacitor Cp discharges to the capacitor Cx. 3. Repeat steps 1&2 to charge the capacitor Cx. When the voltage level of capacitor Cx is greater than the reference voltage VREF at the negative terminal of comparator ACP4, the analog comparator COUT outputs high voltage level and filter begins to perform sampling and filtering. 4. After sampling and filtering process, the discharging timer outputs high voltage level and NMOS becomes conducted. At this point, S2 and S3 are disconnected and Cx begins to discharge. (In order to ensure that the discharging of the capacitor Cx is complete, the discharging time can be extended. Users can set different discharging time by software according to the capacitance of Cx.) 5. When the filter outputs low level and the capacitor Cx discharge is completed, the charging timer starts counting the charging time of the capacitor Cx, and the charging time will be used as the sampling result. Multiple sampling can be configured by software, and the hardware automatically calculates the average value of all the samplings. 6. When the filter outputs high level, the value of the charging timer is sent to the operational amplifier to increase the noise margin in the current state. At the same time, the discharging timer starts counting the discharging time of capacitor Cx. If no false start or no calculation overflows, the hardware automatically generates an end-of-calculation interrupt, and loads the 24-bit sampling value to finish one touch key scan. Filter COUT Cx charge SW1 Cp charge SW2 Cp discharge Cx discharge CX_DISCH TKEN Figure 5-10 No Touch State Diagram V1.0 64/138

65 COUT Cx charge Filer SW1 SW2 CX_DISCH Cp charge Cp discharge Cx discharge TKEN Figure 5-11 Touch State Diagram Touch Key Port When the touch key module is enabled and register TKCTR is set, unselected key ports are automatically set to digital output mode. The output mode of untouched touch keys can be set by register TKOUTS. V1.0 65/138

66 Touch Key Scan Flowchart Configure operating mode register WaitF for 10uS Configure start register N Scan TK module interrupt Interrupt occurred? Clear interrupt and start error flag Y Y Start error flag asserted? N Clear interrupt and overflow flag Y Counter overflow flag asserted? N Calculation overflow flag asserted? N Clear interrupt Read 24-bit data register Y Clear interrupt and Calculation overflow interrupt modify reference Value register End Figure 5-12 Touch Key Operation Flowchart Note1: TKERR, the touch key start error flag bit, is used to determine the suitability of the discharging time setting and the capacitance of Cx. Note2: A 28-bit amplification factor is used to amplify the difference between the values of touched and untouched. If the higher bits are non-zero (not readable by customers), there will be a calculation overflow and the overflow flag bit TKOV will be set. If there is indeed a calculation overflow, indicating that the operational result of 24 bits is greater than ffffff H, then the 28-bit amplification factor should be reduced accordingly. Note3: If TK scan overflows, the flag bit SCANOV will be asserted and this can be avoided by reducing the operating frequency through TKFS<1:0>. V1.0 66/138

67 Analog Comparator ACP4 The positive input of the comparator 4 is shared with PB7 and the negative input can be configured by software to connect with the internal or external reference voltage. Note that when using analog comparator, TKCTL<1> (TKEN) register should be enabled Internal Reference Voltage VREF module can be enabled by the enable bit VREFEN (VRC1<7>). VREF voltage can be calibrated to 2.5V by calibration register bits VREFCAL<2:0>, and can be configured to output to an IO port. VREF is factory calibrated to 2.5V within accuracy±2% at 25. Two reference voltages VREF1 and VREF2 are available and can be individually configured to output a voltage in the range 0.6V~2.5V. Note1: Under some adverse conditions, to make sure of the touch key sensitivity, it is suggested not to share the touch key input with ADC analog input. Note2: TK0 and TK1 have lower SNR compared with other channels. Thus, it is not suggested to use them as TK channels under some adverse conditions. V1.0 67/138

68 Special Function Registers Touch Key Selection Register(TKSEL) FFE5 H Reset Value TKCHS<3:0> bit3-0 R/W 14 Touch Key Channels (TK0~TK13) select bits 0000: Select TK0 0001: Select TK1 0010: Select TK2 0011: Select TK3 0100: Select TK4 0101: Select TK5 0110: Select TK6 0111: Select TK7 1000: Select TK8 1001: Select TK9 1010: Select TK : Select TK : Select TK : Select TK ~1111: Channel selection masked TKFS<1:0> bit5-4 R/W Operating frequency select bits (The higher the operating frequency, the more effective the touch key scan. 4MHz is recommended.) 00: fosc/4 01: fosc/8 10: fosc/16 11: fosc/32 TKDUS bit6 R/W Analog charge/discharge duty cycle select bit 0: Charge/discharge duty cycle 1:4 1: Charge/discharge duty cycle 1:2 TKCTR bit7 R/W TK module untouched keys KIN0~KIN6 output enable bit 0: Disabled 1: Enabled Note: For output enable bit of KIN7~KIN13 untouched keys, refer to the configuration word. V1.0 68/138

69 Touch Key Tune Register (TKTUN) FFE6 H Reset Value TKOUTS<1:0> bit1-0 R/W TK switch level output control bits 00: Untouched key outputs low level 01: Untouched key outputs high level 10: Untouched key outputs SW1 signal 11: Untouched key outputs inverted SW1 signal TKDIST<1:0> bit3-2 R/W Cx discharge time select bits 00: 32 * Tosc; 01: 160* Tosc; 10: 288 * Tosc; 11: 416 * Tosc; TKCFT<1:0> bit5-4 R/W Comparator output filtering time select bits 00: No filtering 01: 2 * Tosc 10: 4 * Tosc 11: 8 * Tosc TKTMS<1:0> bit7-6 R/W The number of sampling times select bits 00: Sample once, the result is the average value of the one sampling 01: Sample 4 times, the result is the average value of 4 samplings 10: Sample 8 times, the result is the average value of 8 samplings 11: Sample16 times, the result is the average value of 16 samplings V1.0 69/138

70 Touch Key Control Register(TKCTL) FFE7 H Reset Value TKGO bit0 R/W Touch key scan start go bit (set by software and auto cleared by hardware. Software clearing will force the current scan to stop ) 0: No scan started 1: Touch key scan in progress TKEN bit1 R/W Touch key enable bit 0: Disabled 1: Enabled TKOV bit2 R Calculation result overflow flag bit 0:No overflow 1:Overflow occurred TKERR bit3 R Scan start error flag bit 0:No scan start error 1:Scan start error occurred SCANOV bit4 R Scan counter overflow flag bit 0:No overflow 1:Overflow occurred - bit7-5 R/W - Touch Key Data Register Low Byte (TKDAL) FFE8 H Reset Value TKDAL<7:0> bit7-0 R Low byte of scan result register Touch Key Data Register Middle Byte (TKDAM) FFE9 H Reset Value TKDAM<7:0> bit7-0 R Middle byte of scan result register Touch Key Data Register High Byte (TKDAH) FFEA H Reset Value TKDAH<7:0> bit7-0 R High byte of scan result register V1.0 70/138

71 Amplification Factor Register (TKMODL) FFEB H Reset Value TKMODL<7:0> bit7-0 R/W Low byte of amplification factor Amplification Factor Register (TKMODM) FFEC H Reset Value TKMODM<7:0> bit7-0 R/W Middle byte of amplification factor Amplification Factor Register (TKMODH) FFED H Reset Value TKMODH<7:0> bit7-0 R/W High byte of amplification factor Amplification Factor Register (TKMODU) FFEE H Reset Value TKMODU<3:0> bit3-0 R/W Upper 4 bits of amplification factor - bit Analog Comparator Control Register (ACPC4) FFF9 H Reset Value C4EN bit0 R/W Comparator enable bit 0: Disabled 1: Enabled C4INV bit1 R/W Comparator output polarity invert bit 0: Non-inverted output 1: Inverted output - bit C4NM<1:0> bit5-4 R/W Comparator negative input select bits 00: External VREF 01: Internal VREF1 10: Internal VREF2 11: External VREF C4OUT bit6 R Comparator output status bit 0: CINN > CINP V1.0 71/138

72 - bit : CINN < CINP Internal Reference Voltage Control Register 1(VRC1) FFFB H Reset Value VOUTEN bit0 R/W Internal Reference Voltage VREF 2.5V output to PB7 enable bit 0: Disabled 1: Enabled VRC1S<2:0> bit3-1 R/W Internal Reference Voltage VREF1 select bits 000: 0.6V 001: 1.4V 010: 1.5V 011: 2.0V 100: 2.1V 101: 2.2V 110: 2.4V 111: 2.5V VRC2S<2:0> bit6-4 - Internal Reference Voltage VREF2 select bits 000: 0.6V 001: 1.4V 010: 1.5V 011: 2.0V 100: 2.1V 101: 2.2V 110: 2.4V 111: 2.5V VREFEN bit7 R/W VREF and ADCVREF 2.5V reference voltage module enable bit 0: Disabled 1: Enabled Note1: When VREF2.5 and ADVREF2.5 are used, VREFEN must be enabled. Note2: When configuring TK, VOUTEN must be cleared and VREFEN be set. V1.0 72/138

73 VBG Calibration Control Register(VREFCAL) FFA2 H Reset Value Reference voltage module VREF 2.5V calibration bits VR2D6CAL <4:0> 00000:Minimum Bit7 R/W Bit :Typical 11111:Maximum AD2D6CAL <2:0> Bit6-4 R/W ADCVREF 2.5V reference voltage calibration bits 000:Minimum :Typical value :Maximum Note: The reference voltage 2.5V has been calibrated at 25 within accuracy ±2% before leaving factory. PPG Control Register(PPGC) FFFC H Reset Value Bit3-0 R/W fixed to 0 CMXOFFSET<3:0> Bit7-4 R/W Comparator offset voltage 0000:(recommended) Note: When operating with PPGC Register, PPGC<3:0> is recommended to set to all 0s. V1.0 73/138

74 5. 3 Universal Asynchronous Receiver Transmitter (UART) Overview Asynchronous receiver and asynchronous transmitter 8/9-bit data length Full duplex mode s Supports both high-speed mode and low-speed mode with configurable transmission baud rate Receive interrupt flag Transmit interrupt flag Compatible with RS-232/ RS-442/RS Block Diagram System Clock Bus Data Read Bus Data Write Bus Control Bus TXIF RXIF Bus Interface TXB Transmit Shift Register TX TXC BRR RXC RXB Baud Rate Generator Receive Shift Register Receive Buffer Register UART RX Figure 5-13 UART Block Diagram Baud Rate Configuration Baud Rate Calculation Formula BRGH Low-speed mode Fosc/(64x(BRR<7:0>+1)) 0 High-speed mode Fosc/(16x(BRR<7:0>+1)) 1 Table 5-6 UART Baud Rate Configuration Data Format Frame TX/RX Start RXB0 TXB0 RXB1 TXB1 RXB2 TXB2 RXB3 TXB3 RXB4 TXB4 RXB5 TXB5 RXB6 TXB6 RXB7 TXB7 RXB8 TXB8 Stop Data code Figure 5-14 UART Data Format Diagram Asynchronous Transmitter A transmission is initiated by writing the data to the TXB register and the TXR8. A start bit and a stop bit are internally generated. The asynchronous transmitter can also implement a continuous data transmission. It is worth mentioning that users need to first poll the TRMT flag bit to check if the transmit shift register is empty. Only when the V1.0 74/138

75 transmit shift register is empty can the data be transmitted. Set the associated I/O ports to output mode before using them. Start Initialize I/O Set baud rate 9 Bits? Y Modify TXR8 N 8/9 bit data length Modify TXB Enable transmitter N Complete? TXB empty? Y N Y Disable transmitter End Figure 5-15 UART Asynchronous Transmission Flowchart Asynchronous Receiver The received data can be obtained by reading the RXB register and the RXR8. The receive interrupt flag bit RXIF can be polled to determine whether the received data frame is complete. A 2-level 9-bit FIFO is used as a buffer on the receiver. If the RXB has not been read prior to the completion of receiving the 3 rd data, the overrun error flag bit OERR will be set. The framing error FERR will be set if the stop bit has not been received. Set the associated I/O ports to input mode before using them. Start Initialize IO Set asynchronous mode Set baud rate 9 bits? Y Read RXR8 Read RXB N 8/9-bit data length Receive error? Y Enable receiver N N Complete? RXIF=1? Y N Y Disable receiver End Figure 5-16 UART Asynchronous Reception Flowchart V1.0 75/138

76 Special Function Registers Receive Buffer Register (RXB) FFE0 H Reset Value RXB<7:0> bit7-0 R Receive Buffer Register 00 H ~ FF H Receive Control Register (RXC) FFE1 H Reset Value x RXR8 bit0 R 9 th bit of received data 0: The 9 th bit is 0 1: The 9 th bit is 1 FERR bit1 R Framing error flag bit 0: No framing error 1: Framing error occurred (can be updated by reading RXR) OERR bit2 R Receive overrun flag bit 0: No overrun error 1: Overrun error occurred (can be cleared by clearing RXEN) - bit RXM bit6 R/W Receive data format select bit 0: 8-bit data format 1: 9-bit data format RXEN bit7 R/W Receiver enable bit 0: Disabled 1: Enabled Transmit Buffer Register (TXB) FFE2 H Reset Value TXB<7:0> bit7-0 R/W Transmit Buffer Register 00 H ~ FF H V1.0 76/138

77 Transmit Control Register(TXC) FFE3 H Reset Value TXR8 bit0 R/W 9 th bit of transmit data 0:The 9 th bit is 0 1:The 9 th bit is 1 TRMT bit1 R Transmit shift register (TXR) empty flag bit 0:TXR not empty 1:TXR empty - bit BRGH bit5 R/W Baud rate mode select bit 0:Low-speed mode 1:High-speed mode TXM bit6 R/W Transmit data format select bit 0:8-bit data format 1:9-bit data format TXEN bit7 R/W Transmitter enable bit 0:Disabled 1:Enabled Baud Rate Register (BRR) FFE4 H Reset Value BRR bit7-0 R/W UART Baud rate configuration 00 H ~ FF H V1.0 77/138

78 5. 4 I2C Slave Overview Slave Mode Only - 7-bit slave address - Standard I2C bus protocol, up to 400Kbit/s - SCL/SDA open-drain or push-pull output - 2-level transmit/ receive buffer - Auto clock stretching - Auto NACK transmission - Data order with MSB first I2C Function Registers - 5-bit I2C sampling filter register (I2CX16) - I2C control register (I2CC) - Slave address register (I2CSA) - Transmit buffer register (I2CTB) - Receive buffer register (I2CRB) - Interrupt enable register (I2CIEC) - Interrupt flag register (I2CIFC) Interrupt and halt - Receive START + Matched Slave + Transmit ACK interrupt flag (I2CSRIF) - Receive STOP interrupt flag (I2CSPIF) - Transmit buffer empty interrupt flag (I2CTBIF,read-only) - Receive buffer full interrupt flag (I2CRBIF, read-only) - Transmit error flag (I2CTEIF) - Receive overrun interrupt flag (I2CROIF) - Receive NACK interrupt flag (I2CNAIF) - In idle mode, transmission and reception are suspended I2C Port Configuration I2CS Clock Port I2CTE I2CS Data Port Configuration Configuration 1 SCL SDA 0 PC1 PC0 V1.0 78/138

79 Communication Protocol Master Slave Master Slave START Slave + write ACK Data byte 1 ACK Data byte 2 ACK STOP START Slave + read ACK Data byte 1 ACK Data byte 2 ACK STOP Figure 5-17 I2C Bus Communication Protocol The following protocol must be strictly observed in I2C communication. 1. A master device initiates the communication, sending a start bit to control the bus and a stop bit to release the bus. 2. The bus supports multimaster capability (prior to that, each master must support multimaster arbitration mechanism) and at least 1 slave device. Each slave device must have an independent and unique address. 3. The master sends a start bit, followed by the slave address and the read/write bit 4. Read/write bit R/#W (also called direction bit) is to notify the slave device the direction of the data. 0 indicates the master device is writing data to the slave device while 1 indicates the master device is reading data from the slave device. 5. I2C communication protocol supports the acknowledge mechanism. A receiver must respond with an ACK signal or NACK signal, thereby, the transmitter will act accordingly. 6. If the SCL of both master and slave devices are open drain and the master supports SCL stretching, the slave can stretch the SCL when it is at low level, allowing the master to wait for the slave until the slave releases the SCL. 7. The MSB is sent first Data Transfer Format S SLAVE ADDRESS #W ACK Memory ACK DATA0 ACK Call 7-bit slave address Set memory address Write data 0 DATA1 Write data 1 ACK DATAn Write data n ACK (NACK) P Master Reception Master Transmission Figure 5-18 Master Device Writing to Slave Device V1.0 79/138

80 S SLAVE ADDRESS #W ACK Memory ACK Call 7-bit slave address Set memory address R-S SLAVE ADDRESS R ACK DATA0 ACK Call 7-bit slave address Read data 0 DATA1 Read data 1 ACK DATAn Read data n NACK P Master Reception Master Transmission Figure 5-19 Master Device Reading from Slave Device Interrupt and Halt If any interrupt flag bit I2CSRIF / I2CSPIF / I2CTBIF / I2CRBIF / I2CTEIF / I2CROIF / I2CNAIF is asserted, I2C interrupt flag I2CIF (INTF2<6>) will be set and must be cleared by software. The related interrupt flag, such as I2CSRIF / I2CSPIF / I2CTEIF / I2CROIF / I2CNAIF, must be cleared before clearing I2CIF interrupt flag. If the I2C interrupt enable bit I2CIE (INTE2<6>) and global interrupt enable bit GIE (INTG<7>) are both set, the I2C interrupt will occur; otherwise, the interrupt will not be serviced. I2CS communication is halted in idle mode. Note: For details of GIE/ I2CIE/I2CIF, please refer to 6.4 Interrupt Handler. V1.0 80/138

81 Special Function Registers I2C Sampling Filter Register (I2CX16) FFEF H Reset Value 0000_0000 I2CX16<4:0> bit4-0 R/W Sampling filter control bits 00 H :Disable sampling filter 01 H ~1F H :communication clock and data sampling filter time is T osc x(i2cx16+1)x3 - bit I2C Control Register (I2CC) FFF0 H Reset Value 0000_0000 I2CEN bit0 R/W I2C module enable bit 0:Disabled 1:Enabled I2CRST bit1 R/W I2C module reset by software enable bit 0:Disabled 1:Enabled (cleared by hardware automatically after reset) I2CCSE bit2 R/W I2C clock stretching enable bit 0:Disabled 1:Enabled I2CANAE bit3 R/W I2C auto NACK enable bit 0:Disabled 1:Enabled I2CTAS bit4 R/W I2C transmit ACK/NACK select bit 0: Transmit ACK 1: Transmit NACK I2COD bit5 R/W I2C open-drain output enable bit 0: Push-pull output 1: Open-drain output I2CPU bit6 R/W I2C internal weak pull-up enable bit (When I2CTE=1, I2CPU is used to control SCL/SDA weak pull-up) 0:Disabled 1:Enabled I2CTE bit7 R/W I2C communication port enable bit 0:Disabled 1:Enabled V1.0 81/138

82 Note1: When I2C clock stretching is enabled: When an external master device sends the slave address + R and 2-level transmit buffer is empty before transmitting data, the slave device will hold the clock line low before sending the ACK under I2CANAN disabled condition. If 2-level transmit buffers are empty after transmitting data, the slave device will hold the clock line low after receiving the ACK When the external master device sends the slave address + #W and 2-level receive buffers is full before receiving data under I2CANAE=0 condition, the slave device will hold the clock line low before sending the ACK. If 2-level receive buffer is full after receiving data, the slave device will hold the clock line low before sending the ACK. Note2: When I2C auto NACK is enabled When an external master device sends the slave address + R and 2-level transmit buffer is empty, the acknowledge bit after the slave device address is NACK. When the external master device sends the slave address + #W and 2-level receive buffer is full before receiving data, the acknowledge bit after the slave device address is NACK. If 2-level receive buffer is full after receiving data under I2CCSE=0 condition, the acknowledge bit after received data is NACK. Note2: When I2CTE=1, I2CPU bit is used for SCL/SDA port weak pull-up control. Otherwise, PC port weak pull-up is controlled by PCPU<1:0> bits. I2C Register (I2CSA) FFF1 H Reset Value 0000_0000 I2CRW bit0 R Read / Write bit automatically updated after matched slave address 0: Write 1: Read I2CSADR<6:0> bit7-1 R/W Slave Used to compare and match after receiving start/restart signal I2C Transmit Buffer Register (I2CTB) FFF2 H Reset Value 0000_0000 I2CTB<7:0> bit7-0 R/W Transmit Buffer Note: Write the first data into transmit buffer before the transmitter is enabled. I2C Receive Buffer Register (I2CRB) FFF3 H Reset Value 0000_0000 I2CRB<7:0> bit7-0 R Receive Buffer V1.0 82/138

83 I2C Interrupt Enable Register (I2CIEC) FFF4 H Reset Value 0000_0000 I2CSRIE bit0 R/W I2C Receive START+ Matched Slave + Transmit ACK interrupt enable bit 0: Disabled 1: Enabled I2CSPIE bit1 R/W I2C receive STOP interrupt enable bit 0: Disabled 1: Enabled I2CTBIE bit2 R/W I2C transmit buffer empty interrupt enable bit 0: Disabled 1: Enabled I2CRBIE bit3 R/W I2C receive full interrupt enable bit 0: Disabled 1: Enabled I2CTEIE bit4 R/W I2C transmit error interrupt enable bit 0: Disabled 1: Enabled I2CROIE bit5 R/W I2C receive overrun interrupt enable bit 0: Disabled 1: Enabled I2CNAIE bit6 R/W I2C receive NACK interrupt enable bit 0:Disabled 1:Enabled - bit7 - - V1.0 83/138

84 I2C Interrupt Flag Registe r(i2cifc) FFF5 H Reset Value I2CSRIF bit0 R/W I2C receive START + Matched Slave + Transmit ACK interrupt flag bit 0: Not received 1: Received, should be cleared by software. I2CSPIF bit1 R/W I2C receive Stop bit interrupt flag bit 0:Not received 1:Received, should be cleared by software I2CTBIF bit2 R I2C transmit buffer empty interrupt flag bit 0:2-level transmit buffer full 1:2-level transmit buffer empty I2CRBIF bit3 R I2C receive buffer full interrupt flag bit 0: 2-level receive buffer not full 1: 2-level receive buffer full I2CTEIF bit4 R/W I2C transmit error interrupt flag bit 0: Master reads normally from slave 1: Master continues to read from slave while 2-level transmit buffer is empty (cleared by software) I2CROIF bit5 R/W I2C receive overrun interrupt flag bit 0: No overrun 1: Overrun occurred (cleared by software) I2CNAIF bit6 R/W I2C NACK interrupt flag bit 0:No NACK received/transmitted 1:NACK received/transmitted, should be cleared by software - bit7 - - Note1: Clear the corresponding interrupt flag in I2CIFC first before clearing I2CIF. Note2: A receive overrun will occur if more than 2 data are received continuously, and the 3 rd data will be lost. Note3: Once the STOP is received after every data frame transmission, the transmit buffer register will be automatically cleared by hardware. V1.0 84/138

85 5. 5 Analog-to-Digital Converter ADC Overview 12-bit resolution 14 analog input channels Data alignment: right-aligned or left-aligned Configurable reference voltages, external or internal reference voltage ADCVREF Configurable AD conversion clock Automatic control of AD sampling time Block Diagram System Clock Bus Read Bus Write Bus Control Bus ADIF Bus Interface ADCRH/ADCRL Converter Clock Selector ADC Control Reigster ADC ADC Channel Select ADVREF AIN0 AIN1 AIN2 AIN3 AIN6 AIN7 AIN8 AIN13 Figure 5-20 ADC Block Diagram AD Channel Selection Analog Input Port ADCHS AIN AIN AIN AIN AIN AIN AIN AIN AIN AIN AIN AIN AIN AIN ADCVREF 1110 Reserved 1111 Table 5-7 AD Channel Configuration V1.0 85/138

86 Note1: Before configuring AD input channels, the AINx port must be configured to analog port; Note2. Internal ADC reference voltage output is 2.5V (ADCVREF) AD Conversion Timing ADEN ADC_RST Tog* 13Tadclk ADC_CVNT ADTRG ADIF ADCR Sampling time Raw data Figure 5-21 ADC Conversion Timing (SMPS=1) New data Cleared by software Note1: Tog>0; Note2: The AD conversion clock period Tadclk is configurable through ADCKS register Reference Example Application Example: AD conversion in AIN0) BCC ANS,0 ; AIN0 is configured to analog mode BCC ADCCH, ADFM ; Converted result in left alignment MOVI 0X01 MOVA ADCCL ; Enable AD converter, select channel 0 BSS ADCCL, SMPS ; Control sampling mode by hardware AD_WAIT JBC ADCCL, ADTRG ; Wait for A/D conversion to complete GOTO AD_WAIT MOV ADCRH, 0 ; Read high byte of converted result MOV ADCRL, 0 ; Read lower 4 bits of converted result V1.0 86/138

87 Special Function Registers ADC Parameter Register (ADCTST) FFD9 H Reset Value AINEN bit0 R/W Analog input enable bit 0: Disabled 1: Enabled (input voltage is within 0.2V ~ VDD-0.2V) ADHSEN bit1 R/W AD Conversion high speed enable bit 0: Disabled, low speed ( AD Conversion clock frequency is less than 2MHz) 1: Enabled, high speed - bit Note1: When low speed conversion is selected (ADHSEN=0), Tadclk clock frequency should be less than 2MHz. Note2: When high speed conversion is selected (ADHSEN=1), VDD should be greater than 4V. Note3: For other parameters please refer to Appendix 3.1 Electrical Characteristics. ADC Result Register Low Byte (ADCRL) FFDA H Reset Value xxxx xxxx ADCRL<7:0> bit7-0 R/W Low byte / lower 4-bits of conversion result ADC Result Register High Byte (ADCRH) FFDB H Reset Value xxxx xxxx ADCRH<7:0> bit7-0 R/W Higher 4 bits/ high byte of conversion result ADC Control Register Low Byte (ADCCL) FFDC H Reset Value ADEN bit0 R/W A/D conversion enable bit 0: Disabled 1: Enabled ADTRG bit1 R/W A/D conversion status bit 0:A/D conversion completed/not in progress 1:A/D conversion in progress, set to 1 to start A/D conversion SMPS Bit2 R/W This bit needs to be set to 1 ADVOUT Bit3 R/W A/D reference voltage output control bit 0:Disable ADV 2.5V output from PB4 Port V1.0 87/138

88 ADCHS<3:0> bit7-4 R/W 1:Enable ADV 2.5V output from PB4 Port A/D Analog Channel select bits 0000:Channel 0 (AIN0) 0001:Channel 1 (AIN1) 0010:Channel 2 (AIN2) 0011:Channel 3 (AIN3) 0100:Channel 4 (AIN4) 0101:Channel 5 (AIN5) 0110:Channel 6 (AIN6) 0111:Channel 7 (AIN7) 1000:Channel 8 (AIN8) 1001:Channel 9 (AIN9) 1010:Channel 10 (AIN10) 1011:Channel 11 (AIN11) 1100:Channel 12 (AIN12) 1101:Channel 13 (AIN13) 1110:Channel 14 (ADCVREF) 1111: Mask channel selection Note: If AD sampling time is controlled by software, users need to set proper AD sampling time according to the actual application circuit. Otherwise, it may cause error in AD conversion. Using software to control the sampling time is not recommended. V1.0 88/138

89 ADC Control Register High Byte (ADCCH) FFDD H Reset Value ADVREFS<1:0> bit1-0 R/W Voltage reference select bits 00: Reference voltage positive input :VDD, negative input: VSS 01: Reference voltage positive input: internal ADCVREF, negative input: VSS. (VRC1<7>(VREFEN) must be set) 10: Reference voltage positive input: external VREFP, negative input: VSS 11: Reference voltage positive input: external VREFP, negative input: external VREFN ADST<1:0> bit3-2 R/W A/D sampling time select bits (with one instruction cycle deviation) 00: About 2 Tadclk 01: About 4 Tadclk 10: About 8 Tadclk 11: About 16 Tadclk ADCKS<2:0> bit6-4 R/W A/D conversion clock frequency (Tadclk) select bits 000: Fosc 001: Fosc/2 010: Fosc/4 011: Fosc/8 100: Fosc/16 101: Fosc/32 110: Fosc/64 111: WDT_RC ADFM bit7 R/W A/D conversion result format select bit 0: Left alignment (ADCRH<7:0>, ADCRL<7:4>) 1: Right alignment (ADCRH<3:0>, ADCRL<7:0>) Note: When AD conversion is in progress, switching the AD conversion clock may cause error in the first converted result after switching. V1.0 89/138

90 Analog Select Register Low Byte (ANSL) FFDE H Reset Value ANSL<6:0> bit6-0 R/W Analog mode select bit 0:AIN0~AIN6 are analog inputs 1:AIN0~AIN6 are digital inputs - bit7 - - Analog Select Register High Byte (ANSH) FFDF H Reset Value ANSH<6:0> bit6-0 R/W Analog mode select bit 0:AIN7~AIN13 are analog inputs 1:AIN7~AIN13 are digital inputs - bit7 - - Internal Reference Voltage Control Register 1 (VRC1) FFFB H Reset Value VOUTEN bit0 R/W Internal reference voltage VREF 2.5V output to PB7 enable bit 0:Disabled 1:Enabled - bit VREFEN bit7 R/W VREF and ADCVREF 2.5V reference voltage module enable bit 0:Disabled 1:Enabled Note: When using VREF2.5 and ADVREF2.5, VREFEN must be enabled. V1.0 90/138

91 Chapter6 Special Functions and Operations 6. 1 System Clock and Oscillator Overview The HR7P201 provides two system clock sources: external oscillator (HS and XT mode) and internal 16MHz RC oscillator (INTOSC and INTOSCIO mode). The specific clock source and the corresponding mode can be selected via OSCS <2:0> of the configuration word. OSCS<2:0> OSC2 OSC1 External oscillator 16MHz Internal 16MHZ RC Clock 8MHz 4MHz 2MHz 1MHz Clock Selector Fosc Internal WDT RC Clock Internal Osaillator Figure 6-1 System Clock Block Diagram Crystal/ Ceramic Resonator Modes (HS/XT Mode) When chip configure word OSCS<2:0>=000, HS mode is selected; when OSCS<2:0>=001, XT mode is selected. OSC1/CLKI To Internal Logic C1 Rf Enable C2 R S OSC2/CLKO Figure 6-2 Crystal / Ceramic Resonator mode (HS/XT mode) Note: R S is optional. V1.0 91/138

92 OSC Type XT HS OSC Frequency C1* C2* 1MHz 4MHz 15 ~ 33pF 15 ~ 33pF 8MHz 16MHz 15pF 15pF Table 6-1 Crystal Oscillator Capacitor Parameter Note: These values can be slightly adjusted depending on the OSC frequency and peripheral circuit Internal Clock (INTOSC and INTOSCIO Mode) In INTOSCIO mode, PA0 and PA1 are used as general purpose I/Os. In INTOSC mode, PA0 is used to output CLKO which is Fosc/16. And PA1 is used as general purpose I/O. The factory calibration accuracy is 25, VDD = 3.3V ~ 5.5V. V1.0 92/138

93 Special Function Registers Internal 16MHz Clock Calibration Register Low Byte (OSCCALL) FFA4 H Reset Value OSCCALL<7:0> bit7-0 R/W Internal 16MHz clock calibration low byte : Minimum : Maximum Internal 16MHz Clock Calibration Register High Byte (OSCCALH) FFA5 H Reset Value OSCCALH<1:0> bit1-0 R/W Internal 16MHz clock calibration higher 2 bits 00: Minimum 11: Maximum - bit V1.0 93/138

94 6. 2 Watchdog Timer (WDT) Overview When the WDT enable bit WDTEN=1, WDT is enabled. Otherwise, WDT is disabled. This can be done through programming interface. When WDT overflow occurs, the device is reset or wakes up from idle mode. The WDT counter can be cleared by CWDT instruction. WDT supports one prescaler for frequency division on WDT input clock and the prescaled clock source is used as the counter clock for WDT timer. When the prescaler is disabled, internal WDT clock is used with the clock frequency 32KHz and WDT overflow time 8ms at Block Diagram Internal WDT Clock System Clock Bus Read Bus Write Bus Control Bus Control Word Bus Interface Watchdog Timer Prescaler Frequency Division Controller WDT WDT Overflow Reset Figure 6-3 WDT Block Diagram V1.0 94/138

95 Special Function Registers WDT Clock Calibration Control Register (WDTCAL) FFA3 H Reset Value VREFBGCAL<2:0> bit2-0 R/W VREF2.5V calibration register (reserved, write operation not allowed) WDTCAL<7:3> bit7-3 R/W WDT 32KHz Clock calibration register : Maximum : Minimum Note: Register WDTCAL<7:0> has been well calibrated before leaving factory, and it is used to calibrate the ADC internal reference voltage 2.5V and WDT 32KHZ clock. Users are not allowed to modify this register because it would lead to irregular behavior of other corresponding functional modules. WDT Control Register (WDTC) FFA7 H Reset Value WDTPRS<2:0> bit2-0 R/W WDT prescaler ratio select bits 000: 1:2 001: 1:4 010: 1:8 011: 1:16 100: 1:32 101: 1:64 110: 1: : 1:256 WDTPRE bit3 R/W WDT prescaler enable bit 0: Disabled 1: Enabled - bit V1.0 95/138

96 6. 3 Reset Module Overview Power-On Reset (POR) Brown-Out Reset (BOR) External N_MRST Reset (active low) WDT Overflow Reset RST Instruction Software Reset Fosc PWRTEB BOREN N_MRST WDT_RST Instruction RST Brown-Out Detection Power-On Detection BOR POR POR/BOR Filter Timer 72ms POR_BOR Power up Timer Crystal Start up Timer POR_BOR_RST System Reset RESET Reset Timing Diagram Figure 6-4 Reset Block Diagram VDD Operating Voltage 0V T filter RESET 72ms Crystal settling time Figure 6-5 POR Timing Diagram Operating Voltage VDD BOR Preset Voltage 0V T filter RESET 72ms Crystal settling time Figure 6-6 BOR Timing Diagram Note1: 72ms settling time can be masked by PWRTEB Note2: T filter time is about 220us Note3: The crystal start up time is 1024x system clock cycles. V1.0 96/138

97 N_MRST Reset Reference Circuit VDD D1 DIODE R1 R2 N_MRST Pin C1 Figure 6-7 N_MRST Reset Reference Circuit 1 Note: In RC reset, 47KΩ R1 100KΩ, C1=0.1μF, and R2 is a current limiting resistor, 0.1KΩ R2 1KΩ. VDD VDD R1 Q1 PNP R4 N_MRST Pin R2 R3 C1 Figure 6-8 N_MRST Reset Reference Circuit 2 Note: In PNP transistor reset circuit, the voltage divided by R1 (2KΩ) and R2 (10KΩ) is used as a base input; the emitter is connected to VDD. One end of the collector is connected to ground through R3 (20KΩ), the other is connected to ground through R4 (1KΩ) and C1 (0.1μF). The ungrounded end of C1 is used as an input to N_MRST pin. V1.0 97/138

98 Special Function Registers Power Control Register (PWRC) FFA6 H Reset Value N_BOR bit0 R/W BOR status bit 0: BOR reset occurred(must be set to 1 by software after BOR reset) 1: No BOR reset occurred N_POR bit1 R/W POR status bit 0: POR reset occurred (Must be set to 1 by software after POR reset ) 1: No POR reset occurred N_PD bit2 R Low power consumption flag bit 0:Cleared after executing idle instruction 1:Set after POR or executing CWDT instruction N_TO bit3 R WDT overflow flag bit 0:Cleared after watchdog overflow 1:Set after POR or executing CWDT and idle instruction N_RSTI bit4 R/W Reset instruction flag bit 0:Reset instruction executed (Must be set by software) 1:Reset instruction not executed VRST<1:0> bit6-5 R/W LDO settling time select bits (default value 11 recommended.) 11:About 64 WDT_RC clock cycles LPM bit7 R/W Idle mode select bit 0:Idle0 mode 1:Idle1 mode Note: LDO is the built-in power supply module for the internal circuits. Power Enable Register (PWEN) FFA9 H Reset Value SREN bit0 R/W Brown-out reset software enable bit (set by software) RCEN bit1 R/W WDT internal RC clock enable bit 0: Disable WDT internal RC clock (prohibited) 1: Enable WDT internal RC clock - bit Note: When erasing or writing to Flash data, RCEN must be cleared to disable WDT module. Under any other circumstances, RCEN must be enabled. V1.0 98/138

99 6. 4 Interrupt Handler Overview This chip supports total of 4 interrupt sources and two interrupt modes, which are default interrupt mode and vectored interrupt mode selected by the register INTVEN0. System Clock Bus Read Bus Write Bus Control Bus Peripheral Interrupt Flag Bus Interface Software Interrupt Interrupt Controller Interrupt Enable Logic Interrupt Arbitration Logic Interrupt Handler Interrupt Request(CPU) Figure 6-9 Interrupt Control Logic Interrupt Mode Configuration {INTVEN0,INTVEN1} Interrupt mode Default interrupt mode Vectored interrupt mode Table 6-2 Interrupt Mode Configuration Note: INTG control register INTVEN0 and configuration word INTVEN1 bit must be set at the same time to enable the vectored interrupt mode. V1.0 99/138

100 Interrupt Logic Table No. Global Interrupt Interrupt Interrupt Interrupt Interrupt Name Flag Mask Enable Enable Note 1 Software Interrupt SOFTIF - - GIE - KMSK0 2 KINT KIF KMSK1 KMSK2 KMSK3 KIE GIE - 3 PINT0 PIF0 - PIE0 GIE - 4 PINT1 PIF1 - PIE1 GIE 5 T8NINT T8NIF - T8NIE GIE - 6 T8P1INT T8P1IF - T8P1IE GIE - 7 T8P2INT T8P2IF - T8P2IE GIE - 8 T8P3INT T8P3IF - T8P3IE GIE - 9 ACP4INT ACP4IF - ACP4IE GIE - 10 ADINT ADIF - ADIE GIE - 11 TXINT TXIF - TXIE GIE - 12 RXINT RXIF - RXIE GIE - 13 I2CINT I2CIF - I2CIE GIE - 14 TKINT TKIF - TKIE GIE Table 6-3 Interrupt Logic Table (Default Interrupt Mode) Note: When configured to default interrupt mode, all interrupt vector start addresses are located at 0004 H. Users should check the interrupt flag and interrupt enable bit in interrupt service routine to determine the interrupt source and execute the corresponding interrupt service subroutine. Priority configuration is not supported in the default interrupt mode. V /138

101 Vectored Interrupt Mode Interrupt Vector Allocation Table Priority 0 (Highest) (Lowest) Start 0004 H 0008 H 000C H 0010 H 0014 H 0018 H 001C H 0020 H 0024 H 00 IG0 IG1 IG2 IG3 IG4 IG5 IG6 IG7 INTV 01 Software IG0 IG1 IG6 IG7 IG4 IG5 IG2 IG3 10 Interrupt IG4 IG5 IG2 IG3 IG0 IG1 IG6 IG7 11 IG7 IG6 IG5 IG4 IG3 IG2 IG1 IG0 Table 6-4 Interrupt vector configuration table Note : When configured to vector interrupt mode, interrupt vector table is supported. All interrupt sources are divided into groups, and each group of interrupts have a corresponding interrupt vector start address. Software interrupt start address is at 0004 H and its priority is the highest. Other hardware interrupts are divided to 8 groups (IG0~IG7), which can be configured with different vector priorities and 8 corresponding interrupt start addresses. Each group of hardware interrupts can be configured to have high/low priority in order to respond the interrupt nesting. All hardware interrupts can be separeted into high or low priority arbitration area by IGPx bit, where each group in its corresponding region are ranked based on the setting of INTV<1:0> and the group with the highest priority is first responded. The high and low priority arbitration regions are respectively enabled by the high priority interrupt enable bit GIE and low priority interrupt enable bit GIEL. During the execution of the low priority interrupt service routine, the nested interrupt with high priority will be serviced first Interrupt Vector Groups Interrupt High/Low Priority group No. Selection Interrupt Name Remark IG0 IGP0 KINT - T8NINT T8P1INT - IG1 IGP1 T8P2INT T8P3INT IG2 IGP2 PINT0 - PINT1 IG3 IGP3 TXINT - RXINT IG4 IGP4 ADINT IG5 IGP5 ACP4INT IG6 IGP6 I2CINT - TKINT - IG7 IGP7 - - Table 6-5 Interrupt Vector Groups V /138

102 Interrupt Enable Configuration No. Interrupt Interrupt Interrupt High / Low Priority IGPx Name Flag Enable Interrupt Enable Remark 1 Software Set by SOFTIF - - GIE interrupt software 2 PINT0 PIF0 PIE0 0 GIEL - 1 GIE - 3 PINT1 PIF1 PIE1 0 GIEL - 1 GIE - 4 T8NINT T8NIF T8NIE 0 GIEL - 1 GIE - 5 T8P1INT T8P1IF T8P1IE 0 GIEL - 1 GIE - 6 T8P2INT T8P2IF T8P2IE 0 GIEL - 1 GIE - 7 T8P3INT T8P3IF T8P3IE 0 GIEL - 1 GIE - 8 TXINT TX1IF TX1IE 0 GIEL - 1 GIE - 9 RXINT RX1IF RX1IE 0 GIEL - 1 GIE - 10 ADINT ADIF ADIE 0 GIEL - 1 GIE - 11 KINT KIF KIE 0 GIEL - 1 GIE - 12 ACP4INT ACP4IF ACP4IE 0 GIEL - 1 GIE - 13 I2CINT I2CIF I2CIE 0 GIEL - 1 GIE - 14 TKINT TKIF TKIE 0 GIEL - 1 GIE - Table 6-6 Vectored Interrupt Mode Enable Configuration V /138

103 Special Function Registers Global Interrupt Control Register (INTG) FF96 H Reset Value INTV<1:0> bit1-0 R/W Interrupt vector table select, please refer to interrupt vector configuration table for details INTVEN0 bit2 R/W Interrupt mode select bit 0:Default interrupt mode 1:Vectored interrupt mode (the configuration word INTVEN1 must be set) SOFTIF bit3 R/W Software interrupt flag bit 0:No software interrupt 1:Software interrupt occurred - bit GIEL bit6 R/W Low priority interrupt enable bit (vectored interrupt mode) 0:Disable low priority interrupt 1:Enable low priority interrupt GIE bit7 R/W Global interrupt enable, or high priority interrupt enable 0:Disable all interrupts, or disable high priority interrupt 1:Enable all unmasked interrupts, or enable high priority interrupt Interrupt Priority Register (INTP) FF97 H Reset Value IGP<7:0> bit7-0 R/W IG7-IG0 interrupt priority select bit 0:Low priority 1:High priority Interrupt Control Register 0 (INTC0) FF98 H Reset Value KMSKx<3:0> bit3-0 R/W KINx key input mask bits 0:Masked 1:Not masked - bit PEG0 bit6 R/W PINT0 trigger edge select bit 0:PINT0 falling edge 1:PINT0 rising edge V /138

104 PEG1 bit7 R/W PINT1 trigger edge select bit 0:PINT1 falling edge 1:PINT1 rising edge Interrupt Flag Register 0 (INTF0) FF9B H Reset value KIF bit0 R/W T8NIF bit1 R/W T8P1IF bit2 R/W T8P2IF bit3 R/W T8P3IF bit4 R/W Level change interrupt flag bit 0:No interrupt 1:Interrupt occurred T8N overflow interrupt flag bit 0:No overflow 1:Overflow occurred ( cleared by software) T8P1 interrupt flag bit 0:No match interrupt 1:Match interrupt occurred (cleared by software) T8P2 interrupt flag bit 0:No match interrupt 1:Match interrupt occurred (cleared by software) T8P3 interrupt flag bit 0:No match interrupt 1:Match interrupt occurred (cleared by software) - bit5 - - PIF0 bit6 R/W External port interrupt 0 flag bit 0:No interrupt signal on external port PINT0 1:Interrupt signal generated on external port PINT0(cleared by software) PIF1 bit7 R/W External port interrupt 1 flag bit 0:No interrupt signal on external port PINT1 1:Interrupt signal generated on external port PINT1(cleared by software) Interrupt Enable Register 0(INTE0) FF9A H Reset Value KIE bit0 R/W T8NIE bit1 R/W Level change interrupt enable bit 0:Disabled 1:Enabled T8N overflow interrupt enable bit 0:Disable T8N interrupt 1:Enable T8N interrupt V /138

105 T8P1IE bit2 R/W T8P2IE bit3 R/W T8P1 interrupt enable bit 0:Disable T8P1 interrupt 1:Enable T8P1 interrupt T8P2 interrupt enable bit 0:Disable T8P2 interrupt 1:Enable T8P2 interrupt T8P3IE bit4 R/W T8P3 interrupt enable 0:Disable T8P3 interrupt 1:Enable T8P3 interrupt - bit5 - - PIE0 bit6 R/W External port interrupt 0 enable bit 0:Disable external port interrupt 0 1:Enable external port interrupt 0 PIE1 bit7 R/W External port interrupt 1 enable bit 0:Disable external port interrupt 1 1:Enable external port interrupt 1 Interrupt Flag Register 1 (INTF1) FF9D H Reset value ADIF bit0 R/W ADC interrupt flag bit 0: A/D conversion in progress 1:A/D conversion completed(cleared by software) - bit ACP4IF bit4 R/W ACP4 interrupt flag bit 0:No change on Analog comparator 4 output 1:Analog comparator 4 output changed(cleared by software) - bit Interrupt Enable Register 1 (INTE1) FF9C H Reset value ADIE bit0 R/W ADC interrupt enable bit 0:Disable ADC interrupt 1:Enable ADC interrupt - bit ACP4IE bit4 R/W ACP4 Analog Comparator interrupt enable bit 0:Disable ACP4 interrupt 1:Enable ACP4 interrupt V /138

106 - bit Interrupt Flag Register 2 (INTF2) FF9F H Reset value TXIF bit0 R UART transmit interrupt flag bit 0:Transmit buffer full (transmission not completed) 1:Transmit buffer empty (transmission completed), should be cleared by writing TXB register RXIF bit1 R UART receive interrupt flag bit 0:Receive buffer empty (reception not completed) 1:Receive buffer full (reception completed), should be cleared by reading RXB register - bit I2CIF bit6 R/W TKIF bit7 R/W I2C communication interrupt flag bit 0:No communication interrupt occurred 1:Communication interrupt occurred Touch key interrupt flag bit 0:Not started or scan in progress 1:Scan completed V /138

107 Interrupt Enable Register 2 (INTE2) FF9E H Reset Value TXIE bit0 R/W RXIE bit1 R/W UART transmit interrupt enable bit 0:Disabled 1:Enabled UART receive interrupt enable bit 0:Disabled 1:Enabled - bit I2CIE bit6 R/W I2C communication interrupt enable bit 0:Disabled 1:Enabled TKIE bit7 R/W Touch key interrupt enable bit 0:Disabled 1:Enabled V /138

108 6. 5 Low Power Mode MCU Low Power Mode Two low power modes are available, idle0 mode or idle1 mode, selected by LPM bit (PWRC<7>). Idle 0 - Idle0 mode is entered by executing the IDLE instruction when LPM = 0 - The clock source stops and the system clock halts. - Program and synchronous module are suspended while asynchronous module continues to run, thus reducing the device power - Supports wake-up with configurable wake-up time. LDO settling time should be considered. - All I/Os maintain the status they had before entering idle0. - If WDT is enabled, WDT will be cleared but keeps running. - N_PD bit is cleared and N_TO bit is set. Idle 1 - Idle1 mode is entered by executing the IDLE instruction when LPM = 1 - The clock source continues to run and the system clock halts. - Program and synchronous module are suspended while asynchronous module continues to run, thus reducing the device power - Supports wake-up with configurable wake up time, minimum 1 machine cycle - All I/Os maintain the status they had before entering idle1 - If WDT is enabled, then WDT will be cleared but keeps running. - N_PD bit is cleared and N_TO bit is set Low Power Mode Configuration Low Power Mode LPM Idle 0 Mode 0 Idle 1 Mode 1 Table 6-7 Low Power Mode Configuration Note: Configure LPM (PWRC<7>) to select low consumption mode and enter low consumption mode using the idle instruction. To reduce the power consumption, all I/O pins should be tied to VDD or VSS. To avoid switch current caused by floating pins, all input I/O pins should be tied to high level or low level. V /138

109 Wake-up Sources No. Wake-up Interrupt Interrupt Source Mask Enable Interrupt Mode Remark 1 N_MRST WDT WDT overflow KMSK0 3 KINT KMSK1 Default KIE KMSK2 /vectored - KMSK3 4 PINT0 - PIE0 Default /vectored - 5 PINT1 - PIE1 Default /vectored - 6 ACP4INT - ACP4IE Default /vectored - Table 6-8 Wake Up Configuration Note1: Wake-up from low power mode is regardless of the status of the global interrupt enable bit. If an interrupt is generated by peripherals, the system will still wake up from the low power mode even if GIE=0 in default interrupt mode or GIE=0 & GIEL=0 in vectored interrupt mode. However, the interrupt service routine will not be executed. Note2: For external key interrupt, before enabling the interrupt (KMSKx=1, KIE=1), it is necessary to read/write all the port registers and clear KIF to avoid unwanted interrupts Wake-up Time Low Power Mode Calculation Formula Idle 0 Mode VRwkdly + (WKDC[7:4] + 1) 16 2 Tosc Idle 1 Mode (WKDC[7:0]+1) 2 Tosc Table 6-9 Wake Up Time Calculation Note: After waking up from idle mode, CPU will execute the next instruction after the system clock has run for n clock cycles, where n is specified by WKDC register. A minimum of one machine cycle of wake up time is supported in idle 1 mode. In idle 0 mode, n clock cycles are calculated after the system clock source is settled Special Function Registers Wake-up Delay Control Register (WKDC) FFA8 H Reset Value WKDC <7:0> bit7-0 R/W Wake-up delay control bits WKDC<7:0> = FF H : longest delay WKDC<7:0> = 00 H : shortest delay V /138

110 6. 6 Configuration Word OSCS <2:0> WDTEN PWRTEB TKPB6 BORVS BOREN FREN ICDEN INTVEN1 TKPB54 bit2-0 bit3 bit4 bit5 bit7-6 bit8 bit9 bit10 bit11 bit12 Chip Configuration Word (CFG_WD) 8001 H Oscillator select bits 000 : HS mode, high speed crystal/resonator connected to pin PA0 and PA1 001 : XT mode, crystal/resonator connected to PA0 and PA1 010 : INTOSCIO 1MHz mode, PA0 and PA1 used as I/O 011 : INTOSCIO 2MHz mode, PA0 and PA1 used as I/O 100 : INTOSCIO 4MHz mode, PA0 and PA1 used as I/O 101 : INTOSCIO 8MHz mode, PA0 and PA1 used as I/O 110 : INTOSC 16MHz mode, PA0 as CLKO,PA1 used as I/O 111 : INTOSCIO 16MHz mode, PA0 and PA1 used as I/O Hardware WDT enable bit 0:Disabled 1:Enabled POR/BOR timer enable bit 0:Enabled 1:Disabled PB6 /TK13 untouched key output enable bit 0:Disabled 1:Enabled BOR voltage select bits 00:4.0V 01:3.3V 10:2.4V 11:2.1V(default, not recommended if the power supply of the application system is not stable) Brown-Out reset enable bit 0:Disabled 1:Enabled Flash data memory read and write enable bit 0:Disabled 1:Enabled ICD debug mode enable bit 0:Enabled 1:Disabled Interrupt mode select bit 0:Default interrupt mode 1:Vectored interrupt mode (INTVEN0 must be 1) PB5/TK12,PB4/TK11 untouched key output enable bit 0:Disabled V /138

111 VTKVSEL TKPB32 TKPB10 bit13 bit14 bit15 Chip Configuration Word (CFG_WD) 1:Enabled TK mode power supply select bit 0:2.6V (VDD must be greater than 4V) 1:VDD PB3/TK10, PB2/TK9 untouched key output enable bit 0:Disabled 1:Enabled PB1/TK8, PB0/TK7 untouched key output enable bit 0:Disabled 1:Enabled Note1. CLKO = Fosc /16. Note2. For untouched key output state control, refer to TKTUN<1:0> bits (TKOUTS<1:0>) Note3. The BOR voltage is factory calibrated with accuracy of + / - 0.2V at 25 and VDD=5V. Note4. The BOR module is strongly suggested to be enabled at all time. Otherwise, the device might work abnormally in the case that the power supply is unstable. V /138

112 Pin Package Drawing Chapter7 Packaging Information SOP20 E1 E L θ c b D A2 A3 A e A1 Symbol mm inch MIN NOM MAX MIN NOM MAX A A A A b c D E E e 1.270BSC BSC L θ V /138

113 DIP20 A A2 L A1 e b b1 ea eb E1 D Symbol (mm) (inch) MIN NOM MAX MIN NOM MAX A A A b b D E e ea eb L V /138

114 Pin Packaging Drawing SOP16 E1 E L θ c b D A2 A A3 e A1 Symbol (mm) (inch) MIN NOM MAX MIN NOM MAX A A A A b c D E E e (BSC) 0.050(BSC) L θ V /138

115 Pin Packaging Drawing SOP14 E1 E L θ c b D A2 A A3 e A1 Symbol (mm) (inch) MIN NOM MAX MIN NOM MAX A A A A b c D E E e (BSC) 0.050(BSC) L θ V /138

116 Appendix1 Instruction Set Appendix1. 1 Overview The device provides 79 RISC instructions. Most of the assembly instruction names are in abbreviations of English to make programming easier. After being complied and linked by compiler, the program consisting of these instructions will be converted to corresponding instruction codes, which include OP codes and Operands. Each OP code corresponds to one mnemonics. One machine cycle is 500ns when the device runs at 4MHz. Based on the machine cycles required for individual instruction operations, there are two-cycle instruction and single-cycle instruction. CALL, LCALL, RCALL, GOTO, JUMP, RET, RETIA and RETIE are two-cycle instructions; JBC, JBS, JDEC, JINC, are two-cycle instructions only when the jump conditions are met, otherwise they are single-cycle instructions. All other instructions are single-cycle instructions. Appendix1. 2 Register Instruction No. Instruction Affected Machine Status Bit Cycle Operation 1 SECTION I<7:0> - 1 I<7:0>->BKSR<7:0> 2 PAGE I<8:0> - 1 I<4:0>->PCRH<7:3> 3 ISTEP I<7:0> - 1 IAA+i->IAA(-128 i 127) 4 MOVI I<7:0> - 1 I<7:0>->(A) 5 MOV R<7:0>,F Z,N 1 (R)-> (DEST.) 6 MOVA R<7:0> - 1 (A)->(R) 7 MOVAR R<10:0> - 1 (A)->(R) (R is GPR) 8 MOVRA R<10:0> - 1 (R) -> (A) (R is GPR) V /138

117 Appendix1. 3 Program Control Instruction No. Instruction Affected Machine Status Cycle Bit Operation 9 JUMP I<7:0> - 2 PC+1+i<7:0>->PC (-128 i 127) 10 AJMP I<19:0> - 2 I<13:0>->PC<13:0> I<13:8>->PCRH<5:0> 11 GOTO I<10:0> - 2 I<10:0>->PC<10:0> PCRH<5:3>->PC<13:11> 12 CALL I<10:0> - 2 PC+1->TOS,I<10:0>->PC<10:0> PCRH<5:3>->PC<13:11> 13 LCALL I<19:0> - 2 PC+1->TOS,I<13:0>->PC<13:0> I<13:8>->PCRH<5:0> 14 RCALL R<7:0> - 2 PC+1 TOS, (R) PC<7:0>, PCRH<5:0> PC<13:8>, 15 JBC R<7:0>,B<2:0> - 2 or1 Skip the next instruction if R<B> = 0 16 JBS R<7:0>,B<2:0> - 2 or 1 Skip the next instruction if R<B> = 1 17 JCAIE I<7:0> - 2 or 1 Skip the next instruction if (A) = I 18 JCAIG I<7:0> - 2 or 1 Skip the next instruction if (A) > I 19 JCAIL I<7:0> - 2 or 1 Skip the next instruction if (A) < I 20 JCRAE R<7:0> - 2 or 1 Skip the next instruction if (R) = (A) 21 JCRAG R<7:0> - 2 or 1 Skip the next instruction if (R) > (A) 22 JCRAL R<7:0> - 2 or 1 Skip the next instruction if (R) < (A) 23 JCCRE R<7:0>,B<2:0> - 2 or 1 Skip the next instruction if C = R(B) 24 JCCRG R<7:0>,B<2:0> - 2 or 1 Skip the next instruction if C > R(B) 25 JCCRL R<7:0>,B<2:0> - 2 or 1 Skip the next instruction if C < R(B) 26 JDEC R<7:0>,F - 2 or 1 (R-1) -> (destination register), Skip the next instruction if the value of the destination register is 0 27 JINC R<7:0>,F - 2 or 1 (R+1) -> (destination register), Skip the next instruction if the value of the destination register V /138

118 No. Instruction Affected Machine Status Cycle Bit Operation is 0 28 NOP No operation 29 POP AS->A, PSWS->PSW, PCRHS->PCRH 30 PUSH A->AS, PSW->PSWS, PCRH->PCRHS 31 RET TOS->PC 32 RETIA I<7:0> - 2 I->(A),TOS->PC 33 RETIE TOS->PC,1->GIE 34 RST - All States bits are affected 1 Software reset instruction 35 CWDT - N_TO, 00H->WDT,0->WDT Prescaler, 1 N_PD 1-> N_TO, 1-> N_PD 36 IDLE - N_TO, 00H->WDT, 0->WDT Prescaler, 1 N_PD 1-> N_TO, 0-> N_PD V /138

119 Appendix1. 4 Arithmetic/Logical Operation Instructions No. Instruction Affected Machine Status Bit Cycle Operation 37 ADD R<7:0>,F C, DC,Z,OV,N 1 (R)+ (A) -> (DEST.) 38 ADDC R<7:0>,F C, DC,Z,OV,N 1 (R)+ (A) +C-> (DEST.) 39 ADDCI I<7:0> C, DC,Z,OV,N 1 I+(A)+C->(A) 40 ADDI I<7:0> C, DC,Z,OV,N 1 I+(A)->(A) 41 AND R<7:0>,F Z,N 1 (A).AND. (R) -> (DEST.) 42 ANDI I<7:0> Z,N 1 I.AND.(A)->(A) 43 BCC R<7:0>,B<2:0> >R<B> 44 BSS R<7:0>,B<2:0> >R<B> 45 BTT R<7:0>,B<2:0> - 1 (~R<B>)->R<B> 46 CLR R<7:0> Z 1 (R)=0 47 SETR R<7:0> - 1 FF H ->(R) 48 NEG R<7:0> C, DC,Z,OV,N 1 ~(R)+1-> (R) 49 COM R<7:0>,F Z,N 1 (~R)-> (DEST.) 50 DAR R<7:0>,F C 1 (R) (BCD)->( DEST.) 51 DAA - C 1 (A) (BCD) ->(A) 52 DEC R<7:0>,F C, DC,Z,OV,N 1 (R-1)-> (DEST.) 53 INC R<7:0>,F C, DC,Z,OV,N 1 (R+1)-> (DEST.) 54 IOR R<7:0>,F Z,N 1 (A).OR. (R)-> (DEST.) 55 IORI I<7:0> Z,N 1 I.OR.(A)->(A) 56 RLB R<7:0>,F,B<2:0 > C,Z,N 1 C<< R<7:0> <<C 57 RLBNC R<7:0>,F,B<2:0 > Z,N 1 R<7:0> << R<7> 58 RRB R<7:0>,F,B<2:0 > C,Z,N 1 C>> R<7:0> >>C 59 RRBNC R<7:0>,F,B<2:0 > Z,N 1 R<0> >> R<7:0> 60 SUB R<7:0>,F C,DC,Z,OV, N 1 (R)- (A) -> (DEST.) 61 SUBC R<7:0>,F C,DC, Z,OV,N 1 (R)- (A) - (~C) -> (DEST.) V /138

120 No. Instruction Affected Machine Status Bit Cycle Operation 62 SUBCI I<7:0> C,DC,Z,OV, N 1 I-(A)- (~C)->(A) 63 SUBI I<7:0> C,DC,Z,OV, N 1 I-(A)->(A) 64 SSUB R<7:0>,F C,DC,Z,OV, N 1 (A)-(R) -> (DEST.) 65 SSUBC R<7:0>,F C,DC,Z,OV, N 1 (A)-(R) - (~C) -> (DEST.) 66 SSUBCI I<7:0> C,DC,Z,OV, N 1 (A)-I- (~C)->(A) 67 SSUBI I<7:0> C,DC,Z,OV, N 1 (A)-I->(A) 68 SWAP R<7:0>,F - 1 R<3:0>-> (DEST.)<7:4>, R<7:4>-> (DEST.)<3:0> 69 TBR Pmem (FRA)->ROMD 70 TBR# Pmem(FRA)-> ROMD, FRA+1->FRA 71 TBR_ Pmem(FRA)-> ROMD, FRA-1->FRA 72 TBR1# FRA+1->FRA, Pmem (FRA)-> ROMD 73 TBW Not supported 74 TBW# Not supported 75 TBW_ Not supported 76 TBW1# Not supported 77 XOR R<7:0>, F Z,N 1 (A).XOR. (R)-> (DEST.) 78 XORI I<7:0> Z,N 1 I.XOR.(A)->(A) Notes 1. i-immediate, F-Flag, A-Register A, R-Register R, B-the Bth bit in Register R or shift by B bits 2. C-carry/ borrow, DC-half carry/half borrow, Z-Zero flag, OV-Overflow flag, N-Negative flag 3. TOS-Top of Stack 4. If F = 0, the destination register is Register A; if F = 1, the destination register is Register R. 5. Another NOP instruction in the 79 RISC is not described in the above table. 6. For SECTION instruction, the size of N varies from chip to chip. For this chip, given the general-purpose data memory GPR has 8 memory banks, so the N is For PAGE instruction, the size of N varies from chip to chip. For this chip, the N is 3 since there is no PCRU register. 8. For this chip, the length of PC is 14 bits and there is no PCRU register present. V /138

121 Appendix2 Special Function Register Summary Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 POR Value FF80 H IAD Indirect ing Data Register <7:0> FF81 H IAAL Indirect ing Register <7:0> FF82 H IAAH Indirect ing Register <15:8> FF83 H BKSR - BKSR<2:0> FF84 H PSW - UF OF N OV Z DC C x00x xxxx FF85 H AREG Register A <7:0> xxxx xxxx FF86 H PCRL Program Counter <7:0> FF87 H PCRH Program Counter <15:8> FF88 H MULA/ MULL Multiplier A Register / Product Register <7:0> xxxx xxxx FF89 H MULB/ MULH Multiplier B Register / Product Register <15:8> xxxx xxxx FF8A H DIVEL/ DIVQL Dividend Register <7:0>/ Quotient Register <7:0> xxxx xxxx FF8B H DIVEH/ DIVQH Dividend Register <15:8>/ Quotient Register <15:8> xxxx xxxx FF8C H DIVS/DIVR Divisor Register / Remainder Register <7:0> xxxx xxxx FF8D H FF8E H FF8F H FF90 H FRAL Flash Read Register <7:0> xxxx xxxx FF91 H FRAH Flash Read Register <15:8> xxxx xxxx FF92 H ROMDL ROM Data Register <7:0> xxxx xxxx V /138

122 Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 POR Value FF93 H ROMDH ROM Data Register <15:8> xxxx xxxx FF94 H ROMCL - FPEE WREN WR FF95 H ROMCH ROM Control Register <15:8> FF96 H INTG GIE GIEL - SOFTIF INTVEN0 INTV<1:0> FF97 H INTP Interrupt Priority Register IGP<7:0> FF98 H INTC0 PEG1 PEG0 - KMSKx<3:0> FF99 H FF9A H INTE0 PIE1 PIE0 - T8P3IE T8P2IE T8P1IE T8NIE KIE FF9B H INTF0 PIF1 PIF0 - T8P3IF T8P2IF T8P1IF T8NIF KIF FF9C H INTE1 - ACP4IE - ADIE FF9D H INTF1 - ACP4IF - ADIF FF9E H INTE2 TKIE I2CIE - RXIE TXIE FF9F H INTF2 TKIF I2CIF - RXIF TXIF FFA0 H - Reserved - FFA1 H - Reserved - FFA2 H VREFCAL VR2D6CAL <4> AD2D6CAL<2:0> VR2D6CAL<3:0> FFA3 H WDTCAL Internal 32KHz RC calibration register<7:0> FFA4 H OSCCALL Internal 16mhz Clock Calibration Register Low Byte FFA5 H OSCCALH - OSCCALH<1:0> FFA6 H PWRC LPM VRST N_RSTI N_TO N_PD N_POR N_BOR FFA7 H WDTC - WDTPRE WDTPRS<2:0> FFA8 H WKDC Wake-Up Delay Control Register <7:0> FFA9 H PWEN - RCEN SREN FFAA H PA PA7 PA6 PA5 PA4 PA3 - PA1 PA xxxx V /138

123 Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 POR Value FFAB H PAT PAT7 PAT6 PAT5 PAT4 PAT3 - PAT1 PAT FFAC H PB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 xxxx xxxx FFAD H PBT PBT7 PBT6 PBT5 PBT4 PBT3 PBT2 PBT1 PBT FFAE H PC - PC1 PC0 xxxx xxxx FFAF H PCT - PCT1 PCT FFB0 H PAPU Port A Pull-up Register FFB1 H PBPU Port B Pull-up Register FFB2 H PCPU Port C Pull-up Register FFB3 H PALC PALC<7:3> - PALC<1:0> FFB4 H PAOD Port A Open Drain Register FFB5 H PBOD Port B Open Drain Register FFB6 H PCOD Port C Open Drain Register FFB7 H PAPD Port A Pull-down Register FFB8 H PBPD Port B Pull-down Register FFB9 H PCPD Port C Pull-down Register FFBA H FFBB H T8N T8N Timer/Counter FFBC H T8NC T8NEN T8NCLK T8NM T8NE G T8NPRE T8NPRS<2:0> FFBD H T8P1 T8P1 Timer/Counter FFBE H T8P1C T8P1M T8P1POS<3:0> T8P1E T8P1PRS<1:0> FFBF H T8P1P T8P1 Period Register FFC0 H T8P1RL T8P1 Resolution Register FFC1 H T8P1RH T8P1 Resolution Buffer Register FFC2 H T8P1OC - PWM11 PWM10E V /138

124 Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 EN N POR Value FFC3 H T8P2 T8P2 Timer/Counter FFC4 H T8P2C T8P2M T8P2POS<3:0> T8P2E T8P2PRS<1:0> FFC5 H T8P2P T8P2 Period Register FFC6 H T8P2RL T8P2 Resolution Register FFC7 H T8P2RH T8P2 Resolution Buffer Register FFC8 H T8P2OC - PWM21 EN PWM20E N FFC9 H T8P3 T8P3 Timer/Counter FFCA H T8P3C T8P3M T8P3POS<3:0> T8P3E T8P3PRS<1:0> FFCB H T8P3P T8P3 Period Register FFCC H T8P3RL T8P3 Resolution Register FFCD H T8P3RH T8P3 Resolution Buffer Register FFCE H T8P3OC - PWM31EN PWM30EN FFCF H EPWM1C PWM1ADEN P1M1 - PWM1ADS - EPWM1M<1:0> FFD0 H EPWM2C PWM2ADEN P1M2 - PWM2ADS EPWM2 OS EPWM2M<1:0> FFD1 H EPWM3C PWM3ADEN P1M3 - PWM3ADS - EPWM3M<1:0> FFD2 H PDD1C PRSEN1 PDD1C<6:0> FFD3 H PDD2C PRSEN2 PDD2C<6:0> FFD4 H PDD3C PRSEN3 PDD3C<6:0> FFD5 H TE1AS EPWM1ASF - FFD6 H TE2AS EPWM2ASF - EPWM1A S0 EPWM2A S0 - PSS1BD<1:0> PSS2BD<1:0> V /138

125 Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 POR Value FFD7 H TE3AS EPWM3ASF - EPWM3A S0 - PSS3BD<1:0> FFD8 H TMRADC PWM Edge Detect Delay Register FFD9 H ADCTST - ADHSEN AINEN FFDA H ADCRL ADC Result Register Low Byte xxxx xxxx FFDB H ADCRH ADC Result Register High Byte xxxx xxxx FFDC H ADCCL ADCHS<3:0> ADVOUT SMPS ADTRG ADEN FFDD H ADCCH ADFM ADCKS<2:0> ADST<1:0> ADVREFS<1:0> FFDE H ANSL - Analog Select Register Low Byte FFDF H ANSH - Analog Select Register High Byte FFE0 H RXB UART Receive Buffer Register FFE1 H RXC RXEN RXM - OERR FERR RXR x FFE2 H TXB UART Transmit Buffer Register FFE3 H TXC TXEN TXM BRGH - TRMT TXR FFE4 H BRR UART Baud Rate Register FFE5 H TKSEL TKCTR TKDU S TKFS<1:0> TKCHS<3:0> FFE6 H TKTUN TKTMS<1:0> TKCFT<1:0> TKDIST<1:0> TKOUTS<1:0> FFE7 H TKCTL - SCANO V TKERR TKOV TKEN TKGO FFE8 H TKDAL Touch Key Data Register Low Byte FFE9 H TKDAM Touch Key Data Register Middle Byte FFEA H TKDAH Touch Key Data Register High Byte FFEB H TKMODL Amplification Factor Register Low Byte FFEC H TKMODM Amplification Factor Register Middle Byte V /138

126 Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 POR Value FFED H TKMODH Amplification Factor Register High Byte FFEE H TKMODU - Amplification Factor Register Upper 4 Bits<3:0> FFEF H I2CX16 - I2C Sampling Filter control bit <3:0> FFF0 H I2CC I2CTE I2CP U I2COD I2CTAS I2CANAE I2CCSE I2CRST I2CEN FFF1 H I2CSA I2CSADR<6:1> I2CRW FFF2 H I2CTB I2C Transmit Buffer Register FFF3 H I2CRB I2C Receive Buffer Register FFF4 H I2CIEC - I2CNAIE I2CROIE FFF5 H I2CIFC - I2CNAIF I2CROIF I2CTEI E I2CTEI F I2CRBIE I2CTBIE I2CSPIE I2CSRIE I2CRBIF I2CTBIF I2CSPIF I2CSRIF FFF6 H FFF7 H FFF8 H FFF9 H ACPC4 - C4OUT C4NM<1:0> - C4INV C4EN FFFA H FFFB H VRC1 VREFE N VRC2S<2:0> VRC1S<2:0> VOUTEN FFFC H PPGC CMXOFFSET<3:0> - - FFFD H FFFE H FFFF H V /138

127 Appendix3 Electrical Characteristics Appendix3. 1 Parameter Characteristics Absolute Maximum Ratings Parameter Symbol Conditions Range Unit Power supply VDD ~ 7.5 V Input voltage V IN ~ VDD V Output voltage V OUT ~ VDD V Storage temperature T STG ~ 125 Operating temperature T OPR VDD:3.0 ~ 5.5V -40 ~ 85 Power Consumption Characteristics Parameter Symbol Min. Typ. Max. Unit. Operating Condition Power supply VDD V -40 ~ 85 Static current I DD ua 25,VDD = 5V,BOR disabled. All I/O port input low level, N_MRST = 0,OSC1 = 0, OSC2 floating. Idle 0 current I PD μa 25,VDD = 5V, BOR disabled. WDT enabled. I PD μa 25, VDD = 5V, BOR enabled, WDT enabled. I PD μa 25, VDD = 5V, BOR enabled, WDT enabled, Idle 1 current internal oscillator. 25, VDD = 5V, BOR I PD μa enabled, WDT enabled, external oscillator. I OP1-2 - ma 25,VDD = 5V, normal operation mode, internal 16MHz clock input, I/O port output level fixed, no load. Operating current 25,VDD = 5V, normal I OP ma operation mode, external HS mode 16MHz clock, I/O port output level fixed, no load. Max. input current on VDD pin I MAXVDD - 80 ma 25,VDD = 5V V /138

128 Parameter Symbol Min. Typ. Max. Unit. Operating Condition Max. output current on VSS pin I MAXVSS ma 25,VDD = 5V Sink current on 25,VDD = 5V I OL ma normal drive I/O V OL = 0.6V Source current on 25,VDD = 5V I OH ma normal drive I/O V OH = 4.4V Sink current on 25,VDD = 5V I OL ma high drive I/O V OL = 0.6V Source current on 25,VDD = 5V I OH ma high drive I/O V OH = 4.4V Input Port Characteristics Chip Operating Temperature: -40 ~ 85 Parameter Input high voltage (with Schmidt input characteristic) N_MRST input high voltage (with Schmidt input characteristic) Input low voltage N_MRST input low voltage Input leakage current Reset pin leakage current Input weak pull-up current Input weak pull-down current Symbo l Min. Typ. Max. Unit Test Condition 0.8VDD - VDD V V IH V IL I IL 0.8VDD - VDD V 3.0V VDD 5.5V VSS VDD V VSS VDD V 3.0V VDD 5.5V μa VSS Vpin VDD (ports in high impedance state) μa VSS Vpin VDD I WPU μa 3.0V VDD 5.5V Vpin = VSS I WPD μa 3.0V VDD 5.5V Vpin = VDD 25,VDD=5V,Weak Input VDD/2 output V VDD/2 - ±5% - - pull up and weak pull down enabled at the same time V /138

129 Output Port Characteristics Operating Temperature Range: -40 ~ 85 Parameter Symbol Min. Typ. Max. Unit Test Condition Output high 3.0V VDD 5.5V V OH VDD V voltage I OH = 6.0 ma Output low 3.0V VDD 5.5V V OL V voltage I OL = 12 ma System Clock Requirements Parameter Symbol Min. Typ. Max. Unit Test Condition System clock frequency F OSC M Hz 3.0V VDD 5.5V System clock period T OSC ns 3.0V VDD 5.5V Machine cycle T inst ns - External clock high and low time External clock rising and falling time WDT overflow time (No frequency division) T OSL, T OSH T OSR, T OSF T WDT ns ns - 3.0V VDD 5.5V ms -40 ~ 85 (54KHz) (32KHz) (9.6KHz) V /138

130 12-Bit ADC Characteristics Parameter Symbol Min. Typ. Max. Unit Test Condition Power supply VDD V V ADHSEN=1(high-s peed) ADHSEN=0(low-sp Resolution R R bit 25,VDD=5V,f ADC Differential DNL CLK - - ±2 LSB Non-Linearity =2MHz,ADHSEN= Integral INL 0, the sampling - - ±2 LSB Non-Linearity time is 8 x V OFFSET ADCCLK, the Offset Error LSB reference voltage is the internal VDD V REF1 25,VDD=5V,Inter VDD V nal VDD reference V REF2 25, VDD=5V, Reference voltage range V internal 2.5V reference V REF3 25, VDD=5V, 2 - VDD V external VREFP reference Analog voltage V ADIN input - - V REF1~3 V - Input capacitor C ADIN Pf - Input resistor R ADIN KΩ - F ADCLK (high-sp Conversion MHz ADHSEN=1 eed) clock F ADCLK (low-spe frequency MHz ADHSEN=0 ed) Conversion time (sampling T ADC - Tadclk - 13 time excluded) eed) Sampling time T ADS ADHSEN=1 high-speed us T ADS low-speed ADHSEN=0 Note: All data listed above are theoretical values. V /138

131 ADC Conversion Time Table A/D Clock Operating Frequency Source 16M 8M 4M 1M Fosc Not recommended Not recommended Not recommended T ADCLK = 1us Fosc/2 Not recommended Not recommended T ADCLK = 0.5us T ADCLK = 2us Fosc/4 Not recommended T ADCLK = 0.5us T ADCLK = 1us T ADCLK = 4us Fosc/8 T ADCLK = 0.5us T ADCLK = 1us T ADCLK = 2us T ADCLK = 8us Fosc/16 T ADCLK = 1us T ADCLK = 2us T ADCLK = 4us T ADCLK = 16us Fosc/32 T ADCLK = 2us T ADCLK = 4us T ADCLK = 8us T ADCLK = 32us Fosc/64 T ADCLK = 4us T ADCLK = 8us T ADCLK = 16us T ADCLK = 64us Analog Comparator Characteristics Parameter Symbol Min. Typ. Max. Unit Test Condition Power supply VDD V - Input offset voltage (after V OFFSET mv 25,VDD=5V calibration) Input common mode voltage V COM VDD-1 V - Response time T RESP us - Reference Voltage Characteristics Parameter Symbol Min. Typ. Max. Unit Test Condition Internal reference voltage output VREF2.5 V REF V 25,VDD=5V Internal 16MHz Clock Calibration Characteristics Calibration condition Frequency calibrated to 16MHz at 25 Operation condition Min. Typ. Max. Unit -40 ~85, VDD = 3.0V~5.5V MHz V /138

132 Appendix3. 2 Characteristic Graphs All the graphs provided are a statistical summary based on a limited number of samples and are provided for design reference only. Some data in part of the graphs are beyond specification and the device is guaranteed to operate normally only within the specified range. Static current vs.vdd I/O input voltage vs. VDD (Room Temperature:25 ) VILmax(V) VDD(V) VIHmin(V) VDD(V) V /138

133 I/O Port Output Characteristics (Normal Drive) A: I OH vs. V IOH(mA) VDD=3V VOH(V) B: I OL vs. V VDD=3.0V IOL(mA) VOL(V) V /138

134 C: I OH vs. V D: I OL vs. V VDD=5.0V IOL(mA) VOL(V) V /138

135 E: I OH vs. V F: I OL vs. V VDD=5.5V IOL(mA) VOL(V) V /138

136 I/O Port Output Characteristics (High Drive) A: I OH vs. V B: I OL vs. V V /138

137 C: I OH vs. V D: I OL vs. V V /138