Layer transfer with porous Silicon (PSI-Prozess)

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1 Thin-film Si wafer cells from layer transfer: surpassing the recombination hurdle of Si thin-film technologies Rolf Brendel 1,2 and Barbara Terheiden 1 1 (ISFH) 2 Institut für Festkörperphysik, Leibniz Univ. Hannover

technologies Rolf Brendel 1,2 and Barbara Terheiden 1

2 Layer transfer with porous Silicon (PSI-Prozess) Si cell poröses Si Si substrate textured Si substrate porous Si Si substrate glass carrier Si cell glass carrier Si cell porous Si Si substrate detach cell re-use substrate Si substrate R. Brendel, 14th EU-PVSEC, (1997), p.1354.

carrier Si cell glass carrier Si cell porous Si Si substrate detach

3 Stable process since structure evolves into minimum free energy N. Ott, M. Nerding, G. Müller, R. Brendel, and H. P. Strunk, J. Appl. Phys. 95, 497 (2004). First report on surface closure: V. Labunov, Thin Solid Films 137, 123 (1986) sintered porous Si First report on separation layer formation: H. Tayanaka, in Proc. 2 nd World Conf., (Vienna 1998), p.1272 separation layer Si substrate 200 nm

Labunov, Thin Solid Films 137, 123 (1986) sintered porous Si First report on separation layer

4 Various cell process are easily feasible 20 µm 15 µm Solarzelle! Texturing on one or the other side Trennschicht! Diffusion on one or the other side! Mech. supported monocrystalline Si film 20 µm Substrat

5 High lifetime in layer transfer films 16 Effective Eff. Lebensdauer life time τ eff eff [µs] τ vol =16.4 µs S f+r =38 cm/s τ vol =12.3 µs S f+r = 5 cm/s Thickness Dicke W W [µm] [µm]! µw-pcd on transferred a-si passivated thin films! 16 µs lifetime! Surface recombination velocity of 20 cm/s A. Wolf B. Terheiden, and R. Brendel, Progr. in Photov. (2006)

3 µs S f+r = 5 cm/s 5 10 15 20 25 30 Thickness Dicke W W [µm] [µm]!

6 Efficiency potential of thin-film c-si wafers EFFICIENCY η [%] τ t = 1000 µs ms 100 µs 10 µs 3 µs 1µs h η = 18 % 0.1µs W = 2.5 µm RECOMB. VEL. S [cm s - 1 ] " Assumptions: Good optics τ = 1 µs S = 100 cm/s " Simulated efficiency: η = 18 % W = 2.5 µm 90% of Lambetian 16 µs measured 120 cm/s measured R. Brendel, Solar Energy 77, 969, (2004).

S [cm s - 1 ] " Assumptions: Good optics τ = 1 µs S = 100 cm/s " Simulated efficiency: η = 18 %

7 Outline! Efficiency results! Layer transfer processes: a thin-film wafer technology! Active layer deposition: status and perspectives! Cell- and module technology: Status and perspectives

8 Cell results the full scope of wafer cell processes is applicable

9 ELIT*-Process (CNRS group) *Epitaxial Layer for Interdigitated Back Contacts on Transferred Solar Cells J. Kraiem et al. 21st ECPVSEC 2006, p. 1268! Back contacted cell! Thin brother of big brother A300! Cell area 0.5 cm 2 Si-Thickness 70 µm V OC = 515 mv J SC = 26.8 ma/cm 2 FF = 60 % η = 8.2 %

1268! Back contacted cell! Thin brother of big brother A300! Cell area 0.

10 FMS* with heterojunction (IMEC-group) *Free Standing Monocrystalline Silicon L. Carnel et al., IEEE PVSC 2005, p. 1157, C.S. Solanki et al. PIP 2005;13: ! a-si/c-si hetero junction! Thin brother of big brother HIT! Cell area 0.5 cm 2 Si-Thickness 30 µm V OC = 578 mv J SC = 29.2 ma/cm 2 FF = 56.6 % η = 9.6 %! Free standing film processed

a-si/c-si hetero junction! Thin brother of big brother HIT! Cell area 0.

11 QMS-process (Univ. Stuttgart group)! Thin brother of big brother PERC! Laser-fired contacts J. H. Werner, Final Report of Project A, funded by BMU, Germany, 2006, p. 26, 32! Cell area 4 cm 2 Si-Thickness 46 µm V OC = 641 mv J SC = 33.5 ma/cm 2 FF = 78.5 % η = 16.9%

Werner, Final Report of Project 0329818 A, funded by BMU, Germany,

12 PSI*-process on enlarged area *Porous Silicon Process! Process without photolithography! Cell area 26 cm 2 Si-Thickness 25 µm V OC = 611 mv J SC = 34.2 ma/cm 2 FF = 74.6 % η = 15.6%

13 Even larger area... SiN a-si Al n + -type emitter p-type base p + -type bsf Al B. Terheiden, R. Horbelt, and R. Brendel, in Technical Digest, 15th Intern. Photov. Sci. and Eng. Conf. (Shanghai, Institut für 2005) Solarenergieforschung p Hameln Structured by shadow mask! Cell area 95 cm 2 Thickness 26 µm V OC = 616 mv J SC = 29.0 ma/cm 2 FF = 78.8 % η = 14.1%

and Eng. Conf. (Shanghai, Institut für 2005) Solarenergieforschung p. 196.

14 Localization and quantification of recomb. losses in 95 cm 2 - and 14.1%-cell Efficiency loss η [% abs.] Emitter Rear surface Volume 2nd diode Shunt! J sc -V oc analysis j o, j o2,r sh! Optical analysis Generation G! IQE-Analysis S, L, j ob j oe η [ qg Jcoll loss Jrec, V mpp J η η J sc 44 J coll loss J mpp + J mpp rec, V mpp ] V mpp

0 Emitter Rear surface Volume 2nd diode Shunt! J sc -V oc analysis j o, j o2,r sh!

15 Layer transfer is a thin-film wafer technology

16 Layer transfer is a thin-film wafer technology c-si-wafer Thickness > 100 µm Area <20x20 cm 2 Efficiency > 15% T > 800 C feasible p + n n + or p + p n + structure Grain diameter > 1 cm.. Pyramidal texture c-si-thin film Thickness < 50 µm Area > 1 m 2 Efficiency < 15% T < 800 C p + i n + structure Grain diameter < 10 µm Texture by TCOs Black holds for layer transfer Grey Institut für does Solarenergieforschung not hold layer Hamelntransfer

. Pyramidal texture c-si-thin film Thickness < 50 µm Area > 1 m 2 Efficiency < 15% T < 800 C p + i n +

17 Surpassing the hurdles of recombination and stability Module efficiency η [%] Thin-film wafer Recombination hurdle LTP as today µ-morph thin-film CSG thin-film thin-film a-si Saving cost and material Future work Mech. stability hurdle Cell thickness W [µm] Thin Wafer Many wafer projects Wafer

CSG thin-film thin-film a-si 1 3 10 30 100 300 Saving cost and material Future

18 Layer transfer films will have reduced costs per area HCL quartz carbon metalurgical gradesilicon! 10 times less chlorosilane required per area chlorosilanes destillation semiconductor gradechlorosilanes CVD recycling semiconductor gradesilicon 3% 33% 33% melting Siemensprocess thin filmsi CzochralskiSi block casting ribbon 33% wafering 33% wafering Institut 3% für 33% Solarenergieforschung 100% wafer Hameln costs per area! Layer transfer replaces poly-cvd by thin film epitaxy! No melting of poly-si! No CZ-growth! No wafering

gradesilicon 3% 33% 33% melting Siemensprocess thin filmsi CzochralskiSi block casting ribbon 33% wafering 33% wafering Institut 3%

19 Layer deposotion: status and perspective low-cost epitaxy is the problem to solve

20 Status porous Si: Electro-chemical etching of 6 wafers p-type Si wafer HF:H 2 O + Pt porous Si HF:H 2 O Pt Porosity 20 % Porosity > 50% 1 µm Substrate! Important: tunnel and non-porous edge to stabalize! 12 µm of Si substrate lost per cycle (5 µm, Fave et al., 2006)! Etch time 55 s/cell (perspective 25 s)! Batch processing demonstrated with 2 wafers (perspective 10 wafers 2.5 s/cell)

Important: tunnel and non-porous edge to stabalize!

21 Status epitaxy: AP-CVD on 6 Si wafers with porous Surface! 10-fold substrate use demonstrated! No lifetime degradation! 85% yield for transfer of 145 pieces of 6 -wafers! Layer thickness 8 to 25 µm (perspective 5 µm)! Growth rate 1 µm/min (perspective 2.5 µm/min -> 2 min/cell)! Batch of 100 wafer -> 1.2 s/cell

22 Various other epitaxy techniques under investigation Photos: centrotherm! Epitaxy in a LP-CVD reactor (IMEC) -Growth rate 0.2 µm/min -2 s /cell in a batches of 200 in 4 tubes! Epitaxy in an in-line reactor (Fraunhofer ISE)! Epitaxy on large areas (ZAE Bayern)

23 Large-area Silicon epitaxy system (ZAE Bayern group) T. Kunz et al., Proc. 4th WCPEC, (Hawaii, 2006) p ! Convection-assisted deposition (CoCVD)! Substrate size up to 43 cm x 43 cm 200 flow profile Substrate x-position / mm outlet α inlet α = 30 α = 60 α = 90 v / (m/s)

24 Cell and module technology takes full advantage of current developments for high efficiency wafer cells

25 Future cell: 10 µm x 15.6 x15.6 cm 2 layer transfer cell with η =18% Rear junction & back contacted 1 2 n + -type SiN p-type Al/Ag Cell-sized carrier Local contacts p + -type a-si Structured Al contact 3 Soldered tab 4

26 1 A-Si passivated rear-junction and back-contacted PSI-mini-module SiN a-si n + -type emitter p-type base B. Terheiden et al., 21st EU-PVSEC, (Dresden, 2006) Structured by shadow mask " Access to contacts by etching " Module area 9.1 x 9.0 cm 2 Thickness 25 µm V OC = 626 mv per cell J SC = 28.4 ma/cm 2 FF = 67.3 % η = 12.0 %

27 2 Wafer cell with evaporated local contacts by COSIMA " Identical processing on n- type and p-type Si by COSIMA " PECVD-equipment available " Evaporation-equipment feasible " 20.5 % on 2 x 2 cm 2 FZ V oc = 655 mv J sc = 38.6 ma/cm 2 S = 120 cm/s H. Plagwitz, M. Schaper, A. Wolf, R. Meyer, J. Schmidt, B. Terheiden, and R. Brendel, Proc. 20th EU-PVSEC, (2005), p. 725.

28 Structured Al contact by laser technology Al/Ag on Si lasered trench " Laser structuring of an Ag-etch barrier " Etching of Al Al/Ag on Si Si-surface 3

29 3 Laser structured Al in RISE wafer solar cell (W = 200 µm) " 20.0 %* on 9 x 9.3 cm 2 FZ V oc = 655 mv J sc = 38.6 ma/cm 2 " 22.0 %* on 2 x 2 cm 2 FZ V oc = 662 mv J sc = 41.7 ma/cm 2 *independendly confirmed P. Engelhart et al., Progress in Photovoltaics, (2006).

30 4 PSI-transfer module with laser soldered interconnects Cu Sn96.5Ag3.5 Si Ag Al " Module with four cells " Lead-free soldered " Result: Cell area = 92 cm 2 Si thickness 26 µm V oc = 2.33 V J sc = 728 ma FF = 76.1 % η = 14.0 % M. Gast, M. Koentges, and R. Brendel Progr. in Photovoltaics, (2007), in press.

31 Do you want to join us? Contact for open post doc or PhD positions

32 Good reasons for pushing layer transfer! 14.1% efficiency with 26 µm on 95 cm 2 demonstrated! 10-fold use of substrate wafer demonstrated! New soft processiong techniologies such as COSIMA, laser structuring and laser soldering pave the way for higher efficiencies.! Layer transfer benefits form the fact that such soft processing technologies are currently under development for high-efficiency wafer cells.! High efficiency (18%) with little Si (< 1 g/w p ) is feasible.! This 10-fold reduction of Si consumption reduces vulnarability to Si-supply shortages. Presentation may be down loaded soon from

33 Acknowledgements! Results of project finished in March 2006! Federal Ministry for the Environment, Nature Conservation and Nuclear Safety! AZUR Space Solar Power GmbH! Robert Bosch GmbH

Silicon Wafer Solar Cells

Silicon Wafer Solar Cells Armin Aberle Solar Energy Research Institute of Singapore (SERIS) National University of Singapore (NUS) April 2009 1 1. PV Some background Photovoltaics (PV): Direct conversion