2003 THRU 2024 HIGH-VOLTAGE, HIGH-CURRENT DARLINGTON ARRAYS ABSOLUTE MAXIMUM RATINGS FEATURES

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1 THRU Data Sheet 9F Dwg. No. A-99 Note that the ULNxxA series (dual in-line package) and ULNxxL series (small-outline IC package) are electrically identical and share a common terminal number assignment. ABSOLUTE MAXIMUM RATINGS Output Voltage, V CE (ULNxA and ULNxL)... V (ULNxA and ULNxL)... 9 V Input Voltage, V IN... V Continuous Output Current, I C... ma Continuous Input Current, I IN... ma Power Dissipation, P D (one Darlington pair).... W (total package)... See Graph Operating Temperature Range, T A... - C to +8 C Storage Temperature Range, T S... - C to + C Ideally suited for interfacing between low-level logic circuitry and multiple peripheral power loads, the Series ULNxxA/L high-voltage, high-current Darlington arrays feature continuous load current ratings to ma for each of the seven drivers. At an appropriate duty cycle depending on ambient temperature and number of drivers turned ON simultaneously, typical power loads totaling over W ( ma x 7, 9 V) can be controlled. Typical loads include relays, solenoids, stepping motors, magnetic print hammers, multiplexed LED and incandescent displays, and heaters. All devices feature open-collector outputs with integral clamp diodes. The ULNA/L and ULNA/L have series input resistors selected for operation directly with V TTL or CMOS. These devices will handle numerous interface needs particularly those beyond the capabilities of standard logic buffers. The ULNA/L and ULNA/L have series input resistors for operation directly from 6 to V CMOS or PMOS logic outputs. The ULNA/L and ULNA/L are the standard Darlington arrays. The outputs are capable of sinking ma and will withstand at least V in the OFF state. Outputs may be paralleled for higher load current capability. The ULNA/L and ULNA/L will withstand 9 V in the OFF state. These Darlington arrays are furnished in 6-pin dual in-line plastic packages (suffix A ) and 6-lead surface-mountable SOICs (suffix L ). All devices are pinned with outputs opposite inputs to facilitate ease of circuit board layout. All devices are rated for operation over the temperature range of - C to +8 C. Most (see matrix, next page) are also available for operation to - C; to order, change the prefix from ULN to ULQ. FEATURES TTL, DTL, PMOS, or CMOS-Compatible Inputs Output Current to ma Output Voltage to 9 V Transient-Protected Outputs Dual In-Line Plastic Package or Small-Outline IC Package x = digit to identify specific device. Characteristic shown applies to family of devices with remaining digits as shown. See matrix on next page.

2 THRU DEVICE PART NUMBER DESIGNATION V CE(MAX) V 9 V I C(MAX) ma ma Logic Part Number V ULNA* ULNA* TTL, CMOS ULNL* ULNL 6- V ULNA* ULNA CMOS, PMOS ULNL* ULNL PARTIAL SCHEMATICS *Also available for operation between - C and +8 C. To order, change prefix from ULN to ULQ. ULNxA/L (Each Driver) COM.7K 7.K K ULNxA/L (Each Driver).K 7.K K Dwg. No. A-96 COM ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS..... SUFFIX 'A', R = 6 C/W θja SUFFIX 'L', R = 9 C/W θja 7 AMBIENT TEMPERATURE IN C Dwg. GP-6A Dwg. No. A-9898A X = Digit to identify specific device. Specification shown applies to family of devices with remaining digits as shown. See matrix above. Northeast Cutoff, Box 6 Worcester, Massachusetts 6-6 (8) 8- Copyright 97, 998 Allegro MicroSystems, Inc.

3 THRU Types ULNA, ULNL, ULNA, and ULNL ELECTRICAL CHARACTERISTICS at + C (unless otherwise noted). Test Applicable Limits Characteristic Symbol Fig. Devices Test Conditions Min. Typ. Max. Units Output Leakage Current I CEX AAll V CE = V, T A = C < µa V CE = V, T A = 7 C < µa B ULNA/L V CE = V, T A = 7 C, V IN =. V < µa A Collector-Emitter V CE(SAT) ll I C = ma, I B = µa.9. V Saturation Voltage l C = ma, I B = µa.. V I C = ma, I B = µa..6 V Input Current I IN(ON) ULNA/L V IN =.8 V.9. ma ULNA/L V IN =. V.. ma V IN = V.. ma I IN(OFF) A ll l C = µa, T A = 7 C 6 µa Input Voltage V IN(ON) ULNA/L V CE =. V, l C = ma. V V CE =. V, I C = ma.7 V V CE =. V, l C = ma. V ULNA/L V CE =. V, l C = ma. V V CE =. V, l C = ma 6. V V CE =. V, I C = 7 ma 7. V V CE =. V, l C = ma 8. V Input Capacitance C IN A ll pf Turn-On Delay t PLH 8 All. E IN to. E OUT.. µs Turn-Off Delay t PHL 8 All. E IN to. E OUT.. µs A A Clamp Diode I R 6 ll V R = V, T A = C µa Leakage Current V R = V, T A = 7 C µa Clamp Diode V F 7 ll I F = ma.7. V Forward Voltage Complete part number includes suffix to identify package style: A = DIP, L = SOIC.

4 THRU Types ULNA, ULNL, ULNA, and ULNL ELECTRICAL CHARACTERISTICS at + C (unless otherwise noted). Test Applicable Limits Characteristic Symbol Fig. Devices Test Conditions Min. Typ. Max. Units Output Leakage Current I CEX AAll V CE = 9 V, T A = C < µa V CE = 9 V, T A = 7 C < µa B ULNA/L V CE = 9 V, T A = 7 C, V IN =. V < µa A Collector-Emitter V CE(SAT) ll I C = ma, I B = µa.9. V Saturation Voltage l C = ma, I B = µa.. V I C = ma, I B = µa..6 V Input Current I IN(ON) ULNA/L V IN =.8 V.9. ma ULNA/L V IN =. V.. ma V IN = V.. ma I IN(OFF) A ll l C = µa, T A = 7 C 6 µa Input Voltage V IN(ON) ULNA/L V CE =. V, l C = ma. V V CE =. V, I C = ma.7 V V CE =. V, l C = ma. V ULNA/L V CE =. V, l C = ma. V V CE =. V, l C = ma 6. V V CE =. V, I C = 7 ma 7. V V CE =. V, l C = ma 8. V Input Capacitance C IN A ll pf Turn-On Delay t PLH 8 All. E IN to. E OUT.. µs Turn-Off Delay t PHL 8 All. E IN to. E OUT.. µs A A Clamp Diode I R 6 ll V R = 9 V, T A = C µa Leakage Current V R = 9 V, T A = 7 C µa Clamp Diode Forward Voltage V F 7 ll I F = ma.7. V Complete part number includes suffix to identify package style: A = DIP, L = SOIC. Northeast Cutoff, Box 6 Worcester, Massachusetts 6-6 (8) 8-

5 THRU TEST FIGURES FIGURE A FIGURE B FIGURE V CE V CE µa µa h FE = I C I B I CEX V IN I CEX V I B V CE I C Dwg. No. A-979A Dwg. No. A-97A Dwg. No. A-97A FIGURE FIGURE FIGURE V CE µa I IN I IN I C V IN ma µa V IN V V V CE I C Dwg. No. A-97A Dwg. No. A-97A Dwg. No. A-97A FIGURE 6 FIGURE 7 FIGURE 8 V R INPUT % V IN % µa I F I V R V F OUTPUT t phl % t phl % + V V in Dwg. No. A-97A Dwg. No. A-976A ULNX* ULNX*. V V PULSE GENERATOR PRR = KHz DC = % INPUT 9 Ω Ω Ω OUT pf * Complete part number includes a final letter to indicate package. X = Digit to identify specific device. Specification shown applies to family of devices with remaining digits as shown.

6 THRU ALLOWABLE COLLECTOR CURRENT AS A FUNCTION OF DUTY CYCLE (Dual In-line-Packaged Devices, Suffix A ) 6 TYPICAL APPLICATIONS +VSS 6 +V OUTPUT CURRENT IN ma/channel NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY 7 6 TA = +7 C RθJA = 6 C/W PMOS OUTPUT Dwg. No. A DUTY CYCLE IN PER CENT Dwg. GP-7 +VDD 6 +V (Small-Outline-Packaged Devices, Suffix L ) 6 OUTPUT CURRENT IN ma/channel SATURATION VOLTAGE AS A FUNCTION OF COLLECTOR CURRENT 6 NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY 7 6 TA = +7 C RθJA = 9 C/W 6 8 DUTY CYCLE IN PER CENT Dwg. GP-A 6 CMOS OUTPUT 6 Ω 7 Ω 8 9 N9 Dwg. No. A-96A COLLECTOR CURRENT AS A FUNCTION OF INPUT CURRENT COLLECTOR CURRENT IN ma TYPICAL MAX. SATURATION VOLTAGE COLLECTOR CURRENT IN ma TYPICAL MAX. REQ'D INPUT CURRENT.... COLLECTOR-EMITTER SATURATION VOLTAGE Dwg. GP-67 6 INPUT CURRENT IN µa Dwg. GP-68 Northeast Cutoff, Box 6 Worcester, Massachusetts 6-6 (8) 8-

7 THRU TYPICAL APPLICATIONS +V CC +V 6 INPUT CURRENT AS A FUNCTION OF INPUT VOLTAGE Types ULNA, ULNL, ULNA, and ULNL.. TTL OUTPUT INPUT CURRENT IN ma I IN... MAXIMUM TYPICAL AREA OF NORMAL OPERATION WITH STANDARD OR SCHOTTKY TTL Dwg. No. A-96A INPUT VOLTAGE Dwg. GP-69 +VCC 6 +V Types ULNA, ULNL, ULNA, and ULNL. TTL OUTPUT RP INPUT CURRENT IN ma IIN... MAXIMUM TYPICAL Dwg. No. A-, INPUT VOLTAGE Dwg. GP-69-

8 THRU 6 PACKAGE DESIGNATOR A Dimensions in Inches (controlling dimensions) MAX MIN. MAX. MIN Dimension in Millimeters (for reference only) 9.. Dwg. MA--6A in MAX MIN. MAX.9 MIN Dwg. MA--6A mm NOTES:. Leads, 8, 9, and 6 may be half leads at vendor s option.. Lead thickness is measured at seating plane or below.. Lead spacing tolerance is non-cumulative.. Exact body and lead configuration at vendor s option within limits shown. Northeast Cutoff, Box 6 Worcester, Massachusetts 6-6 (8) 8-

9 THRU PACKAGE DESIGNATOR L Dimensions in Inches (for reference only) TO MIN. Dimension in Millimeters (controlling dimensions) 6 9 Dwg. MA-7-6 in TO MIN. Dwg. MA-7-6A mm NOTES:. Lead spacing tolerance is non-cumulative.. Exact body and lead configuration at vendor s option within limits shown.

10 THRU The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Northeast Cutoff, Box 6 Worcester, Massachusetts 6-6 (8) 8-