DC Distributed Power Systems

Transcription

1 DC Dstrbuted Power Systems Aalyss Desg ad Cotrol for a Reewable Eergy System Per Karlsso Doctoral Dssertato Idustral Electrcal Egeerg Departmet of Idustral Electrcal Egeerg ad Automato

2 Departmet of Idustral Electrcal Egeerg ad Automato Lud Uversty Box 8 SE- LUND SWEDEN ISBN X CODEN:LUTEDX/(TEIE-33)/-/() Per Karlsso Prted Swede by Meda-Tryc Lud Uversty Lud

3 Abstract Reewable eergy systems are lely to become wde spread the future due to evrometal demads. As a cosequece of the dspersed ature of reewable eergy systems ths mples that there wll be a dstrbuted geerato of electrc power. Sce most of the dstrbuted electrcal eergy sources do ot provde ther electrc power at le frequecy ad voltage a DC bus s a useful commo coecto for several such sources. Due to the dffereces output voltage amog the sources depedg o both the type of source ad ther actual operatg pot the sources are coected to the DC power system va power electroc coverters. The teto behd the preseted wor s ot to replace the exstg AC power system but to clude local DC power systems. The AC ad DC power systems are coected at some pots the etwor. The reewable eergy sources are wea compared to the preset hydro power ad uclear power plats resultg a eed of power codtog before the reewable eergy s fed to the trasmsso les. The beeft of such a approach s that power codtog s appled o a cetral level.e. at the terface betwee the AC ad DC power systems. The thess starts wth a overvew of related wor. Preset DC trasmsso systems are dscussed ad vestgated smulatos. The dfferet methods for load sharg ad voltage cotrol are dscussed. Especally the voltage droop cotrol scheme s examed thoroughly. Sce the droop cotrol method does ot requre ay hgh-speed commucato betwee sources ad loads ths s cosdered the most sutable for DC dstrbuted power systems. The voltage feed bac desg of the cotroller also results a specfcato of the DC bus capactors (equvalets to DC l capactors of sgle coverters) eeded for flterg. If the coverters the DC dstrbuto system are equpped wth capactors selected from ths desg crtero ad f the DC bus mpedace s eglected the source coverters share the total load equally per ut.

4 The same DC dstrbuto bus cofgurato s studed a wd power applcato. Especally the dyamc propertes of load-source teractos are hghlghted. They are terestg sce the sources are cosdered wea for a dstrbuted power system. Ths s llustrated wth smulatos where the power s fed from wd turbes oly ad costat power loads are cotrolled at the same tme as the DC bus voltage level. The wd power geerators are modeled as permaet-maget sychroous maches. The cotroller eeded for the maches cludg posto estmato ad feld weaeg s dscussed. To cotrol the DC bus voltage the avalable wd power must be hgher tha the power cosumed by the loads ad the excess power removed by ptch agle cotrol. Ptch agle cotrol s a comparably slow process ad therefore the DC bus voltage cotroller must hadle the traset power dstrbuto. Persoal safety ad preveto of property damage are mportat factors of covetoal AC power systems. For the vestgated DC power system ths s maybe eve more mportat due to the fact that the star pot of the sources ad loads s left ugrouded or grouded through hgh mpedace. The dffculty of detectg groud faults arses from the fact that the AC sources ad loads are ugrouded or have hgh mpedace to groud order to effectvely bloc zero-sequece currets flowg betwee the AC systems. A groudg scheme for the DC dstrbuto system together wth algorthms for detecto of groud faults are preseted. The proposed method detects groud faults o both the AC ad DC sdes ad s exteded to cover short crcut faults wth a mor wor effort. Two schemes for hgh voltage tercoecto of DC systems are studed. Oe of them provdes galvac solato whch s a advatage sce elevated voltage mght appear the DC systems otherwse the case of a groud fault the hgh voltage tercoecto. Expermetal verfcatos follow the theoretcal vestgatos troduced above. Frst dyamc propertes are studed ad the behavour predcted from theoretcal aalyss ad smulatos s verfed. The load sharg s vestgated. Also ths vestgato the expermetal results agree wth the smulated. v

5 Acowledgemets Frst I would le to tha my colleague ad fred Jörge Svesso who I have wored wth the last three years. I would also le to express my scere grattude to my fred ad former colleague Mart Bojrup who I wored wth durg I am very grateful to my two metors Professor Lars Gertmar ad Professor Sture Ldahl. Both Lars ad Sture have tme to dscuss all ds of topcs ot oly techcal. I would also le to tha my supervsors Professor Mats Alaüla ad Professor Gustaf Olsso. Professor Alaüla who has bee my ma supervsor has show much ethusasm for power electrocs ot strctly focusg o the research project. Eve f hs schedule s tght Mats has always tme to gve a helpg had. Mats has also ecouraged me to partcpate courses ad meetgs whch s greatly acowledged. Gustaf s also head of the departmet. As such he strves hard to provde a fredly atmosphere at the departmet whch has bee very successful. The steerg commttee cludg the four professors above ad Dr Magus Ae Dr Olof Samuelsso ad Dr Ja Svesso has cotrbuted wth valuable commets ad dscussos. Ths has ehaced my wor ad s greatly acowledged. I would also le to tha Aders Lasso ABB Utltes AB ad Ulf Thoré Sydraft AB from the steerg commttee of the former research project I was volved together wth Mart Bojrup. Professor Frede Blaabjerg ad Dr Stg Mu Nelse both at Aalborg Uversty Demar have also meat a lot to me. I 996 they asssted me whe I evaluated the SABER smulato software. Professor Blaabjerg also evaluated my Lcetate s thess o Quas Resoat DC L Coverters. v

6 I would le to express my grattude to the staff at IEA. Eve f all the people at the departmet are helpful ad fredly there are those that I owe a specal tha. Dr Chrsta Rose s a very good fred ad a perso you ca dscuss aythg wth. He has also proof read several of my artcles whch s greatly acowledged. Also at IEA Getachew Darge ad Begt Smosso have provded practcal help for electroc desgs. I th that Begt has at least oe catalogue or data boo for every apparatus ad compoet. I must tha Dr Ulf Jeppsso who used to mata the UNIX-system wth softwares le SABER ad ACE ad owadays taes care of the ecoomcal ssues of the departmet. Thas to the former Assocate Professor at IEA Stg Ldqust for always beg ce. I am very thaful to Magus Mats Lars Chrsta Ja ad Jörge for proof readg my thess. I have also had the prvlege to wor together wth Aa Nlsso Departmet of Buldg ad Evrometal Techology Lud Uversty. Aa does ot hestate to teach evrometal ssues a advaced course o power electrocs or preset the same materal o a coferece o power electrocs. I also tha the staff at ABB Uversty Ludva especally Ewa Wström ad Elly Hartgs for ecouragg me to partcpate ther courses o HVDC ad HVDC Lght. I do ot ow how to tha my famly eough. My parets Sv ad Axel have always ecouraged me to study wthout puttg ay requremets o the result. They have also helped me wth all ds of practcal ssues ad facal support for my udergraduate studes. I caot mage that ths would have bee possble wthout your help thas aga. My dear ad beloved Aa has ehaced my lfe to a large extet. Though I sped too much tme at the departmet Aa does ot compla. I hope that I sometme ca retur ths patece whe she eeds t. The Cotrol of Reewable Eergy Sources (CORE) project s facally supported by DESS (Delegatoe för Eergförsörjg SydSverge The Board for Eergy Supply Souther Swede). Ths support s gratefully acowledged. Per Karlsso v

7 Cotets CHAPTER INTRODUCTION.... Objectves.... Cotrbutos Outle of the thess Publcatos Prevous wor Specfcato of a dstrbuted power system... CHAPTER EXISTING DC POWER SYSTEMS.... HVDC.... VSC based HVDC... 6 CHAPTER 3 DC BUS VOLTAGE CONTROL Ivestgated system DC bus model Cotroller structure Cable mpedace Load sharg Cocludg remars... 6 CHAPTER 4 WIND POWERED DC BUS Ptch agle cotrol Droop offset cotrol Speed estmato Feld weaeg Smulatos... 7 v

8 CHAPTER 5 FAULT DETECTION AND CLEARANCE Groudg ad fusg Fault stuatos Detecto ad selectvty Smulatos CHAPTER 6 DC TRANSMISSION The bac-to-bac structure The DAB structure Proposed tercoecto structure... 4 CHAPTER 7 MEASUREMENTS Expermetal set-up Dyamc propertes Load sharg... 3 CHAPTER 8 CONCLUSIONS Summary of results Future wor REFERENCES...39 APPENDIX A MODULATION...49 A. Modulato methods A. Vector represetato APPENDIX B VECTOR CONTROL...67 APPENDIX C CONVERTER LOSSES...7 APPENDIX D NORMALISATION...77 D. Base system for a sgle coverter D. Coverter data expressed per ut APPENDIX E NOMENCLATURE...83 v

9 Chapter Itroducto I ths chapter DC dstrbuted power systems (DPS) are troduced together wth a revew of the DC DPS state of the art techology. Reewable eergy systems are lely to become wde spread the future due to evrometal demads for example regardg polluto. Ths mples that there wll be a dstrbuted geerato of electrc power. Sce several of the dstrbuted electrcal eergy sources provde DC voltage several such sources mght be coected. Due to the dffereces output voltage amog the sources depedg o both the type of source ad ther actual operatg pot the sources are coected to the DC power system va power electroc coverters. It should be clear that the teto s ot to replace the exstg AC power system but to clude local DC systems [4]. These AC ad DC systems are coected at some pots the etwor. The beeft of such a approach arses from the fact that reewable eergy sources are wea compared to preset fossl fuel hydro power ad uclear power plats resultg a eed of power codtog before beg fed to the trasmsso les. Wth a DC dstrbuted system codtog ca be appled at a cetral level of the AC dstrbuto system close to the DC system coecto pots. Also several cosumer loads operate o DC (rectfed AC). Therefore DC dstrbuto could be used to omt the eed for trasformers ad rectfers every sgle load. The DC dstrbuted power system has varous ds of eergy storage added whch meas that t ca support earby customers durg AC power system falure or emergecy stuatos. Also sestve equpmet lely to be stalled future tellget buldgs also eeds eergy bacup.e. uterruptable

10 Chapter. Itroducto power supply (UPS) propertes. Ths s already use for example telecommucato sub-statos where bacup batteres are usually stalled. Aother example s gve [63] where a battery powered DC system s supplyg the AC system crcut breaer cotrol system. Of course relable operato of such systems s ecessary. A larger part of the power trasmsso etwor s lely to use hgh voltage drect curret (HVDC) trasmsso techology the future [4]. Also the recetly troduced medum voltage DC (MVDC) techology s lely to be used DC dstrbuted power systems [4]. Ths mples that future electrc power systems costtute a mxture betwee AC ad DC techology. A dstrbuted power system wth as much as several hudred power electroc coverters call for ew methods ad techologes both o the operator ad system level. Not oly a creased cotrol effort s requred but also the complexty of protecto systems wll crease the case of dspersed geerato [3]. Ths s true especally f autoomous operato of the dstrbuted power system s teded. Ths wor addresses cotrol ad stablty ssues of DC dstrbuted power systems together wth ther coectos to surroudg AC power systems sources ad loads. Also groudg ad ssues o fault detecto ad clearace are cosdered.. Objectves The ma objectve of ths wor s to study the cosequeces of large-scale corporato of power electroc coverters DC dstrbuted power systems. The ma objectve s splt to several sub-objectves all mperatve for a large-scale system. The frst ssue to treat s selecto of a sutable system voltage at least at the cosumer level. Stablty ad dyamc propertes of DC voltage cotrol are of great cocer. Requremets o hardware ad software should be stated so that the system could grow.e. addtoal coverters stalled a exstg system wthout system degradato. Voltage cotrol the case of wea sources should also be vestgated sce several of the reewable eergy sources possess low erta. Sutable groudg ad fault detecto schemes should be vestgated. Coecto of several DC systems should be vestgated. Oe mportat objectve s that the eed of commucato should be studed.

11 . Cotrbutos 3. Cotrbutos The cotrbutos of ths wor are gve Chapters 3 to 7 ad cocluded Chapter 8. The ma results are summarsed here. Sutable voltage levels are ot explctly dscussed the thess. Istead a DC bus voltage level sutable for 4 V AC sources ad loads s adopted. Ths s due to the fact that by dog so the proposed system voltage covers exstg cosumer loads. Future apparatus mght requre a dfferet load voltage level. To compesate ths shortcomg a large porto of the vestgato s made o a per ut (p.u.) bass. Therefore the results ca be used for ay DC bus voltage level. The coverters are frst specfed wth focus o teracto betwee the AC ad DC sdes. The a DC bus voltage droop cotroller s adopted. The demads o teracto together wth droop requremets gve a specfcato of the relato betwee rated power ad coverter DC sde flter.e. DC bus capactace for each coverter. The dyamc propertes are vestgated both by meas of stablty aalyss terms of root-locus ad large-sgal smulatos. It s foud that for reasoable DC bus cable parameters stablty s of mor cocer for the selected DC sde flter. I other words the requremets o teracto betwee put ad output of the coverters s stroger tha the stablty requremet. Voltage droop cotrol provdes autoomous load sharg mplyg that commucato s ot eeded. The selected mplemetato of the droop algorthm ad the cotroller parameters allow a arbtrary umber of coverters the DC system. Furthermore the already serted uts are ot altered f addtoal uts are corporated. A wd powered DC system s adopted to vestgate voltage cotrol ad load sharg the case of reewable eergy sources. I ths case a speed droop algorthm s developed. The dyamc propertes of speed ad voltage droop cotrol are vestgated. It s cocluded that low-speed commucato s beefcal for o-dspatchable sources. A fault detecto algorthm s developed. The algorthm s studed for dfferet levels of commucato ragg from oe to pot-to-pot commucato. A exstg coverter topology s adopted for tercoecto of DC systems. The same coverter topology s also used for power trasmsso. Voltage droop cotrol s adopted also here. Thus hgh-speed commucato s ot ecessary. However whe low-badwdth commucato s utlsed the system operator has the ablty to cotrol power flow. A laboratory set-up s desged to verfy voltage cotrol load sharg ad fault detecto.

12 4 Chapter. Itroducto.3 Outle of the thess Ths chapter cotas a bref troducto to the thess ad the academc wor preseted. A survey of prevous wor s also gve. Chapter revews classcal HVDC ad Voltage Source Coverter (VSC) based HVDC trasmsso systems. The study cludes smulatos where especally the harmoc cotet of the currets s compared. I Chapter 3 voltage ad power cotrol methods for the vestgated dstrbuted power system are developed. Ths aalyss also results a method for selecto of DC bus flter capactors. The steady state ad dyamc propertes of the selected cotrol scheme are vestgated for varyg cable parameters. Load sharg s vestgated for dfferet voltage cotrol methods. I Chapter 4 the same system but wth wea sources s vestgated. Here the DC power system s fed oly wth wd power ad stll costat power loads ca be suppled ad the DC bus voltage cotrolled. Persoal safety ad protecto of equpmet are mportat ssues for ay power system ad Chapter 5 s devoted to these topcs. The chapter starts wth a presetato of the groudg scheme ad typcal fault codtos. The the methods of fault detecto ad localsato are preseted ad verfed smulatos. I Chapter 6 coecto of DC dstrbuted systems s cosdered. The proposed scheme cotas a trasformer provdg galvac separato betwee dfferet DC systems. I Chapter 7 measuremet results verfyg dyamc propertes load sharg ad fault detecto are preseted. The wor s cocluded Chapter 8. MATLAB TM Power System Blocset s utlsed for the tme-doma smulatos of Chapter where thyrstor based coverters are cosdered. DYMOLA TM s utlsed for the tme-doma smulatos cludg trasstor based coverters.e. for the smulato of VSC based HVDC trasmsso Chapter ad all tme-doma smulatos Chapters 3 to 7. Large-sgal coverter models are used for smulatos vestgatg two-coverter systems ad DC trasmsso systems. Average coverter models are utlsed for smulatos where load sharg or fault detecto s vestgated. Dscrete-tme cotrollers are utlsed for both the large-sgal ad the average coverter models. MATLAB TM s used Chapter 3 for vestgato of stablty for dfferet cable parameters terms of root-locus of the poles. The smulatos the appedxes are all carred out MATLAB TM -SIMULINK TM.

13 .4 Publcatos 5.4 Publcatos The results preseted ths thess regard DC bus voltage cotrol ad fault detecto ad clearace foud Chapters ad 7. The ma results of these chapters are also preseted P. Karlsso ad J. Svesso "DC Bus Voltage Cotrol for Reewable Eergy Dstrbuted Power Systems" IASTED Power ad Eergy Systems Coferece PES Cof. Proc. Mara del Rey CA USA May 3-5 pp P. Karlsso ad J. Svesso "Fault Detecto ad Clearace DC Dstrbuted Power Systems" IEEE Nordc Worshop o Power ad Idustral Electrocs NORPIE worshop proc. Stocholm Swede Aug. -4 CD- ROM pages 6. P. Karlsso ad J. Svesso "DC Bus Voltage Cotrol for a Dstrbuted Power System" provsoally accepted for publcato IEEE trasactos o power electrocs paper o LP. P. Karlsso ad J. Svesso "Voltage Cotrol ad Load Sharg DC Dstrbuto Systems" submtted to Europea Coferece o Power Electrocs ad Applcatos EPE 3 Toulouse Frace Sept The thess author has also authored the publcato J. Svesso ad P. Karlsso "Wd Farm Cotrol Software Structure" Iteratoal Worshop o Trasmsso Networs for Offshore Wd Farms worshop proc. Stocholm Swede Apr. - proceedg pages 5. the same research project. The cotrbuto made by the thess author the last paper s mor. The prevous wor o off-board battery chargers for electrc vehcles also part of the research wor s reported P. Karlsso M. Bojrup M. Alaüla ad L. Gertmar "Effcecy of Off-Board Hgh Power Electrc Vehcle Battery Chargers wth Actve Power Le Codtog Capabltes" Europea Coferece o Power Electrocs ad Applcatos EPE 97 Cof. Rec. Trodhem Norway Sept vol. 4 pp

14 6 Chapter. Itroducto M. Bojrup P. Karlsso B. Smosso ad M. Alaüla "A Dual Purpose Battery Charger for Electrc Vehcles" IEEE Power Electrocs Specalsts Coferece PESC 98 Cof. Rec. Fuuoa Japa May vol. pp M. Bojrup P. Karlsso M. Alaüla ad L. Gertmar "A Multple Rotatg Itegrator Cotroller for Actve Flters" Europea Coferece o Power Electrocs ad Applcatos EPE 99 Cof. Rec. Lausae Swtzerlad Sept CD-ROM pages 9. P. Karlsso M. Bojrup M. Alaüla ad L. Gertmar "Zero Voltage Swtchg Coverters" IEEE Nordc Worshop o Power ad Idustral Electrocs NORPIE worshop proc. Aalborg Demar Ju. 3-6 pp P. Karlsso M. Bojrup M. Alaüla ad L. Gertmar "Desg ad Implemetato of a Quas-Resoat DC L Coverter" Europea Coferece o Power Electrocs ad Applcatos EPE Cof. Rec. Graz Austra Aug. 7-9 CD-ROM pages. Oly mor parts of the wor reported the secod ad thrd publcatos above are attrbuted the author of ths thess. The wor o resoat coverters reported the other publcatos above s also the bass of the Lcetate s thess P. Karlsso "Quas Resoat DC L Coverters - Aalyss ad Desg for a Battery Charger Applcato" Lcetate thess Departmet of Idustral Electrcal Egeerg ad Automato Lud Isttute of Techology Lud Swede November 999. Ths wor was evaluated by Professor Frede Blaabjerg at the Departmet of Eergy Techology Aalborg Uversty Demar. Besdes the publcatos wth the research projects aother publcato related to power electrocs educato has bee preseted A. Nlsso P. Karlsso ad L. Gertmar "Evrometal Egeerg the Power Electrocs Educato" Europea Coferece o Power Electrocs ad Applcatos EPE Cof. Rec. Graz Austra Aug. 7-9 CD-ROM pages. Less tha half of the wor of ths paper s attrbuted the thess author.

15 .5 Prevous wor 7.5 Prevous wor Ths secto provdes a lterature survey of prevous wor o reewable eergy sources ad dstrbuted power systems whch the most relevat prevous wor s dscussed. A classfcato of the papers s made based o the ature of the refereces eve though several of them cover more tha oe topc. However the refereces are sorted uder the topc whch the thess author fd most terestg the cotext of the rest of the thess. Dstrbuted eergy systems Several argumets for dstrbuted power systems are lsted [3]. Amog these trasmsso capablty saturato of cetralsed power systems ad related stablty problems seem most mportat. The addtoal tellgece eeded to cotrol protect ad mata dstrbuted power systems s focused [3]. The future maret of (DC) dstrbuted power systems s dscussed [33] where t s cocluded that the growg maret cludes computer mltary/aerospace ad commucato applcatos. It s also stated that dstrbuted power systems are more costly tha cetralsed. Note that [3] the dstrbuted system s part of a ato wde power trasmsso/dstrbuto system cludg dspersed geerato. I [33] the dstrbuted system teded s restrcted to supply power to electroc equpmet le sde a sgle computer. Power electrocs for use reewable eergy applcatos are dscussed [4]. Also some beefts ad drawbacs assocated wth reewable eergy sources are dscussed. Photovoltac fuel cell ad wd eergy systems are revewed brefly. Small-scale hydro pump statos or battery bas for electrc eergy storage are however ot dscussed [4]. Stll they are cluded the prcpal scheme of a dstrbuted power system together wth flywheel ad supercoductg magetc eergy storages. DC dstrbuted power systems Some of the lterature studed does ot ft to the study though terestg. For example [39][4][4][4][66] vestgate a hgh curret low voltage DC mesh wth thyrstor based coverters. I [39][4][4] a supercoductg power system s cosdered whereas a dustral power dstrbuto system wth heret UPS propertes s cosdered [4][66]. The teded system

16 8 Chapter. Itroducto mght cota several hudred thyrstor based sources (rectfers) ad loads (verters) but the smulated systems are of cosderably lower complexty. I [39] a DC power system formed by oe rectfer ad three verters s studed. I [4][4][4][66] three rectfers are used as sources. Sce three sources are preset load sharg has to be cosdered. I all these cases DC voltage droop cotrol s used to gve approprate load sharg. Ths meas that a voltage droop characterstc s assged to each source. I [4][66] the LVDC mesh s smplfed to a rg bus ad [4] a supercoductg eergy storage (SMES) s added to the system. The paper [4] focuses o vestgato of the droop scheme. It s stated that ths wors well for supercoductg etwors. However the performace of a osupercoductg etwor s questoed. I the lterature the term power electroc buldg bloc (PEBB) s sometmes used as a term for geerc buldg blocs for power coverso cotrol ad dstrbuto wth cotrol tellgece ad autoomy. The wor preseted [] proposes a dstrbuted dgtal cotroller for PEBBs. The ma requremets ad desred features of such a cotroller s dscussed []. The proposed cotroller s based o compoets presetly avalable ad used other applcatos. A 6 W frot-ed source coverter module ad a 3 W load coverter module are desged [36]. The source coverter s desged for zero voltage trasto (ZVT) techque ad the load coverter utlses zero voltage swtchg (ZVS) techque. The source coverter s formed by a sgle-phase rectfer equpped wth a power factor corrector (PFC).e. followed by a boost coverter. The DC system voltage equals 48 V. Expermetal results are cluded [36]. I [46] coverter topologes sutable for DC dstrbuted power systems are evaluated. Especally source sde frot-ed boost rectfer caddates are vestgated but also load sde coverter modules. Voltage cotrol ad load sharg There are bascally two dfferet methods to acheve load sharg. Oe of the methods s referred to as the droop cocept ad the other as the master/slave cocept. For the droop cocept a fte loop ga for the DC voltage cotroller s adopted. A droop characterstc s obtaed from the trasfer fucto slope the P-V plae at the desred DC bus voltage. Sce ths droop characterstc appears as a egatve slope the P-V plae load sharg s obtaed. The

17 .5 Prevous wor 9 qualty of load sharg s determed by the egatve slope of the droop characterstc.e. for a steep slope load sharg s good but voltage regulato s poor. O the other had for a shallow slope load sharg s poor but voltage regulato s good. Therefore a trade-off betwee voltage regulato ad load sharg has to be made for the droop cocept. I the master/slave cocept oly oe of the source coverters s cotrollg the DC bus voltage. The other source coverters are curret cotrolled. Ths results a stff DC bus voltage regulato ad a fully cotrollable load sharg. The papers [38][5][58] gve a overvew of these parallelg methods. Accordg to [5] fve dfferet droop schemes exst. The frst s based o the use of coverters wth heret droop feature. The secod scheme s based o voltage droop due to seres resstors. The thrd scheme s called voltage droop va output curret feedbac. The fourth scheme s referred to as curret mode wth low DC ga. The ffth s schedulg cotrol va a o-lear ga. The beefts of the droop schemes are the ease of mplemetato ad expaso ad that o commucato betwee the coverters (.e. supervsory cotrol) s eeded. Ths gves hgh modularty ad relablty. The ma dsadvatages are that the voltage regulato s degraded to acheve the droop characterstc ad that the curret sharg s poor due to ope loop cotrol of the etre system. The ext large group detfed [5] s referred to as actve curret sharg schemes. Commo to these schemes s that a addtoal cotrol loop s used to provde curret sharg. Accordg to [5] three dfferet actve curret sharg cotrol structures are used for parallel coverter systems. The frst cotrol structure s called er loop regulato (ILR). The secod cotrol structure s referred to as outer loop regulato (OLR). The thrd structure reles o a exteral cotroller (EC). EC mples a large umber of tercoectos betwee the coverters. Ths meas that both the modularty ad relablty mght be degraded. It s however stated [5] that the rapd developmet of dstrbuted power systems mples that ths techque should be examed a ew lght. The hgh level supervsory cotroller ca be redudat ad the coverter cells are oly resposble for gatg ad fault dcato. Ths method s lely to yeld the hghest performace because of ts possblty of terleavg [5]. Also sx curret programmg (CP) methods for actve curret sharg schemes are revewed [5]. Of these sx three are average ad three are

18 Chapter. Itroducto master/slave curret programmg methods. Seve methods to operate multple DC-DC coverters parallel are gve [38]. I [58] four methods to acheve load sharg parallel coverter systems are gve. I [9] load sharg propertes are studed by examg the output plae (output curret versus voltage). A small-sgal model s developed for the vestgato. Smulatos ad expermets verfy the theoretcal results. The output plae s derved from equatos for curret programmed coverters [3]. The output plae s verfed large-sgal smulatos ad expermets. Droop load sharg s evaluated [37]. Oe of the mportat coclusos made [37] s that the droop method requres precse cotrol of the tal output voltage. It s also stated that the ma advatages of the droop cotrol method compared to other coverter parallelg schemes are the ease of mplemetato ad that commucato by meas of cotrol-wre coecto s ot requred. A droop fucto wth a programmed droop resstace equal to the equvalet seres resstace (ESR) of the output capactor s proposed [6]. Load sharg wth the selected droop fucto s vestgated by meas of smulatos ad expermets. A parallelg scheme called cetral-lmt cotrol closely related to master/slave cotrol s preseted [64] ad revewed [58]. The ma dfferece betwee master/slave ad cetral-lmt cotrol s that for the latter all the sources regulate the load coverter DC bus voltage. Autoomous master/slave curret sharg s used [6] for two source coverters coected parallel. A small-sgal model for the two source coverters together wth ther cotrollers s derved. A curret sharg algorthm s also preseted. Curret sharg cotrol s ecessary sce otherwse small dffereces the source coverter parameters would cause severe load mbalace. Also the voltage loop s vestgated. Desg of the compesators s dscussed but oly a few actual results are cocluded. I a stuato where several coverters coected to the DC dstrbuto bus that all cotrol the voltage precsely to the referece at ther respectve coecto pot load sharg amog sources s ot cotrolled. Istead load sharg s etrely determed by the dstrbuto bus mpedace [75]. I [76] t s stated that dstrbuted power systems have better performace tha cetralsed. Moreover t s stated that the sources coected parallel to the DC bus (frot-ed boost rectfers) should share the load to esure proper

19 .5 Prevous wor operato. I [76] the droop method s used together wth ga schedulg whch s sad to gve a robust desg terms of source-load teracto.e. good load sharg ad good voltage regulato for a modular desg approach. Accordg to [76] the ma problems of master/slave load sharg are that fast commucato s requred ad that a sgle pot falure ca dsable the etre system. Also all modules are cotrol depedet. Sx mportat ssues are addressed [76]. The frst s stablty for example terms of teractos betwee parallel coverters (especally the case of three-phase sources due to the appearace of zero-sequece currets). The secod mportat ssue s load sharg whe several sources are coected parallel to the DC dstrbuto bus. The thrd ssue s modularty.e. the ablty to maufacture ad mata the DC system. The fourth ssue s autoomous cotrol ehacg modularty ad provdg creased system relablty ad redudacy. The ffth ssue s DC bus voltage cotrol whch s mperatve. The sxth ad last ssue detfed [76] s the source output mpedace whch deed affect several of the other ssues for example the teracto betwee coverters coected to the DC system. The ga-schedulg method utlsed [76] s based o a modfed droop method where the voltage loop ga s creased for creasg output power such a way that the voltage error decreases compared to the case wth a costat ga droop fucto. Accordg to [76] both DC bus voltage cotrol ad load sharg show better performace compared to master/slave cotrol. A terestg opto ot dscussed [76] s to use a adaptve cotroller for the DC bus voltage cotrol. I [44] a droop load sharg scheme s vestgated where the DC bus voltage referece s adaptvely cotrolled for each coverter order to mprove voltage regulato ad load sharg. Small-sgal stablty based o mpedace specfcato A system wth a arbtrary umber of DC-DC source coverters paralleled usg master/slave cotrol s vestgated [6]. Small-sgal stablty ad dyamc performace are vestgated. Also a curret sharg compesator s developed. The compesator s desged the frequecy-doma ad verfed through tme-doma smulatos. A small-sgal model for a parallel rectfer system s derved []. Dyamc propertes the case of log ductve ad resstve cables are vestgated. It

20 Chapter. Itroducto s foud that the cable parameters do ot affect the dyamc propertes extesvely. Load sharg s vestgated for both droop ad master/slave methods. It s foud that a system wth parallel rectfers s stable provded that each dvdual rectfer s stable whe the droop method s appled. Ths s ot true the case of master/slave cotrol whch should be desged carefully. Small-sgal stablty crtera for DC-DC coverter systems ofte ed up a mpedace specfcato where the relato betwee source coverter output mpedace Z o ad total load coverter put mpedace Z s gve by ( Z ) Z << Z (.) o where Z s the put mpedace for coverter. Ths mpedace crtero was frst establshed the paper Iput Flter Cosderatos Desg ad Applcato of Swtchg Regulators wrtte by Mddlebroo 976 [55]. Some of the more recet mpedace specfcatos for stable operato of DC dstrbuto systems stead specfy a forbdde rego the complex frequecy plae [][][8][7]. I [7] a forbdde rego for the total loop ga s specfed so that a mmum phase marg s esured. Ths s further developed [][] where the dvdual load coverter mpedace s specfed so that the forbdde rego s avoded by applyg Re Z P Z o load < Psource (.) ad ( Zo Z ) < + Φ 9 Φ < 9 (.3) where Z Pload Zo Psource Φ arcs (.4) The results obtaed [][] are appled for the power supply of a Petum processor [7]. The power system of the vestgated PC provdes the voltage levels 3.3 V 5 V ad V. The teractos betwee source ad

21 .5 Prevous wor 3 load are foud to be strog but o stablty occurs. However t s foud that codtoal stablty problems mght occur. It s stated that codtoal stablty problems caot be solved by the applcato of the mpedace crtero. Accordg to [7] there are two possble solutos to chec for codtoal stablty. The frst s to derve the system trasfer fucto wth dfferet loads whch s geerally very complcated. The secod s to clude ga formato the mpedace crtero gvg a set of mpedace curves for the source coverter output mpedace. There are also two methods reducg the rs for occurrece of codtoal stablty. The frst s to crease the source coverter DC sde capactace. The secod s to apply a curret feedbac loop. The wor [][] together wth the stablty marg motorg method preseted [][3][4][5] s cocluded [5]. I the paper [65] the relatoshp betwee stablty ad DC bus capactace s studed. Also fault propagato s vestgated. The ma objectve of the vestgato s to mmse the DC bus capactace. I [8] large DC power systems for space applcatos are vestgated. Here equato (.) s used for small-sgal stablty aalyss. It s also poted out that large-sgal or traset stablty ssues are of great cocer. The methods suggested for large-sgal aalyss are computer aalyss volvg Bode plots Nyqust curves ad traset resposes. Also hardware testg both for valdato ad model developmet are used the stablty aalyss. Iput flter desg s dscussed [7]. Here all the DC-DC coverters are equpped wth a put flter. Itally the effect of the put flter o the DC-DC coverter trasfer fucto s vestgated. The the extra elemet theorem [56] s used to vestgate the effect caused by the mpedace see from the flter put termals. Ths mpedace s dvded to two parts: the source (seres) mpedace ad the cumulatve (shut) mpedace.e. the collectve regulator put mpedace resultg from the put flters of the other power modules. If Z Z s s << Z << Z d (.5) hold where Z s s the flter output mpedace Z ad Z d are the DC-DC coverter put mpedaces wth the output ulled ad shorted respectvely the the DC-DC coverter trasfer fucto s prcple ualtered by the put flter [7]. Furthermore ths meas that the egatve mpedace

22 4 Chapter. Itroducto resultg from a costat power load s decoupled from the DC dstrbuto bus. It s foud that f several DC-DC coverters equpped wth flters desged from ths rule are coected to a commo DC dstrbuto bus the the cumulatve mpedace s postve ad decrease as the umber of power modules crease. Ths meas that the stablty marg creases as the umber of coected power modules creases. I [5] power bufferg s utlsed to ehace stablty of a DC dstrbuted power system durg trasets. Ths s acheved by reducg the loop ga ad cosequetly the egatve cremetal put mpedace of the coverters so that the sum of the source output mpedace ad the egatve cremetal put mpedace s postve. Ths yelds a stable system. Aother possblty s also dscussed [5] where the power buffer s cotrolled to a certa put mpedace durg the trasets. Large-sgal stablty Large-sgal stablty s treated [] where the dstrbuted power system s formed by oe sgle DC source wth several load coverters coected. Each load coverter s equpped wth a put LC-flter. The LC-flters are modeled as deal except for a resstor R coected seres wth the ductor. The largesgal stablty costrats are expressed as boudares o R. The upper lmt for R s formed by applcato of the equlbrum pot codto.e. by vestgato of the maxmum R yeldg a tersecto betwee the source ad the load characterstcs. Accordg to [] ths gves dc o V R < (.6) 4 P where V dc s the DC source voltage ad P o s the load coverter output power. The lower lmt for R s foud from the mxed potetal crtero. I [] lower lmts o R are establshed for the cases wth oe two ad load coverters coected to a sgle DC source. However computatoal problems appear for larger systems. Therefore approxmatos are used the case of multple costat power loads. I the case of costat power loads t s also assumed that these are equal terms of flter compoet values ad output power. For ths case a approxmate lower boud s gve by [] R > L C (.7)

23 .5 Prevous wor 5 For hgh the resstace R has to be hgh whch mples hgh power dsspato. I [] t s foud that the approxmato of the lower boud for R gves a error betwee the approxmated maxmum sgular value ad the exact approachg % as creases. Robustess agast parameter ucertaty I [47] DC power system stablty s vestgated wth focus o robustess agast parameter ucertaty. Robust cotrol theores are appled to DC power systems. Accordg to [47] ths s doe to cope wth the sestvty to parameter ad load varato resultg DC power systems proe to stablty. The stablty robustess s vestgated by computg the multvarable stablty marg m ad the structured sgular value µ. Calculatg these quattes exactly s cumbersome. Therefore dfferet approxmato methods are vestgated [47]. The heret stablty of DC dstrbuto systems orgates from the fact that costat power loads appear as egatve resstaces to the regulators (source coverters). The equvalet resstace see from the regulator s [47] R eq v vbus (.8) P I [47] Mddlebroo s Crtero [55] s regarded as the ormal way to hadle ths problem.e. to use a solato cocept. Two problems arse from usg Mddlebroo s Crtero accordg to [47]. Frstly parameter varatos are ot covered by the crtero ad secodly t s teded for a two-port system. For the multloop case cosdered [47] a multple put multple output (MIMO) system should stead be vestgated whch s ot covered by Mddlebroo s Crtero. I [47] expressg the electrcal system as a MIMO system ad the use the covex hull algorthm to calculate the stablty marg s stead emphassed. Ths method s compared to other. Coverter modelg ad cotrol Modelg ad cotrol ssues for frot-ed three-phase boost rectfers are dscussed [34]. A average model s developed ad the stablty wth dfferet loads coected across the DC sde s vestgated. Sce a average model s used a costat power load s modeled as a resstor wth egatve resstace. A o-lear cotroller e.g. wth feed forward of the load curret gves the best performace.

24 6 Chapter. Itroducto Modelg of a four-leg verter.e. a eutral coected verter used a PEBB based DC dstrbuted power system s vestgated [67]. The fourleg coverter s preseted [78]. As [34] the coverter model [67] s averaged. The coverter put flter s of LC-type but wth a RC-crcut coected across the capactor to crease the shut mpedace at hgh frequeces. The mpedace overlap betwee the flter put ad output mpedaces s vestgated to fulfl equato (.). As expected the teracto betwee put ad output decreases as the damper resstace creases.e. the phase marg creases. I [67] a sgle source coverter formed by a trasstor frot-ed rectfer s cosdered. The DC sde flter of the trasstor rectfer s formed by a capactor. Iteracto betwee the rectfer output flter ad the verter put flter s also vestgated. As the prevous case the phase marg creases wth creasg damper resstace. The same result s acheved by creasg the rectfer DC sde capactace. A more terestg soluto exsts accordg to [67]: f the cotroller badwdth s reduced the phase marg s creased. The terestg characterstc about ths feature s that t ca be tued ole whereas the system has to be shut dow for the other two methods. I [75] two source coverters coected to the same DC dstrbuto bus are modeled smultaeously to vestgate ther teracto. Here master/slave cotrol s used ad t s clamed that the same cotrol strategy as the sgle source case apples. However t s stated that for log dstrbuto dstaces wth several sources ad loads other cotrol strateges are probably requred. A swtch model for large-sgal modelg of dstrbuted power systems s studed []. It s foud that the smulato wth the proposed model shows good agreemet wth devce level smulatos. It s also foud that the smulato tme s reduced sgfcatly. The zero-sequece curret dstrbuted power systems The fact that grd coected coverters mght gve rse to hgh commo mode currets s well ow. Ths causes problems le bearg currets ad sulato problems electrcal maches [48]. The commo mode curret results from the varatos voltage potetal of the DC sde supply rals depedg o the actual swtch state. Cosequetly the fudametal of the commo mode curret appears at swtchg frequecy. The capactve couplg betwee the supply rals ad groud provdes a path for the commo mode curret. Due to the capactve ature of the curret path the commo mode curret magtude creases wth creasg swtchg frequecy.

25 .5 Prevous wor 7 I [7] the supply ral voltage shft s aalysed. Frst the eutral to groud voltage varato for a dode rectfer/three-phase coverter combato s vestgated. The eutral s ths case the star-pot of the load at the coverter output whch for example could be the star-pot of a electrcal mache. It s show that the eutral to groud voltage vares as the egatve supply ral to eutral voltage for the rectfer wth the coverter swtchg supermposed. Both smulatos ad measuremets are show. Secod the same vestgato s made for a cotrolled rectfer/coverter combato coected bac-to-bac. I ths case the stuato s eve worse at least terms of hgh frequecy cotet sce the egatve supply ral to groud voltage varato s determed by the swtchg frequecy of the rectfer. Accordg to [7] oe way to partly reduce the problem s to sychrose the modulato carrers of the rectfer ad coverter. Note that sychrosato should be avoded f modularty ad autoomous cotrol s desred. Also a thrd case s vestgated where two geerators feed the same DC dstrbuto bus va trasstor rectfers. I ths case t s complcated to sychrose the swtchg patters sce t s lely that the geerators operate at dfferet load codtos. Furthermore there mght be extremely hgh zero-sequece currets f both geerators are grouded to the same physcal groud potetal. Three methods are proposed to reduce the problems related wth commo mode currets. Frst the allevato method whch cludes stallg electromagetc terferece (EMI) suppressg choes flterg ad the use of soft-swtchg techques. The secod method s referred to as a tolerat method where EMI currets are allowed but sheldg s used the motor to reduce the bearg currets ad sulato stress. The thrd method addresses ew coverter topologes where the four-leg VSC [67][78] s metoed as a example. I [] hgh mpedace groudg s vestgated to maage problems assocated wth eutral voltage shft. I [74] two trasstor rectfers are coected to the same geerator (or equvaletly AC power system) ad the rectfers feed the same DC dstrbuto bus. It s foud that the average smulato model dqcoordates (Appedx B) the zero-sequece curret does ot appear. Istead a dq smulato model has to be adopted. I ths smulato model a hgh zero-sequece curret appears. Ths problem s especally obvous whe oe of the rectfers has the swtch state ad the other (Appedx A) whch meas that the DC dstrbuto bus voltage s appled across the sum of the geerator stator ductaces for each phase. I [74] ths s solved by adoptg a modulato strategy where the zero voltage vectors ad are ot utlsed for the source rectfers. I [77] a o-solated system of oe frot

26 8 Chapter. Itroducto ed boost rectfer ad oe verter s studed from a coverter modulato pot of vew. It s foud that the proposed modulato scheme (terleavg) reduces the commo mode curret. I [75] groud loop teractos betwee two geerators wth a commo groud s also dscussed. A actve flter for the DC bus s dscussed [73]. The actve flter s formed by a trasstor half-brdge ad a DC l capactor. The DC dstrbuto bus sde flter s purely ductve. The actve flter s requred to reduce AC curret compoets jected from three-phase voltage source coverters. These AC compoets result from egatve-sequece or harmoc currets o the AC sde of the three-phase coverters. I [73] the swtchg frequecy of the actve flter s selected cosderably hgher tha the oe of the other coverters of the DC dstrbuto bus. The hgh swtchg frequecy mples that teractos betwee the other coverters ca be suppressed resultg a stablsg effect. Cosequetly the DC dstrbuto bus mpedace s tued for best performace thus ehacg the stablty. Note that the DC l capactor voltage must be hgher tha the DC bus voltage for the actve flter. Electromagetc terferece I the paper [8] EMI problems related to swtch mode power supples coected to a DC dstrbuto bus of log legth are vestgated. The load coverter swtchg appears as a varable load whch geerates reflectos. The hgh rse ad fall tmes geerate hgh frequecy sgals radated by the log power system coductors. I [5] hgh frequecy teracto terms of dsturbace propagato from DC dstrbuto bus voltage to load coverter output voltage s addressed. The problem s vestgated from a aalytcal pot of vew ad wth smulatos ad expermets. The ey result s that the swtchg frequeces of the coverters should be as equal as possble to reduce load coverter output oscllatos. Load flow ad short crcut calculatos DC power system aalyss terms of load flow ad short crcut calculatos s vestgated [6]. Numerous source models (.e. battery charger rectfer ad geerator models) are gve. Also coector models for load flow ad short crcut calculatos are vestgated. Loads ad braches are modeled. Accordg to [6] the preset stadards ( the year 996) are ot complete ad eed further wor.

27 .5 Prevous wor 9 I [3] the methods of the IEC draft stadard Calculato of short crcutcurrets dc auxlary stallatos power plats ad substatos are vestgated. The calculatos are teded to determe approprate fusg for the system. Four dfferet loads are vestgated [3]. These are the (thyrstor) coverter 5 or 6 Hz AC systems statoary lead-acd batteres smoothg capactors ad DC motors. The straghtforward methods gve the stadard are compared wth EMTP smulatos. The stadard gves coservatve estmates of the short crcut currets (5% overestmated). Also the tme costats estmated accordg to the stadard are loger tha the smulated. The stadard was ot applcable ( the year 996) to large DC systems such as ralway tracto systems HVDC trasmsso systems ad photovoltac systems. Accordg to [3] the reaso s that the models developed for the stadard do ot cover the set of electrcal parameters appearg for these systems. A detaled model of a RL-fed brdge coverter for use a Newto-Raphso power flow program for dustral AC/DC power systems s derved [68]. Ths s doe sce brdge models smulato pacages are geerally oly vald for example HVDC applcatos where the commutato resstace s eglgble. Two systems are smulated to demostrate the accuracy a coal me electrcal power system ad a ralway power system. It s foud that the developed model yelds a cosderably hgher accuracy for systems wth hgh commutato resstace. Due to the dffereces betwee load-flow studes of AC ad DC power systems a ew algorthm ad a DC smulato pacage are developed [79]. The load flow algorthm s based o the Newto Raphso method. DC load flow smulato models are developed for costat DC voltage power sources batteres AC/DC rectfers costat power load costat curret load costat resstace load ad tme-varyg load. Several case studes are smulated ad ther voltage profles are show. Groudg Accordg to [7] the best groud pot s the md-potetal betwee the postve ad egatve coductors of the DC dstrbuto bus. Ths meas that the voltage shft s localsed to each sub-system. I [7] groudg ssues for drve systems geeral are dscussed. A thorough aalyss s preseted ad t s foud that hgh mpedace groudg s expected to be used the future as fault detecto systems become more accurate ad relable.

28 Chapter. Itroducto.6 Specfcato of a dstrbuted power system Ths secto cotas the ma requremets put o a future DC dstrbuted power system. The requremets are based o the prevously addressed objectves of ths wor. The power system should be well adapted to operate wth preset sources ad loads terms of voltage ad frequecy. It should also provde a hgh degree of load ad source power cotrollablty. The system should be expadable.e. ew load ad source uts should be possble to add wthout alterg uts already coected. Commucato betwee dvdual coverters should be avoded sce addg ew uts wll be more complcated. Also the system could suffer from relablty problems. O the other had commucato at a low badwdth s cosdered ecessary for supervsory cotrol. Therefore sgle coverters are allowed to rely o low badwdth commucato but should be able to operate as stad-aloe uts. The degree of persoal safety should be equal to or better tha the preset power system. The basc requremets above lead to other more techcal requremets. For example hgh badwdth source ad load sde curret cotrollers should be adopted to provde load ad source power cotrollablty. Also the hgh badwdth of the curret cotrollers together wth the desre to ot rely o (hgh-speed) commucato result a demad of log equvalet tme costats of the DC bus voltage cotrol. Ths also maes the DC bus robust agast dsturbaces o coverter load ad source sdes for example egatvesequece dsturbaces.

29 Chapter Exstg DC power systems There are few systems utlsg DC to trasmt or dstrbute electrcal power by meas of DC today. Most power s trasmtted ad dstrbuted by meas of AC. The AC grd frequecy s thereby the most essetal cotrol parameter ad after that geerato ad dstrbuto of reactve power to eep the voltage wth specfed lmts. The stablty of a AC power system s strogly depedet o ts electro-magetc characterstcs ad to a mor extet o power electrocs because power systems expaded over wde areas durg half a cetury whe DC based hgh-voltage trasmsso was o-compettve. Durg the latter half of the last cetury HVDC trasmsso became cost effectve especally as a way to coect asychroous grds. For the last decades the feasblty of low-voltage self-commutated verters coected to a commo DC bus has creased resultg LVDC dstrbuto systems feedg dustral adjustable-speed drves. Coverters smlar to the oes utlsed VSC based HVDC ad dustral drves are also used o-board electrcal ralway vehcles equpped wth a commo lowvoltage LV or medum-voltage MV DC bus. The ma aspect of those socalled tracto drves s that the coverters coected to the propulso drves are ormally hadlg the same power levels but splt to parallel drves due to redudacy ad/or ratg reasos. There s usually also a auxlary power coverter coected to the commo DC bus. I ths chapter HVDC trasmsso systems are dscussed sce these are judged to have relevace as a bacgroud to the DC dstrbuted power systems to be studed. Frst the classcal HVDC l s vestgated. Secod the recetly troduced VSC based HVDC cocept utlsg sulated gate bpolar trasstor (IGBT) techology s dscussed.

30 Chapter. Exstg DC power systems. HVDC The prcpal structure of a classcal HVDC trasmsso l cossts of two three-phase thyrstor coverters coected va a termedate ductve DC bus. However real stallatos more complcated coverter structures are utlsed. Also shut reactve compesators ad passve flters for suppresso of harmocs are used. Ths s further dscussed at the ed of ths secto. Fgure. shows a prcpal schematc of a HVDC trasmsso system. L dc dc e LN le L le T T 3 T 5 v dc L dc dc T T 3 T 5 L le le e LN vdc v cable T 4 T 6 T v cable Cable T 4 T 6 T Fgure.: Prcpal schematc of a HVDC power trasmsso system. The leftmost coverter Fgure. operates as rectfer ad the rghtmost as verter. The average DC bus voltage for cotrol agle α s calculated from V dc eˆ eˆ LL cos T 6 π T 6 3 E π LL cos LL ( ω t) dt 6 cos( ω t) d( ω t) eˆ cos( α ) ( α ) V cos( α ) dc π 6+ α π 6+ α 3 π LL (.) where E LL s the RMS grd voltage ad V dc s the average DC bus voltage the case of a three-phase dode rectfer. Note that α s defed as the agular dsplacemet from the agle where the correspodg dode rectfer would have expereced a commutato to the agle where t taes place. For a sgle-phase dode rectfer ths agle cocdes wth the zero crossg of the phase voltage. For a three-phase rectfer ths agle s where two le-to-le voltages e LL tersect. The rectfer operates at cotrol agles betwee ad 9 ad therefore ts thyrstors are coected so that the power s postve flowg to the DC cable. The verter operates at cotrol agles betwee 9 ad 8 ad therefore ts thyrstors are coected such a way that the power s postve flowg out of the DC cable.

31 . HVDC 3 Fgure. shows the le-to-le voltages DC sde voltage ad cotrol agle for the rectfer ad verter respectvely. v dc [V] 6 4 α est e RS e TR Fgure.: t [ms] v dc [V] α e ST e RS e TR t [ms] Le-to-le voltages DC sde voltage ad cotrol agles for the rectfer (left) ad verter (rght) of a HVDC trasmsso system. I Fgure.3 ad Fgure.4 the R-phase le curret ad ts spectrum are show for the rectfer ad verter respectvely. le [A] Fgure.3: le [A] t [ms] lep [A] f [Hz] R-phase le curret (left) ad ts spectrum (rght) for the rectfer of a HVDC trasmsso system Fgure.4: t [ms] lep [A] f [Hz] R-phase le curret (left) ad ts spectrum (rght) for the verter of a HVDC trasmsso system.

32 4 Chapter. Exstg DC power systems The oly major dfferece betwee the le currets Fgure.3 ad Fgure.4 s the phase lag of slghtly less tha 8 for currets flowg out from the AC grds. Cosequetly the spectrums for rectfer ad verter operato are smlar. The ceter of the le curret pulse s dsplaced by a agle equal to the cotrol agle relatve to the le voltage. Ths meas that the le curret exhbts a phase lag ϕ α. Therefore the actve P ad reactve power Q are P Q 3E 3E I LL le I LL le cos s ( α ) ( α ) (.) where E LL ad I le are the RMS grd voltage ad fudametal le curret respectvely. Assumg a costat DC sde curret I dc the average DC power s gve by If the losses are eglected ths mples that 3 P VdcIdc ELLIdc cos( α ) (.3) π 3 6 P 3ELLIle cos( α ) ELLI dc cos( α ) Ile I dc (.4) π π The le currets are prcple square for a hgh DC ductace L dc +L dc. For a square le curret (6 coducto terval) the harmocs are π Ile Idc s (.5) π 3 for 573 etc. Ths s a mportat feature of three-phase dode ad thyrstor rectfers wth ductve DC ls. Classcal HVDC utlses a ductve DC bus as show Fgure.. Sce the overhead les are also ductve the commutatos tae a fte tme. Ths tme s termed commutato overlap. Note that the commutato overlap affects the spectrum of a thyrstor based curret source coverter (CSC) sce the edges are slghtly smoother due to the fte curret dervatves. However the reducto harmoc cotet s eglgble at least for low order harmocs. Therefore t s stll a good approxmato to assume that the ampltude of the harmocs fall of as / where s the harmoc order.

33 . HVDC 5 Practcal HVDC stallatos Several modfcatos are made for practcal HVDC stallatos Fgure.5 compared to the prcpal dscussed prevously. T T 3 T 5 L dc C fdc Y Y L fdc T 4 T 6 T v dc v cable C VAr C fac T T 3 T 5 L fac Y D L fdc T 4 T 6 T L dc C fdc Fgure.5: Realstc schematc of a HVDC power stato. The ma reasos for these modfcatos are related to the shape of the le currets show Fgure.3 ad Fgure.4. Frst the ceters of the curret pulses are dsplaced compared to the ceters of the susodal pulses of the le voltages. Ths correspods to a phase lag ϕ α ad yelds that reactve power s cosumed. To crcumvet ths swtched shut capactor bas are stalled o the AC le sdes of the HVDC trasmsso. A swtched capactor ba s formed by several capactors coected to the le through crcut breaers such a way that the reactve power delvered ca be vared steps. Ths s requred sce the reactve power cosumed by a thyrstor rectfer s ( α ) Q 3 E LL I le s (.6) whch meas that the reactve power cosumed s depedet both o the RMS value of the le curret fudametal ad the cotrol agle. The secod ssue regardg the AC le currets relates to ther harmoc cotet. Two methods are used to reduce the harmocs. Frst twelve pulse thyrstor coverter structures are used stead of the basc sx-pulse thyrstor coverter dscussed here. A twelve-pulse coverter cossts of two sx-pulse brdges wth the DC sdes coected seres. The sx-pulse brdges are coected to the same AC grd va a three-wdg three-phase trasformer. Oe of the thyrstor coverters s coected to a delta ( ) wdg ad the other to a wye (Y) wdg. Ths meas that there s a 3 phase shft betwee the AC voltages feedg the two coverters. Ths mples that there s a 3 phase shft betwee the currets fed to the coverters also. Sce the trasformer

34 6 Chapter. Exstg DC power systems coected to the coverters has a commo prmary sde for both secodary wdgs the le curret o the prmary sde wll exhbt ts lowest harmoc aroud the th harmoc.e. the th ad 3 th order harmocs are the lowest appearg. The ext par of curret harmocs appearg are of the 3 rd ad 5 th order. Passve shut flters tued to these specfc harmocs are also cluded to further reduce the harmoc cotet of the AC le currets. Tradtoal le-commutated thyrstor based HVDC trasmsso systems are dffcult to buld ad operate cost-effectvely wth larger complexty tha those two-termal oes dscussed above. The recetly troduced VSC based HVDC trasmsso systems are more feasble to use as mult-termal systems. By adoptg VSCs the problems assocated wth reactve power cosumpto ad harmocs producto are crcumveted to a large extet.. VSC based HVDC HVDC Lght (trademar of ABB) [9] ad HVDC Plus (trademar of Semes) are bascally extesos of the IGBT bac-to-bac coverter operatg at hgher power ad voltage levels ad wth a termedate cable betwee the coverters. Eve though ths mght seem as small step from a developmet pot of vew t has resulted umerous ew patets. The ma reaso s that the developmet of VSC based HVDC has forced the lmts of power electroc coverter techology. For example IGBT valves wthstadg more tha V (through seres coecto) have bee developed lght trggered gate or drve crcuts have bee developed ew cable techologes have emerged ad so o. Of course ths troducto caot provde all the detals but stead focuses o the basc operato. Fgure.6 shows a prcpal scheme of a VSC based HVDC trasmsso system. e LN R le L le C dc v dc v cable Cable v cable v dc C dc L le R le e LN Fgure.6: Basc VSC HVDC power trasmsso tercoecto. From Fgure.6 t s clear that trasstor based VSCs are used for ths ew type of HVDC trasmsso system. Three-phase VSCs heretly provde the possblty of bdrectoal power flow. Both the sedg ad recevg ed coverters are curret cotrolled o the AC sde sce these sdes are

35 . VSC based HVDC 7 ductve. The curret cotrollers operate the dq-frame as descrbed Appedx B. The sedg ed coverter s resposble for cotrollg the DC bus voltage. To ehace the dyamc performace of DC bus voltage cotrol formato o the output power of the recevg ed coverter should be fed forward to the DC bus voltage cotroller. The DC bus voltage cotroller for the coverter operated as rectfer s show Fgure.7. p verter e q qvref v + PI + + dc V dcref + - e q + Cdcref qdcref qref v dc Fgure.7: DC bus voltage cotroller for VSC based HVDC. Fgure.8 shows a more realstc VSC based HVDC scheme where addtoal AC sde flters are cluded. Ths s requred due to the fact that both sdes of each coverter are grouded ad stll thrd order jecto modulato (Appedx A) s used resultg a zero-sequece voltage. To atteuate the curret harmocs shut flters tued to swtchg frequecy are serted betwee the coverter AC sde terface ad the trasformer. Fgure.8 also shows hgh frequecy flters ( Hz ad above) serted at the DC sde of the coverter. These are requred to avod dsturbaces trasmtted from the cable whch could terfere wth broadcastg ad other rado frequecy equpmet. Followg the hgh frequecy DC sde flter a commo mode choe s serted. L f D Y L le Cdc vdc C f L f3 C f3 v cable C f L f Fgure.8: Realstc VSC based HVDC coverter stato. A VSC based HVDC trasmsso system cosstg of two coverters accordg to Fgure.8 ad a T-model of a HVDC cable (smlar to the π- l show Fgure 3.3) s vestgated smulatos. The coverters have a rated power of 33 MVA each ad the omal DC cable voltage s 3 V

36 8 Chapter. Exstg DC power systems (±5 V). The reactace of the ductve le flters equal.4 p.u. ad the equvalet tme costat of each coverter cludg DC l capactor s ms. The rated power s the same as the oe gve [9] ad the other data are typcal for a HVDC Lght system. For the smulatos the rated le-tole voltage s set to 5 V. The shut flter s tued to swtchg frequecy (95 Hz) so that the fudametal curret compoet equals. p.u. whch yelds approprate values for both L f ad C f. The hgh frequecy flter o the DC sde s based o a characterstc frequecy of Hz ad C f C f /. If the capactace of C f s hgher t wll affect the characterstc frequecy of the shut harmoc flter. The mutual ductace of the commo mode choe s set to the same value as L f ad the magetc couplg factor s set to.99. The capactace of C f3 s set to C f3 C f. These compoet values most lely defer from the oes teded for the real stallato. Also the DC bus voltage cotroller ad the coverter curret cotrollers are ot equal to the oes used the real stallato. Probably the curret cotrollers used here have hgher ga tha the oes the real stallato. Fgure.9 ad Fgure. show the coverter power ad DC bus voltage respectvely for a tme-doma smulato startg at o-load. The verter receves a output power commad equal to 65 MW (half rated power) at tme t. ms. The curret cotroller becomes aware of the creased power referece at tme.5 ms ad calculates the desred AC sde voltage referece whch s appled oe sample later at tme.5 ms. The curret mmedately starts to crease but ths s ot otced by the curret cotroller before the ext sample stat at.75 ms. At ths tme the curret cotroller of the verter seds a power referece to the coverter actg as a rectfer whch creases ts power demad. Due to the tme requred to establsh a rectfer put power correspodg to the verter output power the DC bus voltage s somewhat reduced see Fgure.. p p r [MW].5.5 Fgure.9: t [ms] Iverter AC sde power (blac) ad rectfer AC sde power (grey).

37 . VSC based HVDC 9 34 v dc [V] t [ms] Fgure.: Rectfer DC sde voltage. Fgure. shows the le ad coverter currets for both the rectfer ad verter. It s see that the currets cota a rather hgh rpple orgatg from swtchg. Especally the coverter currets exhbt a hgh rpple at the power crease. These rpple currets are maly zero-sequece swtchg frequecy compoets. The rpple s ot so proouced the le currets due to the shut harmoc flter. The hgh ga of the curret cotrollers maes ths problem worse. Fgure. shows the statoary le ad coverter currets for the verter together wth the correspodg harmoc spectrums the vcty of swtchg frequecy. The shut flter tued to swtchg frequecy atteuates ths compoet effectvely. le cov [A] le cov [A] t [ms] Fgure.: Le curret (blac) ad coverter curret (grey) for the rectfer (top) ad verter (bottom) for a load power crease. The currets are postve flowg to the AC grds.

38 3 Chapter. Exstg DC power systems le cov [A] t [ms] lep covp [A] Fgure.: Le curret (blac) ad coverter curret (grey) for the verter (left) ad le curret spectrum (blac) ad coverter curret spectrum (grey) for the verter at frequeces close to swtchg frequecy (rght). I practcal HVDC Lght stallatos resstors are coected parallel to the ductors of the shut flter. As a cosequece harmocs a broader frequecy spectrum are atteuated. Therefore the harmocs aroud swtchg frequecy Fgure. are atteuated more effectvely a real stallato. Feed forward of the output power of the verter for DC bus voltage cotrol s ot used real stallatos. Due to the low equvalet tme costat of the coverters oly low rate of chage of the verter output power s allowed. The HVDC Lght stallatos of comparably low ratg approxmately 5 MW are based o two-level coverter techology (Fgure.8). To acheve hgher power ratgs (3 MW) three-level VSCs are utlsed [9]. Self-commutated two-level coverters of the same type as used the study of VSC based HVDC form thus a bass for the vestgated mult-termal DC dstrbuto system. Some experece could also be foud from dustry ad tracto as metoed the troducto to ths chapter. f [Hz]

39 Chapter 3 DC bus voltage cotrol Two dfferet DC bus voltage cotrol schemes are vestgated. Oe of the methods referred to as the commucato or master/slave method strogly reles o fast commucato betwee the source ad load coverters. The output power wth sg s calculated for each of the coverters. Iformato o total output power s fed forward to the coverters. Oe of the coverters the master s resposble for cotrollg the DC bus voltage. Feed forward of the total output power allows for hgh badwdth DC bus voltage cotrol. The DC bus voltage cotroller s however stll requred durg trasets ad to compesate for losses the DC power system. Due to the resstve voltage drop a proportoal-tegral (PI) cotroller s adopted order to avod statoary DC bus voltage error. The other method s referred to as voltage droop cotrol. Droop cotrol does ot requre ay commucato at all betwee the coverters. Istead the DC bus voltage s measured at the source coverter termals. All the source coverters cotrbute to balace the total power cosumed by the loads ad the losses of the DC power system. I commo voltage droop cotrol the DC bus voltage decreases learly as the output power for the coverter creases order to gve stable operato. Ths of course yelds a statoary error the DC bus voltage. Therefore a restorato process to reduce the statoary DC bus voltage error s also dscussed. The chapter begs wth a overvew of the vestgated system. The the DC bus model used for the aalyss s troduced. The cotroller structures are vestgated ad approprate cotroller parameters are derved. The dyamc propertes the case of droop cotrol are vestgated. Last the vestgated DC bus voltage cotrol schemes are compared terms of load sharg. 3

40 Chapter 3. DC bus voltage cotrol 3. Ivestgated system The vestgated DC dstrbuto etwor model cossts of fve coverters: three are operated as sources ad two are feedg power to loads. The coverters are coected to galvacally separated AC power sources or loads. The sources ad loads are modeled as three-phase grds. The grds are galvacally separated.e. wthout commo referece to avod a lowmpedace path for the zero-sequece ad thrd order harmoc currets [7]. To vestgate the traset respose of the DC bus voltage cotrollers the power refereces for the power fed to the loads are chaged steps. Therefore the dyamcs of the geerators wd turbes etc. mght terfere wth the dyamcs of the voltage cotrol. Ths s further dscussed Chapter 4 where a dstrbuted system operated oly wth wd power s vestgated. Fgure 3. shows a fve-coverter DC power system cofgurato represetatve for the power systems cosdered the aalyss. p p 5 p v v v p 4 p 3 + v 3 v Fgure 3.: The vestgated DC power system cofgurato. Each coverter has a frot terface wth a ductve coecto to the source. Therefore the ed terface coected to the DC bus s capactve. Cosequetly the frot sde of the coverter s curret cotrolled ad the ed sde s voltage cotrolled. I Fgure 3. the th coverter sub-system of the fve cluded the DC etwor s show. From Fgure 3. t s clear that the cosdered coverters are self-commutated three-phase full-brdges. The DC bus capactor s used to partly decouple the AC ad DC systems so that a dsturbace o oe sde s ot reflected o the other sde of the coverter. A smlar system s vestgated [66] but stead of trasstor equpped VSCs thyrstor based CSCs are cosdered.

41 3. Ivestgated system 33 v dc C dc L le R le e LN Fgure 3.: The coverter formg the terface betwee the DC bus ad the th threephase AC etwor source or load. 3. DC bus model There are two DC bus models dscussed ths chapter. The DC bus voltage cotrollers are desged based o the assumpto that the DC bus s purely capactve. Therefore a purely capactve DC bus wth capactace equal to the total coverter DC bus capactace s aalysed frst. The a more accurate DC bus etwor wth the cable segmets modeled as resstve ductve ad capactve π-ls accordg to Fgure 3.3 s aalysed. s cable r v s C s L cable R cable C r v r Fgure 3.3: The two-coverter DC bus π-l model. I the vestgato of dyamc propertes C s ad C r Fgure 3.3 deote the total bus capactace.e. cable ad coverter DC bus capactace for the sedg ad recevg eds respectvely. The cable capactace s splt two equal parts whch are the added to the DC bus capactaces to gve the total sedg ad recevg ed capactaces. I the vestgato o load sharg the cable ad DC bus capactaces are modeled separately. Large-sgal stablty the case of dstrbuted coverters supplyg costat power loads s vestgated []. The result s a put LC-flter specfcato for the load coverters based o the maxmum output power for the load coverters ad the total source coverter output resstace. A equlbrum pot crtero s used to formulate a upper lmt for the source coverter output resstace whch results a tutvely uderstadable crtero statg that: The equvalet load resstace must be hgher tha the source coverter output resstace. Mathematcally ths s expressed as []

42 34 Chapter 3. DC bus voltage cotrol R cable r v < (3.) 4P wth otatos accordg to Fgure 3.3. The load or recevg ed power s deoted P r. A lower boud for the source output resstace s also gve []. For a sgle output coverter wth a costat power load the lower boud the case of a deal source s gve by cable r L R > (3.) cable Cr Modfcatos made to the latter expresso to clude the case wth several costat power load coverters are show []. However the derved expressos are based o the assumpto that the resstace R cable s commo for all the paralleled coverters. I a dstrbuted power system ths s ot lely. The resstace s stead dstrbuted alog the cables. Furthermore the ductace s also a property of the cables ad ot serted o purpose for flterg acto. Here oly capactors are serted as voltage stablsers ad flters close to both source ad load coverters. The stablty problem therefore merely becomes a problem of selectg coverter DC bus capactors. 3.3 Cotroller structure Several dfferet DC bus voltage cotrol schemes exst [5] of whch especally two seem commoly used: master/slave ad droop cotrol. I master/slave cotrol actve load sharg s performed ad the master cotroller dstrbutes power refereces to the other coverter cotrollers operated as sources e.g. the slave coverters. I droop cotrol each source coverter delvers power to the DC bus determed by the actual DC bus voltage error at the coverter. Therefore droop cotrol does ot requre ay commucato. Eve though master/slave ad droop DC bus voltage cotrollers operate a dfferet maer the cotroller structures are essetally equal whch s apparet from [49]. The ma dfferece s that master/slave DC bus cotrol the actual output power of the slave ad load coverters s also fed forward to the master whch tur geerates power refereces for the slave coverters actg as sources. Sce commucato s used for the master/slave scheme the badwdth of the DC bus voltage cotrol ca be creased f the

43 3.3 Cotroller structure 35 commucato badwdth s suffcetly hgh. Thus less eergy eeds to be stored the DC bus whch mples that the DC bus capactace ca be decreased [49]. However the system becomes more proe to teractos betwee the two sdes of the coverters whe the eergy storage s reduced [6]. I [73] grd teractos are hadled by a actve power le codtoer coected to the DC bus. Ths meas that the DC bus capactace ca be ept low ad stll udesred teracto betwee the coverter sdes s atteuated. DC bus voltage droop cotrol I commo voltage droop cotrol the bus voltage decreases learly as the output curret or some cases power for the coverter creases order to gve stable operato (Fgure 3.4). Ths of course results a statoary error the voltage level. V dc V dcref I dc Fgure 3.4: Steady state droop characterstc. The cotroller structure for DC bus voltage cotrol s show Fgure 3.5. A proportoal (P) cotroller s used for the droop scheme smlar to the PIcotroller derved [6] for bac-to-bac coverter DC l voltage cotrol. Ths cotroller structure s mplemeted all coverters teded for power flow to the DC bus. The reaso for ths s to be able to dstrbute the total load betwee the sources whe droop cotrol s used. Note that several coverters are used to support the power flow whch s ot evdet from Fgure 3.5. To smplfy the vestgato a smple system wth oly oe source ad oe load coverter s cosdered. Ths s exteded to cover the case wth several source ad load coverters. The measured DC bus voltage s low-pass fltered (Fgure 3.5) to atteuate teractos betwee the egatve-sequece curret of the AC sde ad the DC bus voltage cotrol dscussed [67] ad to facltate cotroller pole-placemet desg [6].

44 36 Chapter 3. DC bus voltage cotrol P refext (s) I refext (s) V s(s) I cable (s) / Z +/ Z cable r V dcref (s) K G P(s) I sref (s) G cov (s) I s(s) /sc s V s(s) V slp(s) s+ lp lp G lp(s) Fgure 3.5: Structure of the DC bus voltage droop cotroller. The source coverter curret s deoted I s ad the cable curret I cable. The DC bus voltage cotroller for the droop scheme s wrtte ( v ) s ref K Vdc ref s lp (3.3) I the case of a purely capactve DC dstrbuto system.e. whe L cable H R cable Ω ad C dc C r +C s (Fgure 3.3) the closed loop trasfer fucto from DC bus voltage referece to actual voltage s wrtte G cl ( K C )( s + ω ) lp dc lp lp ( s) s (3.4) + ω s + ω ( K C ) The effects of o-zero cable mpedace are show the ext secto where dyamc propertes are examed. I the case of a purely capactve DC dstrbuto system the curret at the recevg ed s expressed as r s Cdc dc (3.5) whch the case of a sgle source gves a droop fucto accordg to V s () s s ( K C )( s + ω ) + ω s + ω lp dc lp lp ( K C ) dc V dc ref () s s ( C )( s + ω ) + ω s + ω The steady state droop mpedace or resstace s thus wrtte lp dc lp lp ( K C ) dc I r () s (3.6) R droop (3.7) K

45 3.3 Cotroller structure 37 The characterstc polyomal of the closed loop trasfer fucto s gve by p () s s +ω s + ω ( K C ) (3.8) The desred characterstc polyomal ca be expressed as ad s fulflled for p lp lp () s s + ζ ω s + ω dc (3.9) K ωlpcdc (3.) ζ ( ) The closed loop badwdth s gve by ω ωlp (3.) ζ It s apparet that a hgh dampg of the poles of the closed loop trasfer fucto requres a hgh DC dstrbuto bus capactace. Here the poles are chose to obta a performace correspodg to the oe of a Butterworth flter whch meas that the dampg s selected as ζ (3.) Ths choce of dampg requres a rather moderate DC dstrbuto bus capactace wthout mag the system oscllatory. The last pot s mportat sce the DC dstrbuto bus s ot purely capactve. Ths mples that t s ot advsory to mae the smplfed system oscllatory ad the troduce o-dealtes to the system. From the equatos above the ga s expressed as K ω lp C dc (3.3) Assume that each coverter correspods to a vrtual resstace wth a base value equal to

46 38 Chapter 3. DC bus voltage cotrol R dc ref V (3.4) P I the case of droop cotrol the DC curret at rated load for rectfer operato creases due to the decreased DC bus voltage caused by the droop characterstc I dc dc ref P I (3.5) V dc ( δ ) ( δ ) where δ s the relatve coverter output voltage droop at rated power. Sce the voltage droop correspods to the ga t s foud that R droop ( ζ ) V dc ref δ R I K ω C lp dc dc ( δ ) ( δ ) δ (3.6) Ths s rewrtte to ( δ ) ( ζ ) ( ζ ) lp R Cdc ωlp τ system δ (3.7) ω where τ system s the tme costat of the system. Now t s assumed that oly half the DC bus capactace requred s located at the source coverter. The other half s located at the recever or load coverter. Ths meas that Cdc C s Cr Cdc coverter (3.8) ad the coverter tme costat s RC τ dc system τ coverter RCdc coverter (3.9) Ths gves the followg specfcato for each coverter both source ad load coverter ζ ω lp τ (3.) ( δ ) δ

47 3.3 Cotroller structure 39 Ths mples that all coverters coected to the DC dstrbuto system should be equpped wth DC bus capactors selected accordg to C P (3.) V ω dc coverter dc ref ζ lp ( δ ) δ Note that for a mult-coverter system all the source coverters should have the same statoary characterstc to obta proper.e. democratc load sharg. If the DC sde capactor of each coverter s selected accordg to the expresso above ths s fulflled. Furthermore for a deal cable.e. wthout ay mpedace other tha the DC sde capactors the system trasfer fucto s the same as for the two-coverter system whe the total rated power of the sources equal the oe of the loads. For coverters wth the followg data V dc ref 75 V ω lp 3 rad/s 88 rad/s ζ δ.5 (3.) t s foud that each coverter source ad load should have a DC sde capactace to rated power rato gve by C dc coverter P coverter 99 F/W (3.3) Note that the rated power s gve for verter operato at a DC l voltage equal to V dcref. Accordg to [4] the coverter losses decrease for rectfer operato compared to verter operato (Appedx C). Ths mples that the maxmum allowable rectfer power s hgher tha the maxmum verter power based o the assumpto that the coverter losses are equal the two cases. It s show a later secto that for the IGBT module Semro SKM3GB3D the rectfer power resultg the same amout of coverter losses as verter operato at rated load s aroud 7% hgher for droop cotrol tha the rated power for verter operato. The hgher rated power at rectfer operato s used to compesate for DC bus losses. The DC bus capactace requred for each coverter by applyg ths method s hgher compared to what has bee reported other wor o the same topc [67]. Therefore the coverter proposed here s more buly. However the DC

48 4 Chapter 3. DC bus voltage cotrol l capactace for each coverter s lower tha twce the oe of a regular three-phase coverter e.g. for motor drve applcatos. Furthermore the magtude of the DC bus voltage oscllatos observed for a ubalaced AC load [67] s versely proportoal to the DC bus capactace [6]. The oscllato appears at twce the fudametal frequecy of the ubalaced AC etwor [6][67] whch meas that troducg a low-pass flter wth breaover frequecy lower tha the oscllato frequecy effectvely atteuates the problem. For the 75 W DUAL battery charger [5] a DC bus varato of 5% of the rated DC l voltage of 75 V s allowed the specfcato. Ths requres a DC l capactace of.45 mf accordg to Appedx D. The susodal Hz compoet has a ampltude of 58 A (4 A RMS). Furthermore two 45 V capactors has to be coected seres whch mples that DC l capactors of 4.7 mf should be suffcet. However the RIFA PEH 4.7 mf capactors oly susta betwee 3.5 ad 5.9 A RMS at Hz. Therefore at least three such braches are requred to avod thermal overloadg of the capactors whch correspods to 7.5 mf. I the mplemeted DUAL battery chargers fve such braches are used to provde marg to the absolute maxmum temperature whch yelds a total DC l capactace of.75 mf. Ths should be compared to the 5 mf requred for a 75 W DC dstrbuto coverter accordg to the selecto method proposed here. DC bus voltage cotrol wth droop error restorato There have bee attempts to clude error restorato droop cotrol [7]. Ths could be doe by for example usg DC bus voltage PI-cotrol stead of the P-cotroller show Fgure 3.5. If a PI-cotroller s adopted the scheme Fgure 3.5 the closed loop trasfer fucto from DC bus voltage referece to actual voltage for each coverter operated as a source.e. supportg the DC bus voltage s wrtte G cl () s s 3 K T C dc + ω s lp ( st + )( s + ω ) Kω + C dc lp lp Kω s + T C lp dc (3.4) where T s the tme costat of the tegral part. The cotroller parameters are selected a smlar way as for the regular droop scheme to compare the cotroller acto. Therefore the closed loop trasfer fucto should have a characterstc polyomal gve by

49 3.3 Cotroller structure 4 p 3 lp lp () s s + ω s + s + ( s + ζ ω s + ω )( s + ω ) lp Kω C dc Kω T C Ths gves the followg cotroller parameters dc (3.5) ω ωlp + ζ K Cdcω + ζ ( + ζ ) T ωlp lp (3.6) For poles located accordg to a correspodg thrd order Butterworth flter a relatve dampg ζ (3.7) s requred. Ths gves the followg cotroller parameters ω ωlp K Cdcω 4 T ωlp lp (3.8) Note that the ga s the same as for the P-cotroller used for regular droop cotrol. Thus the same cotroller ca be used both cases ad the oly dfferece s whether the tegral part should be added or ot. For PI-cotrol the source coverter output voltage s wrtte V s () s s 3 s + ω 3 ( K Cdc )( s + ωlp )( s + ( T )) s + ( K Cdc ) ωlps + ( Kωlp CdcT ) ( Cdc ) s( s + ωlp ) s + ( K C ) ω s + ( Kω C T ) lp + ω lp dc lp lp dc V I dc ref r () s () s (3.9)

50 4 Chapter 3. DC bus voltage cotrol Note that the steady state source mpedace s equal to zero whch s the ma advatage gaed by the use of PI-cotrol. Oe major drawbac exsts wth decetralsed PI DC bus voltage cotrol resultg from the fact that several sources equpped wth tegral parts cotrol the same quatty the DC bus voltage. I automatc cotrol terms ths results that both observablty ad cotrollablty are lost [8]. Ths mples that ay o-deal feature of the DC dstrbuto etwor for example the bus resstace wll force the sources to exhbt poor load sharg. Oe way of partly crcumvet ths problem s to hbt updatg of the cotroller tegral part whe the DC bus voltage at the partcular source s sde a specfed dead-bad [7]. The dead-bad ought to be proportoal to the voltage drop alog the DC bus betwee the source coverter questo ad a predetermed pot the DC etwor commo to all source coverters. Also the traset behavour s affected by the DC bus mpedace ad sce a tegrator correspods to a dyamcal state the mbalace durg the trasets remas statoary codtos. Ths s partly solved by applyg a load depedet tegral tme costat so that a coverter coected to a source wth hgh relatve loadg wll have a wea tegral part. Cosequetly t s oly updated to a lmted extet for a ew load stuato. Ths has bee successfully utlsed for wd power farms operatg drectly o the three-phase AC grd [7]. Smulatos of a DC dstrbuted power system wth source coverters wth tegral parts gve by T 4 P P ωlp (3.3) are show the secto o load sharg. Note that the power s cosdered as postve flowg out of the coverter AC sde. Therefore the tme costat above creases the more power the source delvers to the DC system. Master/slave DC bus voltage cotrol I the master/slave DC bus voltage cotrol scheme vestgated here oly the master s resposble for voltage cotrol. The voltage cotroller for the master coverter s show Fgure 3.6. Iformato o actual power for all the other coverters s fed forward to the master where approprate power refereces for the slaves.e. the other coverters operated as sources are calculated. Eve f ot used here the voltage cotroller output could be cluded the slave power refereces.

51 3.3 Cotroller structure 43 P load (s) V dc(s) V dcref (s) K T G PI(s) I Cdcref (s) G cov (s) I dc(s) /sc dc V dc(s) V dclp (s) s+ lp lp G lp(s) Fgure 3.6: Structure of the master/slave DC bus voltage cotroller. The source coverter curret s deoted I dc. I Fgure 3.6 a PI-cotroller s adopted for master/slave DC bus voltage cotrol. The closed loop trasfer fucto from DC bus voltage referece to actual voltage s equal to the oe for droop cotrol wth voltage error restorato.e. G cl () s s 3 K T C dc + ω s lp ( st + )( s + ω ) Kω + C dc lp lp Kω s + T C lp dc (3.3) Note that for ths master/slave scheme oly oe coverter serves to cotrol the DC bus voltage. Stll several coverters are used to support the power flow but ther power referece s provded by the over-lyg cotroller structure. The load power fed forward Fgure 3.6 s thus the sum of the output power of all the other coverters the DC system. Also for master/slave DC bus voltage cotrol the closed loop trasfer fucto has poles located as a correspodg thrd order Butterworth flter to obta smlar dyamc propertes. Cosequetly the cotroller parameters are gve by (3.8) for the master/slave scheme. However ote that the ga s based o the total DC bus capactace the case of master/slave cotrol. For droop cotrol the ga s calculated based o C dc C dccoverter for each source coverter. For master/slave cotrol the source coverter output voltage s wrtte

52 44 Chapter 3. DC bus voltage cotrol V () s ( ωlp )( s + ωlp )( s + ( ωlp 4 ) ( ω ) s + ( ω ) ( s + ω ) ( s + ) ( ) V dc dc ref lp lp lp () s (3.3) f the power fed forward s accurate ad the DC bus s purely capactve. 3.4 Cable mpedace I ths secto the effect of cable mpedace o voltage droop cotrol s studed. The vestgato focuses o regular droop cotrol.e. wthout voltage error restorato. Steady state characterstcs For smplcty assume a etwor cosstg of oly oe source ad oe load operatg steady state. The latter assumpto mples that the etwor ca be regarded as purely resstve ad that oly the steady state droop characterstc has to be cosdered see Fgure 3.7. I r V dcref R droop R cable R r V r Fgure 3.7: The smplfed Theve equvalet for steady state aalyss. The curret suppled to the load wth referece to Fgure 3.7 s wrtte Vdc ref Vr Pr I r R + R V droop cable r (3.33) Ths s rewrtte to form a secod order algebrac equato r dc ref ( R + R ) P V V V + (3.34) r droop cable If ths s expressed oe commo p.u. system e.g. the oe of the source t s foud that ( ) ( δ ) + (( δ ) δ + r ) p δ (3.35) r r cable r r

53 3.4 Cable mpedace 45 where (-δ r ) ad p r are the p.u. recevg ed voltage ad power respectvely. The p.u. cable resstace s deoted r cable. The p.u. base s gve Appedx D. The stable soluto to ths equato s wrtte δ r δ 4 (( δ ) + r cable ) p r (3.36) Sce the resstors form a voltage-dvdg etwor the source voltage s V R ( V V ) droop s Vdc ref dc ref r (3.37) Rdroop + Rcable The relatve voltage reducto at the sedg ed s thus δ s ( δ ) ( δ ) δ ( δ ) ( δ ) δ δ + r δ + r cable cable δ r 4 (( δ ) δ + rcable ) pr (3.38) The rs of ecouterg coverter over-modulato due to a too low DC bus voltage s the ma reaso for vestgatg the DC bus voltages at dfferet pots the etwor. The mmum DC l voltage s determed from the requred load voltage at the coverter output termals cludg the voltage drop across the output flter. For a three-phase AC load expressed rotatg referece dq-coordates (Appedx A Appedx B) the statoary coverter output voltage s wrtte u u d q R R le d le q ω L + ω L le q le d + e + e d q R R le le Q ωl e q P + ωl e q le le P e q Q + e e q q (3.39) I the expresso above P ad Q deote actve ad reactve power postve flowg from the coverter to the AC system. The AC grd agular rdq frequecy s deoted ω πf ad the voltage vector e ed + jeq. Accordg to Appedx A e d. The AC le flter ductace ad resstace are deoted L le ad R le (Fgure 3.). The output voltage ad curret of the

54 46 Chapter 3. DC bus voltage cotrol r dq coverter are deoted u ud + ju Neglectg the resstve voltage drop gves q ad rdq + j respectvely. d q u u d q ω L ω L le q le d ω L + e q le ω L le P e q Q + e e q q (3.4) The coverter output voltage magtude s gve by r u P Q ud + juq ωl + + le ω L le eq eq eq (3.4) If ths s expressed le-to-eutral RMS voltages t s foud that U P 3 Q 3 Lle + ωlle ELN ELN ω + ELN (3.4) The maxmum allowable RMS le-to-eutral voltage to avod overmodulato statoary operato s gve by Vdc U max (3.43) 6 for symmetrcal voltage refereces.e. whe space vector pulse wdth modulato (SVPWM) [35] s used see Appedx A. If t s assumed that the reactve power Q equals zero the lmtg case s wrtte dc V 6 P 3 ω Lle + ELN E (3.44) LN whch s vald whe the coverter s operatg as verter as well as for rectfer operato. Thus for the recevg ed coverter (dex r) of the DC etwor the lmtg case s V r P 3 r ω r L le r + ELN r (3.45) 6 E LN r

55 3.4 Cable mpedace 47 Cosequetly the recevg ed DC bus voltage p.u. s gve by le r ( r ) p + e r LL r e LL r δ x (3.46) where e LLr ad x ler are p.u. values of the le-to-le voltage ad le reactace of the recevg ed respectvely. The p.u. base s gve Appedx D. Rearragg the terms yelds xle r p r + ell r e LL r δ r (3.47) Rearragg (3.36) gves the cable resstace r cable δ r δ p r 4 ( ) δ (3.48) The maxmum cable resstace allowed s foud from combg the last two expressos r cable xle r p r e LL r p + r e 4 LL r ( δ ) δ (3.49) The p.u. le reactace used [6] s approxmately equal to x.838 (3.5) le whch s requred to fulfl the stadard IEC -3- f E LN 3 V ad V dcref 75 V at a swtchg frequecy of 4.95 Hz. Assumg operato at rated power.e. p r gves ad the maxmum allowable cable resstace p.u. δ.4 (3.5) r r. (3.5) cable

56 48 Chapter 3. DC bus voltage cotrol Furthermore ths correspods to a source voltage gve by the droop ( δ ) ( δ ) δ δ δ s δ r.6 (3.53) + r cable Ths meas that the p.u. power suppled from the source equals p s ( δ s ) ( δ ) δ s.96 δ (3.54) whch mples that the 7% hgher rated power possble at rectfer operato for the same amout of losses as for rated verter operato s ot suffcet. O the other had a DC etwor desg wthout margs to avod overmodulato s ot lely. Also cable losses approxmately equal to. p.u. seems hgh. The p.u. droop characterstc for a three-phase coverter based o Semro SKM3GB3D modules cludg over-modulato ad loss lmts s show as a fucto of curret Fgure 3.8 ad of power Fgure 3.9. v dc dc Fgure 3.8: Per ut v droop characterstc cludg over-modulato ad loss lmts. v dc p dc Fgure 3.9: Per ut pv droop characterstc cludg over-modulato ad loss lmts.

57 3.4 Cable mpedace 49 Fgure 3.8 ad Fgure 3.9 are based o the followg coverter data: S 75 W V dcref 75 V E LN 3 V 5 Hz ad L le mh accordg to (3.5). Furthermore the coverter operates such a way that uty power factor s obtaed for the AC etwor. The loss lmts are calculated from the method gve Appedx C ad the over-modulato lmt s calculated from (3.44). From Fgure 3.9 the creased power hadlg capablty for rectfer operato at a semcoductor loss level equal to the rated appears to be close to 7% as prevously metoed. Dyamc propertes A mpedace specfcato for dvdual loads of DC dstrbuto systems based o the small-sgal stablty crtero s preseted []. Here stablty s studed terms of locato of the closed loop poles ad the root-locus [5] as a fucto of the cable parameters. Therefore the cables are from ow o modeled as resstve ad ductve wth the cable capactace eglected or lumped wth the coverter DC sde capactace.e. wth ( s +) Zcable slcable + Rcable Rcable τ cable (3.55) The equvalet mpedace of the recevg ed s expressed as Z r R sr C r r r Rr + sτ + r (3.56) The mpedace see from the source coverter (cludg ts DC sde capactor) s wrtte Z Z cable + Z r R cable Rr τ cable + (3.57) sτ + ( s + ) Here the cable ad the equvalet recevg ed resstaces are expressed as r Rcable r Vr Rr Pr cable R ( δ ) p r r ref Vdc P r R r (3.58) Ths meas that the correspodg tme costats are

58 5 Chapter 3. DC bus voltage cotrol τ τ r cable τ cable( pu) τ ( δ ) coverter r R rcr τ coverter τ r( pu) τ coverter pr (3.59) where τ (pu) deotes p.u. tme costat. The mpedace s thus wrtte Z Rr sτ + (( r / r )( sτ + )( sτ + ) + ) cable + Zr cable r cable r r (3.6) The source coverter output voltage s dvded betwee the cable mpedace ad the equvalet mpedace of the recevg ed coverter whch gves V V R S Z r r cable cable r Zr + Z r τ cableτ r s ( r / r )( sτ + )( sτ + ) cable r + τ cable cable + s + τ r τ r + r + τ r r cable r cable (3.6) Assumg complex poles the characterstc polyomal s wrtte whch results p ( s) s + ζ oωos + ωo (3.6) ω o τ τ ζ o τ coverter cable( pu) τ + τ cable( pu) cable( pu) τ r( pu) r( pu) τ r( pu) r r cable cable r + r + r r r cable (3.63) Assumg ω ( δ ) δ o ωo( pu) ωlp ω o pu ζ ( ) ω base (3.64) gves a cable costat of

59 3.4 Cable mpedace 5 r + r τ cable( pu) (3.65) ω τ rcable o( pu) r( pu) Sce the measured DC bus voltage s low-pass fltered wth brea-over frequecy ω lp at the sedg coverter termals t s desrable that ζ ω ( (3.66) o pu) ( δ ) δ The ma purpose of (3.6)-(3.66) s to provde a umercal base for the further vestgato where the lmtg case wth cable resstace equal to r.6 (3.67) cable s assumed. Ths gves the recevg ed voltage δ r cable r (3.68) 4 ( ) + ( ( δ ) δ + r ) p V at rated output power. Therefore the recevg ed p.u. resstace s gve by r r ( δ ) p r r.77 (3.69) Note that the p.u. resstace ad tme costat of the recevg ed are equal f the cable capactace s eglected.e. ( δ ) r r rr τ r( pu) (3.7) p Therefore the maxmum allowable tme costat accordg to (3.66) s gve by τ cable( pu) ω o( pu) ( δ ) ζ r r cable δ + r r cable r r p r ( δ ) r + r cable.45 (3.7)

60 5 Chapter 3. DC bus voltage cotrol Ths meas that the cable resstace ad ductace are R L cable cable r τ cable cable R R.6R cable.43 3 τ coverter R (3.7) For a 75 V W system ths s equvalet to cable parameters R L cable cable.3375 Ω.58 mh (3.73) The smulato result for ths case s show Fgure 3.. Note that the cable data vestgated here correspod to r cable.6 p.u. ad l cable.4 p.u..e. τ cable.4 p.u. All tme-doma smulatos ths secto are carred out usg DYMOLA TM wth swtch-mode coverter models utlsg vector curret cotrollers accordg to Appedx B ad voltage droop cotrollers accordg to (3.3). The voltage droop cotroller ga (3.) for each source coverter s calculated based o C dc C s sce a load coverter of the same rated power has C r C s (3.8). The AC sde curret referece for the source coverter s calculated from the droop curret referece based o the assumpto that the coverter s loss-less. v s v r [V] p s p r [W] t [ms] Fgure 3.: DC bus voltage (top) ad power (bottom) of the sedg (blac) ad recevg (grey) ed coverters at a output power step from zero to rated power.

61 3.4 Cable mpedace 53 I Fgure 3. t s show that the statoary voltage s lower tha expected (a few Volts). Ths s due to the fact that rated power s trasmtted to the threephase grd.e. the losses the le sde flter have to be added to the power suppled to the DC sde of the coverter. Ths also mples that the equvalet load resstace R r s lower tha expected from prevous calculatos. Now the system s examed by meas of pole-zero plots. The trasfer fucto V s /V dcref accordg to Fgure 3.5 s vestgated MATLAB TM for dfferet cable parameters ad recevg ed loadg. MATLAB TM s used sce the trasfer fucto s sgfcatly more complcated tha (3.4) whe cable parameters are cluded. The characterstc polyomal for ths two-coverter system s of the fourth order ad aalytcal expressos for the poles are ot possble to derve. Note that (3.6) caot be used the stablty aalyss sce the source coverter output mpedace cludg C s s ot tae to accout. Istead (3.36) s used to calculate the recevg ed voltage for the actual loadg. A equvalet load resstace s calculated from δ r ad p r. The trasfer fucto Z cable +Z r appearg Fgure 3.5 s calculated accordg to (3.57). The total mpedace see from the coverter s calculated as the source coverter DC sde capactace C s parallel wth Z cable +Z r whch also forms the trasfer fucto from I s to V s (Fgure 3.5). The coverter Fgure 3.5 s cosdered havg a trasfer fucto G cov (s) for the frequeces of terest ad the exteral power referece P refext s set to zero. Fgure 3. shows the pole-zero plot for the system wth the same parameters as for Fgure 3. at o-load (small margs) ad at rated load (large margs). It s obvous from Fgure 3. that the actual loadg of the system s of mor mportace for stablty whch s due to the fact that the equvalet load resstace s cosderably hgher tha the cable mpedace. 5 Imag Axs 5 5 ρ ρ 3 ρ 4 ρ Real Axs Fgure 3.: Pole-zero map for cable data r cable.6 p.u. ad l cable.4 p.u. whch gve τ cable.4 p.u. Small margs are used for o-load (p r ) ad large margs for recever output power equal to rated seder power (p r.).

62 54 Chapter 3. DC bus voltage cotrol To vestgate the robustess agast parameter ucertaty r cable s vared from. to. p.u. ad the cable tme costat s vared from. to.4 p.u. The root-locus s vestgated for a case where the recevg ed power s approxmately equal to rated power of the sedg ed coverter.e. p r s equal to oe. Ths s ot a strog lmtato sce t has bee foud that the load level affects the pole-zero map to a barely otceable extet. Fgure 3. ad Fgure 3.3 show the resultg root-locus for the poles ρ ad ρ 3 respectvely (Fgure 3.). The two other poles ρ ad ρ 4 are complex cojugate pars of the oes Fgure 3. ad Fgure 3.3 ad therefore ot cluded. Imag Axs 75 r cable. τ cable. 5 r.6 cable l cable 5 r cable. τ cable Real Axs Fgure 3.: Root-locus for pole ρ at p r. p.u. The traces are from top to bottom: r cable..6 ad. p.u. The dotted les show costat τ cable ad.4 p.u. from left to rght. Imag Axs τ. cable r cable. τ.4 cable r.6 cable r cable. l cable Real Axs Fgure 3.3: Root-locus for pole ρ 3 at p r. p.u. The traces are from top to bottom: r cable..6 ad. p.u. The dotted les show costat τ cable ad.4 p.u. from left to rght. Note that the pole s real valued for low l cable whe r cable. p.u.

63 3.4 Cable mpedace 55 From Fgure 3. ad Fgure 3.3 t s cocluded that a low cable resstace results a moderately damped system whch s also expected. Ths s further see from the overshoot appearg the DC bus voltage respose resultg from a load power step at low cable resstace ad tme costat see Fgure 3.4. The overshoot s due to the ρ 3 -ρ 4 pole par resultg from the selected dampg (3.). v s v r [V] p s p r [W] t [ms] Fgure 3.4: DC bus voltage (top) ad power (bottom) of the sedg (blac) ad recevg (grey) ed coverters at a output power step from zero to rated power whe r cable. p.u. l cable. p.u. ad thus τ cable. p.u. For a log tme costat of the cable the stuato s worse wth a supermposed oscllato o the overshoot (Fgure 3.5). The oscllato frequecy s close to 4 Hz correspodg to the locato of ρ (ad ρ ) Fgure 3.. O the other had whe r cable. p.u. the system s well damped but the recevg ed coverter operates at the lmt of overmodulato for rated output power. Furthermore the cable losses are hgh aroud % as dscussed earler. Therefore such a hgh cable resstace s ot recommeded. From ths vestgato t s cocluded that the DC bus voltage droop cotroller operates as teded for practcal cable parameters. The cable resstace s lmted by the rs of coverter over-modulato. The vestgated cable ductace most lely covers practcal stuatos.

64 56 Chapter 3. DC bus voltage cotrol v s v r [V] p s p r [W] t [ms] Fgure 3.5: DC bus voltage (top) ad power (bottom) of the sedg (blac) ad recevg (grey) ed coverters at a output power step from zero to rated power for the case wth r cable. p.u. l cable.4 p.u. ad thus τ cable.4 p.u. 3.5 Load sharg Load sharg for a fve-coverter DC rg bus (Fgure 3.) s vestgated smulatos. The etwor ad coverter parameters are gve Table 3.. Cable segmet (Fgure 3.3) s coected betwee coverter ad segmet betwee coverter ad 3 etc. Sce ths s a rg bus segmet 5 s coected betwee coverters 5 ad. To determe a approprate cable resstace (R cable Table 3.) t s assumed that the cable legth of each segmet s m ad that the maxmum curret desty s 4 A/mm eve f the rg bus s broe. The cable ductace (L cable ) s calculated assumg a dstace betwee the ceters of the coductors equal to twce the coductor dameter. Ths assumpto s also used the calculato of the cable capactace (C cable ). Both statoary ad traset load sharg are vestgated for master/slave ad droop DC bus voltage cotrol. Load sharg the case of droop cotrol wth voltage error restorato s also vestgated. Three coverters 3 ad 5 Table 3. are operated as sources. Coverters ad 4 are operated as loads. The sources ad loads are modeled as three-phase AC grds whch are galvacally separated. Cosequetly the dyamcs of sources ad loads are ot tae to accout ths vestgato.

65 3.5 Load sharg 57 Table 3.: Smulato model data. Coverter o Rated power S [VA] Le-to-eutral voltage E LN [V] Le frequecy f [Hz] Swtchg frequecy f sw [Hz] Le ductace L le [mh] Le resstace R le [Ω] DC bus capactace C dc [mf] Cable capactace C cable [F] Cable ductace L cable [µh] Cable resstace R cable [mω] DC bus voltage referece V dcref [V] The vestgato starts at a codto where the load coverters ad 4 (Table 3.) operate at o-load. From the tal o-load operatg pot the output power of coverter creases by 5% of rated power at t ms ad the output power of coverter 4 creases by 5% of rated power at t ms. Ths meas that for a deal system.e. wth zero cable mpedace the source coverters should also be loaded to half ther rated power at the ed of the smulato. I all the fgures show ths secto blac curves deote source coverter quattes ad grey deote load coverter quattes. Therefore quattes belogg to coverter sub-system are sold blac are sold grey 3 are dashed blac 4 are dashed grey ad 5 are dash-dotted blac. DC bus voltage droop cotrol Fgure 3.6 shows the smulato result for load sharg the case of DC bus voltage droop cotrol wth a P-type cotroller.e. wthout voltage error restorato. It s see Fgure 3.6 that load sharg wors properly both statoary ad traset codtos. The source coverters are loaded to approxmately.6 p.u. each o the ut base. The barely otceable but preset dfferece relatve loadg s a result of the resstace of the cable segmets. As expected voltage regulato s poor. However as log as the coverters do ot operate over-modulato ths s ot a problem. As dscussed earler ths chapter over-modulato s avoded by selectg a dstrbuto bus wth a moderate resstace.

66 58 Chapter 3. DC bus voltage cotrol 76 v v v 3 v 4 v 5 [V] p p p 3 p 4 p 5 [W] t [ms] Fgure 3.6: DC bus voltage (top) ad power (bottom) for DC bus voltage droop cotrol the case of a output power crease of.5 p.u. of rated load coverter power at t ms for coverter ad t ms for coverter 4 startg from p.u. both cases. DC bus voltage droop cotrol wth error restorato Fgure 3.7 ad Fgure 3.8 show the smulato results for load sharg the case of DC bus voltage droop cotrol wth a PI-cotroller.e. cludg voltage error restorato. The smulato result of Fgure 3.7 s for a cotroller equpped wth a costat tegrato tme costat ad the oe of Fgure 3.8 wth a load depedet tegrato tme costat. The tegrato s hbted whe the DC bus voltage at each source s sde a dead-bad of 5 V located o both sdes of the DC bus voltage referece 75 V. From Fgure 3.7 ad Fgure 3.8 t s see that load sharg s poor both cases. The loadg of the source coverters the case of DC bus voltage droop cotrol wth error restorato s roughly betwee.5 ad.7 p.u. o the ut base accordg to Fgure 3.7 ad Fgure 3.8. Load sharg mght be ehaced f dfferet voltage error dead-bads are specfed for each source coverter. However a mesh etwor le the rg bus vestgated here ths s a complcated tas. O the other had voltage regulato s ehaced compared to regular droop cotrol due to the tegral part. Stll approprate load sharg s cosdered as beg of more cocer.

67 3.5 Load sharg v v v 3 v 4 v 5 [V] p p p 3 p 4 p 5 [W] t [ms] Fgure 3.7: DC bus voltage (top) ad power (bottom) for DC bus voltage droop cotrol wth error restorato the case of a output power crease of.5 p.u. of rated load coverter power at t ms for coverter ad t ms for coverter 4 startg from p.u. both cases. 76 v v v 3 v 4 v 5 [V] p p p 3 p 4 p 5 [W] t [ms] Fgure 3.8: DC bus voltage (top) ad power (bottom) for DC bus voltage droop cotrol wth error restorato the case of a output power crease of.5 p.u. of rated load coverter power at t ms for coverter ad t ms for coverter 4 startg from p.u. both cases.

68 6 Chapter 3. DC bus voltage cotrol Master/slave DC bus voltage cotrol Fgure 3.9 llustrates load sharg the case of master/slave cotrol. As metoed earler the master receves actual power estmatos from all the other uts. The the master dstrbutes power refereces to the slaves.e. the other coverters also operated as sources. These power refereces could also be based o the DC bus voltage cotroller output. However the case vestgated here the power refereces fed from the master are oly calculated from the load coverter output power. The power refereces are scaled proporto to the rated power of each source cludg the master tself. Coverter 5 s assged as master ths case ad therefore delvers oe half of the source coverter output power. It should also delver the power requred to cotrol the DC bus voltage. Coverters ad 3 supply /6 ad /3 of the total power delvered to the loads respectvely. The trasets see Fgure 3.9 are due to DC bus voltage drop maly ad samplg delay. 76 v v v 3 v 4 v 5 [V] p p p 3 p 4 p 5 [W] t [ms] Fgure 3.9: DC bus voltage (top) ad power (bottom) for master/slave DC bus voltage cotrol the case of a output power crease of.5 p.u. of rated load coverter power at t ms for coverter ad t ms for coverter 4 startg from p.u. both cases. From Fgure 3.9 t s obvous that coverter 5 operates at a relatvely hgher loadg tha the other source coverters. Ths s due to the fact that ths coverter s the oly oe resposble for DC bus voltage cotrol sce the power refereces fed forward to the slaves are ot based o voltage cotrol.

69 3.5 Load sharg 6 Master/slave cotrol wth a PI DC bus voltage cotroller gves a statoary voltage error equal to zero at the master DC bus terface. Also load sharg ca be fully cotrolled. The ma dsadvatage of master/slave cotrol s the eed for commucato betwee the coverters. The requred badwdth of the commucato s determed by the eergy storg devces of the DC bus. If the amout of eergy stored the DC bus capactors s hgh the badwdth ca be low ad vce versa. I the smulato result (Fgure 3.9) the same DC bus capactor values as the prevously vestgated droop case are used. At the same tme the commucato badwdth s hgher tha the coverter curret cotroller samplg frequecy. Cosequetly the voltage cotrol ad load sharg show hgh performace ths case. The commucato badwdth could be reduced ths case ad stll the performace would be better tha for the vestgated droop methods. O the other had f commucato s lost the system would ot wor at all. 3.6 Cocludg remars A method to select the coverter DC bus capactace of each coverter coected to the DC dstrbuto bus s preseted. The maxmum cable resstace s specfed upo the marg to over-modulato. Furthermore the dyamc propertes are vestgated wth ad of the root-locus for varyg DC bus cable parameters. The vestgated droop cotrol method s smulated wth the coverter parameters derved from the aalyss both a twocoverter applcato ad a fve-coverter rg bus. From the two-coverter aalyss t s foud that for realstc cable data the system ca be modeled wthout tag the cable ductace to cosderato. Ths meas that system specfcato ad vestgato ca be made usg a resstve cable model a load-flow program. The fve-coverter DC bus rg bus s smulated wth realstc cable parameters for dfferet DC bus voltage cotrol methods. The P-type droop cotroller s selected for the vestgatos to follow due to the hgh performace terms of load sharg ad sce commucato betwee coverters s ot requred.

70

71 Chapter 4 Wd powered DC bus Wd power s oe of the most promsg reewable eergy sources. The reasos for ths are for example hgh effcecy also for the preset wd power techologes ad the fact that wd power turbes ca be located both oshore ad off-shore [53] ad both cases produce hgh power also for rather small stallatos. Ths meas that the ecologcal footprt ca be ept at acceptable levels. Aother beeft s that the rotatg mass costtutes a eergy storage whch meas that small wd varatos mght ot dsturb the power trasfer extesvely. I ths chapter t s vestgated f a DC dstrbuto system ca be operated oly wth wd powered geerators. The vestgato focuses o a load case where three wd power geerators are fed by a wd speed correspodg to rated power ad delvers power approxmately equal to half the rated to a DC grd wth two coverters delverg power to loads. The excess power fed to the wd turbes s removed by ptch agle cotrol. The problem ths case s that the turbe speed mght crease beyod the rated whch mght result severe mechacal stress. Aother problem s that the creased speed results a creased bac-emf of the geerators. I a worst-case scearo the bac-emf mght be so hgh that the cotrolled voltage source coverter looses cotrollablty of the curret ad stead operates as dode rectfers due to the freewheelg dodes. Most moder wd power turbes are speed cotrolled by meas of ptch agle cotrol. However ptch agle cotrol has a rather low badwdth wth tme costats the rage of secods. The chapter starts wth ptch agle cotrol ad the droop offset cotrol follows. The added features of coverter cotrol the case of wd power geerators.e. speed estmato ad feld weaeg are dscussed. Three dfferet dyamc load codtos are vestgated. 63

72 64 Chapter 4. Wd powered DC bus 4. Ptch agle cotrol I ths secto t s vestgated how the wd power turbes respod to a sudde blocg of the load coverters e.g. before ptch cotrol s fully establshed. The ptch agle s cotrolled such a way that the mechacal power delvered to the geerator s expressed as P ge where the avalable wd power s wd P P (4.) wd wd ptch 3 wd P K v (4.) where v wd s the wd speed ad K wd a costat. The power lost due to ptch agle cotrol s proportoal to the error betwee the referece ad actual mechacal speed ad gve by P ptch K ptch ( ω ω ) (4.3) The ptch agle cotroller ga s foud from the tme costat τ ptch ad the momet of erta J m K ptch m ref ptch m J m P ω m (4.4) τ wd P For trasets the followg dfferetal equato apples J m dω dt Assumg the tal codtos m Pwd Pptch Pge Twd Tptch Tge (4.5) ω m P P wd ge ( t ) ( t ) P ad P P wd ( t ) + ( t ) P P ge (4.6) the followg expresso s approxmately vald for the ptch agle cotroller ( t t ) τ ptch Pptch P ( e ) (4.7)

73 4. Ptch agle cotrol 65 whch gves the followg dfferetal equato wth the soluto m dω dt m P ( t t ) τ ptch e (4.8) J ω m τ ptch ωm() t P J m ( t t ) τ ptch ( e ) + ωm (4.9) where ω m s the mechacal speed at tme t. Thus the statoary mechacal speed s gve by τ ω + (4.) ptch m stat P ωm J m The worst-case crease s whe operatg at rated (dex ) speed ad power.e. ω mmax ω mstatmax ω m τ ptch P + ωm ωm (4.) J m Note that the maxmum speed crease τ ptch τ ptch ω m max ω + + m ω m (4.) J mωm H P s equal p.u. for dfferet wd turbes f τ ptch H costat (4.3) s the same for all the wd turbes. To obta smlar behavor the case of power varatos ths rato should be equal for the wd power aggregates. It s lely that the erta costat H s approxmately equal for the aggregates. Therefore the ptch agle cotroller tme costat should also be equal.

74 66 Chapter 4. Wd powered DC bus 4. Droop offset cotrol Droop offset cotrol (Fgure 4.) s troduced to hadle wd speed varatos. There are two ways to troduce ths offset. Frstly a exteral power referece could be added whch s trasferred to a curret referece see Fgure 3.5. Ths s used whe the supervsory cotroller orders that oe source should supply a certa amout of power whe the rest operate at dle codtos. Secodly the DC bus voltage referece could be altered such a way that a source s more lghtly or heavly loaded. Ths secto covers the secod method appled to wd power turbes where the turbe speed s used as a measure o the actual power delverg capablty. V dc V dcref }V dcref I refext I dc Fgure 4.: Droop offset cotrol. From the results of the prevous secto a droop offset cotroller ga used to dvde the actual avalable wd power equally ( p.u.) betwee the source coverters s establshed accordg to K ω V ω dcref max elmax τ P J ( δ ) ptch m z p δ V + ω dc el ω el (4.4) where z p s the umber of pole pars for the electrc mache ad ω el s the electrcal agular frequecy. A ew DC bus voltage referece s formed from V dcref ( z ω ωˆ ) V (4.5) dcref + Vdcref Vdcref + Kω p m ref where V dcref s the tal referece whch s equal to the o-load DC bus voltage. Ths meas that the droop characterstc s shfted up- or dowwards depedg o the dfferece betwee the speed referece ad the estmated electrcal speed. Thus a speed droop s formed. el

75 4.3 Speed estmato Speed estmato A permaet-maget sychroous mache (PMSM) s sutable for wd power applcatos for two reasos correlated to each other. Frstly f a multple pole geerator.e. a mache wth low mechacal base speed s used the mechacal gearbox ca be omtted reducg the weght ad the eed for mateace. Secodly the most sutable mache for low base speed s the sychroous mache at least compared to other three-phase maches e.g. the ducto mache. However t should be ept md that the weght of a multple pole mache s hgher tha the weght of a mache wth a low pole umber but lower f the gearbox s tae to accout. It should also be otced that a PMSM s more expesve tha a ducto mache. A curret cotroller smlar to the oe used for AC etwor coected coverters (Appedx B) s requred also for the cotrol of a PMSM. However the PMSM of a sgle wd turbe caot be regarded as a stff power source whch meas that the frequecy s ot eve ear costat. The speed ad posto eed to be estmated to fx the rotatg (dq) coordate system ad to calculate the reactve voltage drop fed forward the curret cotroller. To trac the speed varatos a speed ad posto estmator s eeded. The oe utlsed here s based o the results obtaed [3]. Frst the d-drecto bac-emf e d whch should be close to zero s estmated e d ud Rsd ref ˆel Lqq ref ω (4.6) where R s s the stator resstace ad L q the stator ductace the q-drecto. The agular frequecy s estmated from ωˆ el ωˆ el ( ω f ) ed (4.7) T sγ where T s s the durato of each samplg terval. The agular posto s estmated from θˆ [ θˆ +T ω T γ ( ω ) e ] π s ˆel s f d (4.8) The estmated speed s low-pass fltered accordg to ( ω ) ω f ω f + Ts ρs ˆ el ω f (4.9)

76 68 Chapter 4. Wd powered DC bus whch s the used to calculate sutable adaptato gas for the estmator [3] ρ γ ω f Ψ ρ γ ω f Ψ m m z z p p (4.) where Ψ m s the flux-lage ad ρ s the real valued double pole of the estmator. Accordg to [3] a proper choce for the pole s o ( 5 ) ρ ρ s. ω el /s (4.) where ρ s s the badwdth of the speed cotrol loop. I ths applcato the speed s ot actually cotrolled but stead a teral droop offset s created from the speed devato. Sce the speed vares slowly a wd power applcato a badwdth of Hz should be suffcet. Ths gves ρ rad/s (4.) s Detals o the dervato of the speed ad posto estmator are gve [3]. 4.4 Feld weaeg Durg abormal operato for example whe the load coverters are bloced the speed mght crease to a level cosderably hgher tha base speed. Ths meas that the duced bac-emf eq ω Ψ (4.3) mght reach levels so hgh that the cotrolled trasstor coverter starts to act as a o-cotrolled dode rectfer formed by the freewheelg dodes. To crcumvet ths potetal rs resultg lost cotrol of the DC bus voltage feld weaeg s troduced. I feld weaeg reactve power s cosumed so that the mache termal voltage s ept at the average level q s q m el m u R + ω L + e (4.4) where L d s the stator ductace the d-drecto. A cotrol law could be formed drectly from ths expresso. However ths mples a hgh ga ad d d q

77 4.4 Feld weaeg 69 sce the speed s estmated ths could result a oscllatory behavour. To reduce ths d of problem the d-compoet of the curret s fltered wth a frst order flter wth ω ρ / (4.5) lp d s The the dfferece betwee the bac-emf at rated speed ad the actual bacemf mus the actual feld weaeg compoet s fed to a PI-cotroller see Fgure 4.. elest L d m /z p PI e qmax dref G PI(s) G cov(s) d lpd s+ lpd G lp(s) e qest Fgure 4.: Cotroller structure for geerato of the d-curret referece used for feld weaeg acto. Note that the mache bac-emf s estmated. The ga ad tegrator tme costat of ths PI-cotroller s selected such a way that the closed loop poles of the feld weaeg sub-system wth the assumpto that the estmated speed s correct are gve by λ ( α d ) ωlp d (4.6) where α d s a weghtg factor to reduce the ga of the feld weaeg subsystem. A sutable value for ths factor s α.55 (4.7) d The ga ad tegrator tme costat used to geerate the d-curret referece requred for feld weaeg are gve by K T fw fw ( α ) ω d lp d L α d α d d Ψ z m p + ω el (4.8)

78 7 Chapter 4. Wd powered DC bus for a cotuous tme cotroller. For the smulato a sampled cotroller s used ad therefore bacward Euler trasformato [8] s appled. 4.5 Smulatos Three ma ssues are vestgated smulatos: wd speed varatos load sharg ad load coverter blocg. A rg bus etwor cofgurato (Chapter 3) s studed. The etwor ad coverter parameters are gve Table 4.. The d- ad q-drecto ductaces L d ad L q foud Table 4. approxmately correspods to the oes gve [3] for a PMSM wth a omal electrcal frequecy of 6.5 Hz (x a.95 p.u. o the mache base accordg to [3]) whch s recalculated to ft a mache wth omal electrcal frequecy equal to 5 Hz (x a.5 p.u. o the mache base accordg to [3]). Table 4.: Smulato model data. Coverter o Rated power S [VA] Le-to-eutral voltage E LN [V] Le/PMSM rated frequecy f [Hz] Swtchg frequecy f sw [Hz] PMSM d-drecto ductace L d [mh] PMSM q-drecto ductace L q [mh] PMSM Stator resstace R s [Ω] Le ductace L le [mh] Le resstace R le [Ω] DC bus capactace C dc [mf] Cable capactace C cable [F] Cable ductace L cable [µh] Cable resstace R cable [mω] DC bus voltage referece V dcref [V] The DC rg bus ad the cable segmets are arraged ad have the same data as Chapter 3. For the wd power aggregates the parameters are J τ m 4 gm /W z p 4. ptch s H s (4.9) where H s the erta costat.

79 4.5 Smulatos 7 The speed referece s mataed at ω mref 6.3 rad/s throughout all the smulatos. The momet of erta s farly low compared to what preset wd turbes exhbt. I the power rage cosdered a turbe momet of erta approxmately fve tmes hgher ca be expected. The teral droop offset cotrol s ot affected by ths fact sce ts ga s calculated based o a estmato of the momet of erta. The oly way that the reduced momet of erta affects the smulato results s therefore terms of the magtude of the crease or decrease the respose of the mechacal speed due to power varatos. The system has bee smulated wth fve tmes hgher momet of erta. Cosequetly τ ptch /H s fve tmes less ad K ω s slghtly less tha fve tmes hgher. It s foud that the resultg waveforms are smlar shape. The actual speed varato s determed by the tal speed ad the voltage varato s determed by the speed error. Three cases are studed. Frst wd speed varatos are cosdered. Secod load sharg s vestgated. Thrd a load coverter blocg stuato s cosdered. I all three cases the vestgato starts at a codto where the load coverters are loaded to half ther rated power respectvely. For a deal system.e. wth zero cable mpedace the source coverters should also be loaded to half ther rated power. For a realstc system cludg cable mpedace t s cumbersome to determe the maxmum allowable load coverter output power for a gve wd stuato by aalytcal methods. However the actual loadg of each source coverter ca be calculated wth a load flow program smlar to the oes used for AC system aalyss to gve the put power requred for a certa loadg. I all the fgures show ths secto blac curves deote source coverter quattes ad grey deotes load coverter quattes. Therefore quattes belogg to coverter sub-system are sold blac are sold grey 3 are dashed blac 4 are dashed grey ad 5 are dash-dotted blac. Wd dsturbace From the tal operatg pot the wd speed of aggregate suddely drops at t.5 s resultg a wd turbe put power reducto from rated level (5 W) to 4% of rated power ( W). Cosequetly the two other source coverters (3 ad 5) are more heavly loaded see Fgure 4.3. The creased loadg of coverters 3 ad 5 result a decreased DC bus voltage due to voltage droop cotroller acto. The power delvered from coverter s reduced sce the droop offset cotrol reduces V dcref for ths coverter. Thus ts voltage error decreases ad the power delvered va coverter s reduced.

80 7 Chapter 4. Wd powered DC bus 75 v v v 3 v 4 v 5 [V] Fgure 4.3: p p p 3 p 4 p 5 [W] t [s] Coverter DC sde voltage (top) ad power (bottom) for coverter to 5 at a wd power decrease of 5 W (6% of rated power) at t.5 s for coverter startg from 5 W (rated power). The power removed by ptch agle cotrol for wd power aggregate s show Fgure 4.4. Note that the power removed by ptch agle cotrol drops suddely at t.5 s due to the rapd decrease put power at ths stat. Both the droop offset cotroller ad the ptch agle cotroller rely o a exteral speed referece. Ths referece s assumed beg suppled from a supervsory cotroller used for the etre DC dstrbuted power system. The speed referece should be based o actual wd speed ad power delverg capablty. The commucato requred s assumed slow ad the speed refereces are ot altered durg the smulato. 5 p ptch [W] Fgure 4.4: t [s] The power removed at wd turbe due to ptch agle cotroller acto.

81 4.5 Smulatos 73 Load sharg From the tal operatg pot troduced above the output power of coverter crease by % of rated power at t.5 s ad the output power of coverter 4 crease by % of rated power at t. s see Fgure v v v 3 v 4 v 5 [V] p p p 3 p 4 p 5 [W] Fgure 4.5: Coverter DC sde voltage (top) ad power (bottom) for a output power crease of. p.u. of rated load coverter power at.5 s for coverter ad. s for coverter 4 startg from.5 p.u. both cases. I Fgure 4.5 t s show that load sharg wors properly both statoary ad traset codtos. Note the rapd steps the DC bus voltage whe the output power s chaged llustrated Fgure 4.5. These are due to voltage droop cotrol acto reducg the voltage because of the creased loadg. The slow varato DC bus voltage s a cosequece of teral droop offset-adjustmet caused by the speed error resultg from the reduced actual speed. The droop offset also strves to reduce the voltage order to dstrbute the total load amog the wd power uts. Actual mechacal speed of the wd turbes s show Fgure 4.6. The mechacal speed s reduced due to the creased loadg. Cosequetly the speed error creases resultg a dowward shft of the droop characterstc of each source coverter. At the same tme the power removed by ptch agle cotrol reduces due to the decreasg speed error. Therefore a ew operatg pot s establshed. t [s]

82 74 Chapter 4. Wd powered DC bus 8 ω m ω m3 ω m5 [rad/s] Fgure 4.6: t [s] Wd power turbe speed. Load blocg From the tal operatg pot troduced above coverter s bloced.e. ts output power s decreased to at t.5 s ad coverter 4 s bloced at t. s see Fgure 4.7. The coverters could be bloced for example because of a emergecy stuato or due to a fault. 79 v v v 3 v 4 v 5 [V] p p p 3 p 4 p 5 [W] Fgure 4.7: Coverter DC sde voltage (top) ad power (bottom) for a output power decrease of.5 p.u. of rated load coverter power at.5 s for coverter ad. s for coverter 4 startg from.5 p.u. both cases. As llustrated Fgure 4.7 load sharg wors properly also ths case. Aga the DC bus voltage levels at the coverter termals exhbt both rapd ad slow varatos. Note that the DC bus voltages approaches each other as t [s]

83 4.5 Smulatos 75 the loadg decreases due to the reduced resstve voltage drop expereced at lght load. The mechacal speed of the wd turbes s show Fgure 4.8. ω m ω m3 ω m5 [rad/s] Fgure 4.8: Wd power turbe speed. Note that the momet of erta used for the wd turbe smulato models are approxmately fve tmes lower tha what ca be expected from a real stallato. The speed crease Fgure 4.8 s rather hgh due to the comparably low momet of erta assumed for the wd power aggregates. At preset wd power turbes exhbt a momet of erta approxmately 5 tmes hgher tha used the smulato. O the other had turbe blade materal s becomg stroger whch mples that the weght ad thereby the momet of erta wll most lely be reduced for future wd power turbes. Posto ad speed estmator Fgure 4.9 shows the actual ad estmated electrcal speed for ut. Note that the badwdth of the speed estmator s suffcet for the applcato. The avalable power could be estmated from the ptch agle ad estmated mechacal speed. Therefore the estmated speed could be used also for other purposes for example motorg ad supervsory cotrol. 36 t [s] Fgure 4.9: ω el ω elest [rad/s] t [s] Actual (blac) ad estmated (grey) electrcal speed (agular frequecy).

84 76 Chapter 4. Wd powered DC bus Ptch agle cotrol The power removed by ptch agle cotrol for wd power aggregate s show Fgure 4.. The removed power approaches rated power at the ed of the smulato. Both the voltage droop offset cotroller ad the ptch agle cotroller rely o a exteral speed referece. Ths referece s cosdered as beg suppled from a supervsory cotroller used for the etre wd power system. The speed referece should be based o actual wd speed ad total DC bus power demad. Therefore ths requres some d of commucato betwee the supervsory cotroller ad each ut. I the smulatos ths commucato s cosdered as beg slow ad therefore the speed refereces are ot altered durg the smulato ru. p ptch [W] Fgure 4.: The power removed due to ptch agle cotroller acto. Feld weaeg The referece ad actual d- ad q-currets for coverter sub-system are show Fgure 4. ad Fgure 4. respectvely. The d-curret referece s egatve due to the fact that the speed s hgher tha the base speed. A egatve d-curret mples that reactve power s cosumed by the coverter. dref d [A] 3 4 t [s] t [s] Fgure 4.: The d-curret (blac) ad ts referece (grey).

85 4.5 Smulatos 77 The q-curret referece s a measure o the actve power delvered from the DC to the AC sde of the coverter. Sce the power s delvered from the AC sde of coverter sub-system the q-curret referece s egatve. qref q [A] t [s] Fgure 4.: The q-curret (blac) ad ts referece (grey).

86

87 Chapter 5 Fault detecto ad clearace Persoal safety ad preveto of property damage are mportat factors of covetoal AC power systems. For the vestgated DC power system ths s maybe eve more mportat sce the star pots of the sources ad loads are left ugrouded. As dscussed Chapter 3 the star pot s ot grouded or grouded through hgh mpedace order to effectvely atteuate eutral currets. Otherwse hgh ampltude eutral currets could flow betwee sources ad loads sce the used coverter topologes do ot provde ay meas to cotrol zero-sequece or thrd order harmoc currets. Short crcut (coductor-to-coductor) ad groud (coductor-to-groud) faults should be detected ad cleared to provde persoal safety ad protecto of equpmet. The safety requremets o DC dstrbuted power systems should most lely comply wth the oes foud [45] for resdetal photovoltac systems. Ths chapter starts wth a presetato of the vestgated DC power system groudg scheme together wth ts fusg. The fuses are teded to act o low mpedace faults. The dfferet fault stuatos are preseted through smulatos. Sce detecto ad selectvty are mportat to guaratee proper operato these ssues are also dscussed. 5. Groudg ad fusg Each coverter s coected to the DC rg bus through a cable ode. The cable ode cotas groudg fuses crcut breaers ad curret trasducers requred for protecto (Fgure 5.). The protecto capactors C p or more correct groudg capactors are selected so that the tme costat of groud 79

88 8 Chapter 5. Fault detecto ad clearace fault currets s suffcetly log for proper detecto. The dea of the fault detecto capactors s that they should provde a mmum groud fault curret depedet of the cable capactace. Sce the fault curret s a quatty maly determed by the cable propertes the capactace of the fault detecto capactors s determed by the cable mpedace ad ot the rated power ad voltage of the coverter coected to the cable ode. Ths maes sese sce the same type of cable s used throughout the etre rg bus due to the fact that the cable ratg should ot lmt the power flow the case of a broe rg bus. R b- L b- R a dcap L a dcbp R b L b R a+ L a+ C g- C g+ C g- dca dcb C g+ L b- R b- L a R a L b R b L a+ R a+ C p C p v dc C dc L le e LN Fgure 5.: Cable ode wth two T-model cable segmets ad oe coverter coected. The terfaces to the cable segmets are deoted A (left) ad B (rght). 5. Fault stuatos To vsualse the fault currets oly low mpedace faults ( Ω fault resstace) are vestgated. For ssues regardg persoal safety ths s a by far too low fault resstace. Therefore hgh mpedace faults (3 Ω fault resstace) are dscussed a later secto where fault detecto s emphassed. The reaso for

89 5. Fault stuatos 8 dvdg the fault stuatos ths maer s because vsualsato of fault currets for hgh mpedace faults s strogly related to the detecto method. The vestgated fve-coverter DC dstrbuto system s detcal to that of Chapter 3. The protecto or fault detecto capactors have a capactace of C p µf ad a equvalet seres resstace of R ESRCp mω. Seres resstors are serted o purpose later o to guaratee a mmum tme costat of fault currets. The capactace s selected based o results obtaed a later secto. Short crcut o the DC sde I the case of a short crcut o the DC sde the DC bus capactors located at each coverter dscharge. For low cable mpedace the DC bus voltage decreases wth tme costats prcple equal all parts of the DC bus. Ths mples that all coverter DC bus capactors cotrbute to the fault curret ad the fault s detected all cable odes. Eve the case of low fault resstace the tme costat of the fault curret s farly log due to the hgh DC bus capactace of the coverters. I Fgure 5. a short crcut occurs the mddle of cable segmet.e. betwee coverters ad at t. ms. The fault resstace s R Fault. Ω. Fgure 5.: dcbp dcap [A] t [ms] Fault currets dcbp for cable ode (blac) ad dcap for cable ode (grey) the case of a short crcut o the DC sde betwee coverters ad at t. ms. The fault resstace s R Fault. Ω. Note that the tme costat of the fault curret s ot of sgfcat mportace for short crcut faults o the DC sde whe stff sources or sources possessg hgh erta are feedg the system. Ths s due to the fact that for a DC sde short crcut the bus voltage decreases oly to the pot where oe of the trasstor coverters starts to operate as dode rectfer. Thus the source starts to cotrbute drectly to the short crcut curret through the freewheelg dodes of the coverter.

90 8 Chapter 5. Fault detecto ad clearace Short crcut o the AC sde For a short crcut o the coverter AC sde the ma fault curret cotrbuto flows from the eergy source. If the source s stff the fault curret remas after the traset. Ths s comparably easy to detect. The fault curret s strogly related to the fault locato. If the short crcut appears close to the coverter the fault ca be detected by the over-curret alarm of the coverter f the fault mpedace s low. If the fault occurs sde the geerator or flter wdgs or betwee a strog grd ad the flter ductors the fault curret mght flow almost etrely from the AC source eve the case of low mpedace faults. I such cases the fault s cleared by the fuses. Groud fault o the DC sde For a groud fault all the protecto capactors cotrbute to the fault curret. Assume that the fault resstace betwee the postve supply ral ad groud or commo s deoted R Fault see Fgure 5.3. v Lcf v Rcf Fault / Fault / v Cp v ESRCp L cf C p R ESRCp Fault/ R cf R Fault v RFault Fault Fgure 5.3: Equvalet crcut for groud fault o the DC sde. Fgure 5.4 shows the smulato result for a postve supply ral to groud fault betwee coverter ad. The fault resstace s R Fault. Ω. 5 dcbp dcap [A] Fgure 5.4: t [ms] Fault currets dcbp for cable ode (blac) ad dcap for cable ode (grey) the case of a low mpedace groud fault o the DC sde betwee coverters ad at t. ms. The fault resstace s R Fault. Ω.

91 5. Fault stuatos 83 Note the short tme costat of the fault currets Fgure 5.4. To ehace fault detecto seres resstors are coected so that the tme costat s ot depedet o the ESR of the groudg capactors. The curret flowg through R Fault to groud s deoted Fault. The fault curret dvdes betwee the protectve capactors such a way that ( Cp Cp ) Fault (5.) where s the umber of cable odes. If the cable resstace s low the fault curret dvdes approxmately equal whe the capactors are of equal capactace.e. ( Cp Cp ) Cp Fault (5.) If the fault s o the mddle of the cable segmet half fault curret flows from each sde see Fgure 5.3. I ths case the capactor curret s related to the fault curret accordg to Cp ad the curret the equvalet ductor s Fault (5.3) Lcf Fault Rcf (5.4) Sce the fault locato s the mddle of the cable R cf ad L cf correspod to oe quarter of the total resstace ad ductace of the cable segmet. A dfferetal equato s establshed from Krchoff s voltage law appled to the equvalet crcut of Fgure 5.3 d vcp R ESR Cp Rcf R dv Fault Cp v Cp dt Lcf Lcf Lcf dt Lcf C p (5.5) Cosequetly the equvalet fault resstace s gve by R Rcf RESR Cp RFault + (5.6) Fault eq +

92 84 Chapter 5. Fault detecto ad clearace The egevalues of the dfferetal equato are gve by Fault eq RFault eq ± L cf L cf R λ (5.7) Lcf C p The soluto to the dfferetal equato s Cp t t () t Ae λ λ + Be v (5.8) Sce L <<C p the egevalues λ are real valued. The capactor curret s Cp () t () t λ t λ t dvcp C p C paλ e + C pbλe (5.9) dt The tal voltage equals oe half of the DC bus voltage ad the tal curret equals zero due to the ductve part of the cable.e. v Cp Cp ( ) ( ) A + B V C p dc Aλ + C B p λ Therefore the costats of the soluto to the dfferetal equato are (5.) λ Vdc A λ λ λ V B λ λ dc (5.) The tme stat of maxmum curret s gve by (λ <λ <) λ t pea l (5.) λ λ λ To select approprate fuses the resultg I t has to be calculated. Ths s frst doe for the capactor curret. Cp ( λ + λ ) Vdc λλ dt C p (5.3) λ ( λ λ ) ( λ + )

93 5. Fault stuatos 85 Sce the curret flowg through the fuses s tmes hgher Fuse C p ( ) V dc Cp dt dt Cp λ λ dt ( λ + λ ) ( λ λ ) ( λ + λ ) (5.4) V 8 dc C R p Fault eq + C C prfault eq prfault eq L cf V 4 dc C R p Fault eq Accordg to smulatos ths expresso yelds a overestmato of the I t the fuse s exposed to by approxmately %. The ma reasos for ths devato are that the pea curret s lower tha expected ad that I t s oly calculated whe the curret exceeds the rated curret the fuse model. Groud fault o the AC sde A groud fault o the AC sde s more complcated to vestgate aalytcally tha o the DC sde due to the susodal ature of the le voltage ad curret resultg tal codtos depedet o the tme stat of the fault occurrece. Stll expressos for the groud fault curret are derved. A expresso for calculatg the stress o fuses terms of I t s ot derved. Fgure 5.5 shows a equvalet crcut for a AC sde phase-to-groud fault. Fault / Fault( -)/ e LN C groud R groud Lle-LFault R Fault v LFault L Fault v RFault Fault s C dc s C p V dc C p Fault / v Cp v Cp Fault/ Fault( -)/ Fgure 5.5: Phase-to-groud fault o the AC sde. Due to the hgh mpedace betwee the eutral (or star) pot of the AC sde trasformer or mache ad the groud the ma cotrbuto of the fault curret flows from the DC sde through the coverter to the fault locato.

94 86 Chapter 5. Fault detecto ad clearace The fault mght be located o ether sde of the AC sde ductors or eve sde the ductors. Therefore LFault L le (5.5) Fgure 5.6 shows the smulato result for a R-phase-to-groud fault of coverter. The fault resstace s R Fault. Ω. The fault s located so that L Fault L le. Therefore the fault currets suppled from the coverter s comparably low. dcbp dcap [A] Fgure 5.6: t [ms] Fault currets dcbp for cable ode (blac) ad dcap for cable ode (grey) the case of a low mpedace groud fault o the AC sde of coverter at t. ms. The fault resstace s R Fault. Ω. The fault resstace.e. the resstace betwee the phase coductor ad groud at the fault locato s deoted R Fault as before. The voltage across the fault s gve by Cp ( s ) vcp s ( vcp + vcp ) vcp s Vdc vcp u s v + (5.6) where u s the output voltage of the partcular phase of the coverter ad the correspodg swtch state s deoted s[]. The capactor currets ad fault curret are related accordg to Fault Ths results a dfferetal equato (5.7) Cp Cp d vcp dt R + L Fault Fault dv dt Cp + L Fault C p v Cp L Fault C p s V dc (5.8) Note that the ESR of the groudg capactors s eglected ths case.

95 5. Fault stuatos 87 The roots to the characterstc polyomal are gve by RFault RFault ± L Fault L Fault λ (5.9) LFaultC p For a hgh fault resstace the egevalues are real ad the characterstc soluto s gve by (5.8). However also for rather hgh fault resstace the poles are complex due to the fact that L Fault >>C p. I ths case the poles are expressed as λ σ ± jω If the swtch state s averaged the followg s vald (5.) ( + dˆ ω t) uˆ s d sωt s + Vdc (5.) whch gves the geeral soluto v Cp σ ( t t ) ( A cos( ω ( t t )) + B s( ω ( t t ))) e Vdc + V + ( ω ) ˆ LFaultC p sωt ωrfaultc p cosωt d ( ω L C ) + ( ω R C ) Fault p Fault p dc + (5.) The costats A ad B are determed by the tal codtos whch are depedet o the tme stat whe the fault occurs. However t s also see that there s a statoary soluto whch s ot damped but remas. Ths soluto s obtaed also for real egevalues. Oly ths part of the soluto s vestgated further. The capactor curret the case of hgh fault resstace s approxmately gve by Cosequetly the fault curret s dvcp Vdc C p dˆ sω t (5.3) dt R Cp Fault Vdc Cp dˆ sω t (5.4) R Fault Fault

96 88 Chapter 5. Fault detecto ad clearace 5.3 Detecto ad selectvty Whe a groud fault occurs the fault curret at the cable ad coverter terfaces of the cable odes flow the same drecto. I other words a groud fault results commo mode currets. If the fault resstace s low a hgh commo mode curret flows. Ths s easly detected by subtracto of the cable currets. If the fault resstace s hgh smple subtracto s ot feasble due to ose ad offset. Therefore two dfferetal curret measuremets are made at each coverter ode (Fgure 5.7). The trasducers measurg dfferetal currets could be placed so that the commo mode curret flowg to the cable ode from each cable segmet s measured stead. Ths s further dscussed at the ed of the chapter. The voltage across the capactors could also be measured to detect a groud fault but ot to localse the fault [54]. a p b p a dcap dcdff dcbp b dcdff C p C p c p c Fgure 5.7: Detal of the placemet of the curret trasducers the cable odes. The terfaces are deoted A (left) B (rght) ad C (bottom). Wth referece to Fgure 5.7 the dfferetal currets dcdff ad dcdff are measured so that dcdff dcdff dcap dcap + + dca dca + dcbp dcbp + dcb dcb (5.5) To crcumvet the problem of calculatg the dfferece betwee two fault currets resultg a low dfferece the measuremets are dfferetal as prevously metoed. The resultg wdg schemes for the trasducer cols are show Fgure 5.7.

97 5.3 Detecto ad selectvty 89 Short crcut Short crcut s detected by measurg over-curret both for the DC ad AC sdes. For the DC sde the curret the postve rals of the cable terfaces at the ode.e. dcap ad dcbp Fgure 5.7 are measured. Whe over-curret s detected the drecto to the fault s also determed. O the AC sde overcurret s detected by the trasducers measurg at least two of the phase currets requred for vector cotrol (Appedx B). Each cable ode s equpped wth a cotroller for decso o approprate acto whe a fault s detected. Commucato betwee the cable odes ca also be used to dstgush the locato of the fault. The eed for commucato s further dscussed later ths secto. Groud fault o the DC sde Some terestg observatos are made for groud faults o the DC sde. Whe the magtude of dcdff s hgher tha twce the magtude of dcdff the the fault s a groud fault o the DC rg bus ad ot betwee the cable ode ad AC source. If dcdff s egatve the groud fault s betwee the postve ral of the DC bus ad groud. If dcdff s postve the groud fault s betwee the egatve ral of the DC bus ad groud. Whe dcdff ad dcdff have the same sg.e. both are postve or both are egatve the groud fault s o the A-sde of the cable ode (Fgure 5. ad Fgure 5.7). If dcdff ad dcdff have opposte sg the groud fault s o the B-sde of the cable ode. Whe commucato wth earby coverters s used the observatos above are used to detect that a DC bus groud fault s preset ad also the locato sce oe of the cable odes at the faulted cable segmet dcates fault o ts A-sde ad the other at the same cable segmet dcates fault o ts B-sde. If commucato betwee earby coverters s ot utlsed fault localsato s more complex. I ths case the fault currets dcdff ad dcdff are stead tegrated whe dcdff exceeds a certa threshold level sgallg a fault stuato. Now the dea s to create a tegral creasg wth the same speed for the cable odes close to the fault but cosderably slower for the cable odes far from the fault locato. There are two reasos why ths s mportat. Frstly the fault dcator should be sgfcat so the correct cable odes detect the fault frst ad dscoects the cable segmet. Secodly the crcut breaers have a rather log operatoal tme whch mples that cable odes far from the fault locato also mght detect the fault before t s cleared by the most approprate cable odes.

98 9 Chapter 5. Fault detecto ad clearace I the case of a ubroe DC rg bus the fault curret flows to the fault locato from both eds of the cable segmet wth approxmately the same magtude but wth opposte sg. Ths meas that dcdff wll have hghest ampltude for the cable odes close to the fault. If the protecto capactors are of equal capactace these two currets are gve by dcdff ( ) dcdff ( ) Cp (5.6) The correspodg tme tegral s gve by dcdff V dc ( ) Cpdt ( ) C p ( ) C pvdc dt (5.7) For the cable ode ext to the faulted cable ode away from the fault the correspodg curret s dcdff ( ) dcdff ( ) Cp 3 3 (5.8) or more geeral terms dcdff ( ( c + ) ) dcdff ( ( c + )) Cp (5.9) where c s the umber of cable segmets betwee the cable ode ad the fault. Ths meas that for a low umber of cable odes dcdff s just tegrated ad the trp level s determed as ( 3) C pvdc < dcdff dt < ( ) C pvdc Trp level (5.3) Already from the prevous expresso t s clear that ths method s complcated to mplemet the case of hgh umber of cable odes. Frstly the trp curret s hgh for hgh ad the fault curret levels for the dfferet cable odes are close to each other magtude. Secodly the tegral for a ufaulted cable ode mght reach the trp curret whle the crcut breaer s operated for the faulted cable ode due to the log operato tme for preset crcut breaers. The stuato becomes worse whe oe fault s already cleared ad the rg structure s broe. Now dcdff s ot determed by the total umber of cable odes but by the umber of cable odes at each sde of the fault. Therefore the approprate trp curret level caot be estmated.

99 5.3 Detecto ad selectvty 9 However f each coverter assumes a worst-case scearo ths mght be solved. To do ths each dcdff tegral s multpled wth a costat so that the crcut breaer s operated whe T T dcdff dt ( ) dcdff dt ITrp (5.3) where s the order of the cable ode ( for the cable odes where the bus s already broe) whch s depedet o the drecto of the fault curret sce dcdff dt ( ) (5.3) dcdff dt ad T s the trp tme. The dea s that the ga should be selected such a way that the fault codtos are evaluated sequetally. Ths meas that a cable ode s ot allowed to dscoect a cable segmet uless t ca guaratee that f the fault should be dscoected by a cable ode dowstream t would already have bee doe ad the fault curret would ot flow aymore. The same trp level I Trp s used for all the cable odes. Therefore where T T ( ) dcdff dt ITrp ( ( ) ) dt (5.33) T T + T dcdff sc (5.34) where T sc s the operato tme for the crcut breaer. Thus T T + Tsc dcdff dt (5.35) T ( ( ) ( ( ) ) ) dcdff dt ( ( ) ) If t s assumed that the tme costat of the fault curret s log compared to the tme eeded to operate the relay multpled by the umber of cable odes.e. τ >> T sc (5.36) λ

100 9 Chapter 5. Fault detecto ad clearace t ca be assumed that the fault curret s costat durg a tme terval equal to T sc. Ths yelds ( ( ) ( 3) ) ( T ) ( ) ( T ) 3 sc (5.37) whch mples that the detecto tme for cable ode s determed from T ( 3) ( ( ) ( 3) ) T (5.38) For the cable ode most far from the fault locato.e. the oe at the upstream ed the tme s gve by sc T T + T sc T + T 3 sc sc ( 3 ) ( 3 ) T sc (5.39) Ths cable ode should detect the fault last. Sce there are at most - cable segmets the tme requred for detecto s ad assumg equalty gves ( ) T sc T (5.4) 3 ( 3 ) (5.4) whch yelds the costat (5.4) ( ) 3 or ( ( ) ) + ( ) (5.43) for the geeral case. If t s assumed that the ( j ) ( j + ) + (5.44) j j

101 5.3 Detecto ad selectvty 93 The approprate trp tme s foud for each cable ode by multplyg the ga determed above ad the tegral of the dfferetal curret dcdff whe the trp level s the same for all the odes. As a result each cable ode wats a tme perod proportoal to the umber of cable odes the drecto of the fault curret. Ths fuctoalty could also be mplemeted as a pure tme delay. However the descrbed method s oly applcable f the tme costat of the fault curret s log compared to the umber of cable segmets multpled by the crcut breaer operato tme. Otherwse the fault detector caot dstgush betwee fault curret removal due to dscharged protecto capactors or crcut breaer operato. The most secure operato to do whe a secod fault s detected s to shut dow the etre rg bus. Ths mght seem le a drastc soluto but f oe groud fault already has occurred the system eeds servce ayway. The other method relyg o commucato betwee earby coverters or cable odes do ot suffer from ths d of problem ad the DC dstrbuto system could be segmeted dow to coverters operatg pars wthout ay problem. It s lely that the terest for such a opto s depedet of the umber of coverters operatg o the DC rg bus as ths determes the eed for ths d of slad operato. Groud fault o the AC sde Smlar to the prevous secto o groud faults o the DC sde a umber of observatos are made for groud faults o the AC sde. Whe the magtude of dcdff s hgher tha the magtude of dcdff the fault s a groud fault o the AC sde of the partcular coverter coected to the rg bus. The magtude of dcdff s tme depedet due to the susodal voltage. I the same way as for a DC sde fault the sg combato of dcdff ad dcdff determes the drecto to fault for each cable ode. Therefore f dcdff ad dcdff have the same sg the fault s located to the left of the cable ode.e. o ts A-sde. If dcdff ad dcdff have opposte sg the fault s located to the rght of the cable ode.e. o ts B-sde. Selectvty s provded also ths case sce the coverter wth a faulted AC sde does ot sgal a DC fault to other cable odes. Cosequetly oly the cable ode at the fault locato detects the fault accurately as a beg a AC sde fault. However the false DC bus groud fault detected by other coverters s ot acowledged ad o attempts to clear the detected but o-exstet DC bus fault s made. Ths mples that commucato yelds the same advatage detecto of AC sde faults as for DC sde faults.

102 94 Chapter 5. Fault detecto ad clearace 5.4 Smulatos As a result of the prevous vestgato commucato s utlsed the smulatos. Wthout commucato oe groud fault allows further operato. For a secod fault the system should be shut dow because selectvty caot be guarateed. Whe commucato s utlsed there s o such lmtato. As a matter of fact the DC etwor ca be segmeted dow to coverters operatg pars. The trp lmt used for the tegrated fault currets s selected as Cp Itrp C pvdc dt (5.45) Sce the magtude of the dfferetal fault currets dcdff ad dcdff are at least twce the curret magtude of the protecto capactors the trp level s reached also for. Ths s mportat the case of a heavly segmeted DC dstrbuto system. The capactace of the protecto capactors s determed so that the tme to detect a hgh mpedace fault s lmted to prevet from persoal jury. Furthermore the tme costat should be suffcetly log for proper detecto of low mpedace faults close to the cable ode for a low umber of cable odes. To satsfy both demads the capactace should be selected from the tme requred for detecto of a hgh mpedace fault wth fault resstace correspodg to the resstace of a huma beg. Here ths resstace s assumed to equal 3 Ω. For a hgh mpedace fault dcdff ( ) ( ) V Fault (5.46) R dc Fault for the cable odes coected to the faulty cable segmet. For a heavly segmeted DC dstrbuto bus () the tme to detect a fault s t detect Itrp C prfault (5.47) dcdff For C p µf ths mples that t detect 6 ms. The crcut breaer operatg tme should be added to get the total tme to clear the fault. Ths tme s ofte the rage of ms. Here ms s used due to the o-ductve

103 5.4 Smulatos 95 characterstc of cables. The relays are modeled as varable resstors wth ostate resstace of. mω ad a off-state resstace of. MΩ. The trasto betwee these two states s modeled as lear wth respect to tme. To esure that low mpedace faults are detected a resstor s coected seres wth each protecto capactor. I ths case Ω s recommeded whch yelds a mmum tme costat of ms for the fault curret. I [6] a purely resstve groudg system s used to lmt the fault curret to prevet humas from electrc shoc. The dfferetal fault currets dcdff ad dcdff ad the postve ral currets dcap ad dcbp wth referece to Fgure 5.7 are measured. Note that the measured fault currets are low-pass fltered wth brea-over frequecy of 5 Hz to atteuate swtchg frequecy dsturbaces. The dfferetal fault currets are tegrated f they exceed a certa lmt. The lmt s set equal to the maxmum offset of the curret trasducers whch s assumed to be ma. Thus ad dcdff-dcdff (5.48) + tsample dcdff f dcdff > offset I dcdff- else dcdff-dcdff (5.49) + tsample dcdff f dcdff > offset I dcdff- else where γ s a forgettg factor. The forgettg factor s set based o the fault sgal reset tme accordg to tsample (5.5) t reset A sutable reset tme s s. Groud faults are detected through GroudFault A ((( Idcdff > ) ad ( Idcdff > Itrp ) ( Idcdff < ) ad ( Idcdff < Itrp ))) ( I < I ) or ad dcdff dcdff (5.5)

104 96 Chapter 5. Fault detecto ad clearace GroudFault B ((( Idcdff < ) ad ( Idcdff > Itrp ) ( Idcdff > ) ad ( Idcdff < Itrp ))) ( I < I ) or ad dcdff dcdff (5.5) I ths applcato there s o dstcto betwee groud fault o the coverter DC sde (C) ad the coverter le sde (AC) terfaces. Istead ( dcdff abs trp dcdff dcdff ( I > I ) ( I I )) GroudFaul tc ad > (5.53) s used for both. The tegral of the absolute value of dcdff s calculated accordg to dcdff- (5.54) + tsample dcdff f dcdff > offset I dcdffabs dcdff- else Short crcut faults are detected by evaluato of A ( dcap < Cablemax ) B ( dcbp < Cablemax ) (( dcap > Cablemax ) ( dcbp Cablemax ) ( > ) ( ) ShortCrcut ShortCrcut C (5.55) (5.56) ShortCrcu t or > (5.57) ShortCrcu t or > (5.58) AC a lemax b lemax For ShortCrcut AC oly two phase currets are evaluated sce oly two are eeded for vector cotrol purposes assumg that the zero-sequece curret equals zero. The followg logcal varables are set f a fault s detected LocalFault A (( ot Dscoected ) ad ( GroudFault or ShortCrcut )) LocalFault B A (( ot Dscoected ) ad ( GroudFault or ShortCrcut )) LocalFault C B (( ot Dscoected ) ad ( GroudFault or ShortCrcut )) C A B C A B C (5.59) (5.6) (5.6)

105 5.4 Smulatos 97 The varables Dscoect are used to start a relay dscoect operato. The varables Dscoected are held also after the fault s cleared. Dscoect A Dscoected Dscoect B Dscoected Dscoected Dscoect Dscoected ( LocalFault A ad RemoteFaultA ) ( DscoectA or Dscoected A ) ( LocalFaultB ad RemoteFaultB ) ( Dscoect or Dscoected ) (5.6) A (5.63) (5.64) B (5.65) B Dscoect C LocalFault C (5.66) AC AC C ( DscoectC or DscoectedC ) ( ShortCrcut AC or LocalFaultC ) ( Dscoect or Dscoected ) (5.67) (5.68) (5.69) The varables RemoteFault are set by the fault detectors the remote ed ad trasferred to the ode the drecto of the fault. I ths way each cable ode seds two sgals ad receves two sgals for fault localsato. The relay operates o two sgals the Dscoected varable ad oe varable dcatg the status of the fuses termed FusesOK. AC B AC ( ot Dscoected A ad A ) ( ot Dscoected B ad B ) ( ot DscoectedC ad C ) ( ot Dscoected ad FusesOK ) OperateA FusesOK (5.7) OperateB FusesOK (5.7) OperateC FusesOK (5.7) Operate AC (5.73) Ths mples that each cable ode must collect four addtoal sgals for each set of fuses. To verfy the prevous statemets several cases are vestgated smulatos. Frst a case wth a. Ω groud fault betwee the postve supply ral ad groud s smulated. The fault occurs betwee coverter ad at t. ms see Fgure 5.8. AC AC

106 98 Chapter 5. Fault detecto ad clearace dcdff dcdff [A] I dcdff [mas] 5 5 Fgure 5.8: t [ms] Top: Fault currets dcdff (sold) ad dcdff (dashed) for coverter (blac) ad coverter (grey) the case of a groud fault o the DC sde (postve supply ral-to-groud) betwee coverters ad at t. ms. Bottom: Itegrated fault curret I dcdff for coverters (blac) ad (grey). The fault resstace R Fault s equal to. Ω. A groud fault o the DC sde s detected by the fact that I dcdff reaches the trp lmt I trp 3.75 mas accordg to (5.45) see Fgure 5.8. The tegral cotues to crease beyod the trp lmt due to the comparably log operato tme of the relays. The sg determes the drecto to the fault locato. The result of the same smulato wth fault resstace equal to 3. Ω s show Fgure 5.9. From both fault stuatos t s apparet that the sg combato of the dfferetal currets dcates that cable ode detects a fault o ts B-sde ad cable ode o ts A-sde. The fault s detected ad localsed. If the rg bus s broe due to a prevous fault the dfferetal currets do ot have equal magtude for the two cable odes whch mples that the fault s ot detected smultaeously. Fgure 5. shows the dfferetal currets dcdff ad dcdff the case of a low mpedace groud fault o the AC sde (. Ω betwee R-phase ad groud). Note that cable ode detects a groud fault o ts A-sde sce both dcdff ad dcdff are egatve ad the absolute value of dcdff s hgher tha the oe of dcdff. Cable ode detects the fault as a groud fault o the AC sde ad does ot sed a fault sgal to cable ode. The fault dcator ths case s calculated as the tme tegral of the absolute value of the dfferetal curret dcdff.

107 5.4 Smulatos 99 dcdff dcdff [ma] I dcdff [mas] Fgure 5.9: t [ms] Top: Fault currets dcdff (sold) ad dcdff (dashed) for coverter (blac) ad coverter (grey) the case of a 3. Ω groud fault o the DC sde (postve supply ral-to-groud) betwee coverters ad at t. ms. Bottom: Itegrated fault curret I dcdff for coverters (blac) ad (grey). dcdff dcdff [A] I dcdffabs [mas] t [ms] Fgure 5.: Top: Fault currets dcdff (sold) ad dcdff (dashed) for coverter (blac) ad coverter (grey) the case of a. Ω groud fault o the AC sde (Rphase-to-groud) of coverter at t. ms. Bottom: Itegrated fault curret I dcdff for coverters (blac) ad (grey).

108 Chapter 5. Fault detecto ad clearace The reaso for calculatg the tegral of the absolute dfferetal curret to determe the trp stat s ot obvous the case of low fault mpedace. However f the same smulato s made wth a groud fault mpedace of 3. Ω (Fgure 5.) t s foud that the dfferetal currets are AC quattes. Therefore the absolute value s used. The AC compoet could also be fltered out whch gves the possblty to dstgush betwee faults o the AC sde ad the coverter-to-cable coecto (C terface). dcdff dcdff [ma] I dcdffabs [mas] t [ms] Fgure 5.: Top: Fault currets dcdff (sold) ad dcdff (dashed) for coverter (blac) ad coverter (grey) the case of a groud fault o the AC sde (R-phase-togroud) of coverter at t. ms. Bottom: Itegrated fault curret I dcdff for coverters (blac) ad (grey). The fault resstace R Fault s equal to 3. Ω. Multple faults The groud fault protecto scheme should wor for multple faults. Therefore a case wth two low mpedace faults (. Ω) s smulated. Frst a short crcut occurs o the DC bus betwee coverters 4 ad 5 at tme t. ms. Secod at t. ms a groud fault occurs betwee the postve supply ral of the DC bus ad groud. The fault currets for coverter ad are show Fgure 5.. It s evdet from Fgure 5. that the magtude of dcdff s o loger equal for the two cable odes. Ths s a cosequece of the fact that the rg bus s broe resultg a uequal umber of cable odes cotrbutg to the fault curret o each sde of the fault.

109 5.4 Smulatos dcdff dcdff [A] I dcdff [mas] t [ms] Fgure 5.: Top: Fault currets dcdff (sold) ad dcdff (dashed) for coverter (blac) ad coverter (grey) the case of a groud fault o the DC sde (postve supply ral-to-groud) betwee coverter ad at t. ms. Bottom: Itegrated fault curret I dcdff for coverters (blac) ad (grey). The fault resstace R Fault s equal to. Ω. Note that the rg bus s broe betwee coverters 4 ad 5 due to a short crcut occurrg at t. ms. Of course the short crcut fault curret does appear the dfferetal currets of Fgure 5.. The tme tegrals of the dfferetal fault currets are also show Fgure 5.. Because the fault curret magtudes of dcdff dffer the tme tegrals reach the trp level at dfferet tme stats. Cosequetly cable ode s aware of the fault pror to cable ode. However cable ode wats utl cable ode acowledges the fault stuato before the crcut breaers are operated. Lmtatos Note that for large DC dstrbuto systems.e. wth a hgh umber of cable odes the groud curret dcdff mght be below the offset level of the trasducer. Ths meas that the fault s ot accurately detected. To crcumvet ths problem the dfferetal currets dcdffa ad dcdffb accordg to dcdffa dcdffb dcap dcbp + + dca dcb (5.74)

110 Chapter 5. Fault detecto ad clearace could be measured stead. The measuremet s made dfferetal.e. the curret trasducers are coected to measure the curret sum drectly a smlar way as for the scheme show Fgure 5.7. Ths method also suffers from a problem although less severe. Cosder a case where the rg bus structure s ot used or have bee broe due to a prevous fault ad a secod fault occurs at the last segmet of the bus. The dfferetal curret dcdffa or dcdffb flowg from the ed of the bus could be lower tha the offset level the case of hgh mpedace faults for a large dstrbuto system. Fgure 5.3 shows the dfferetal currets dcdffa ad dcdffb for the same smulato as show Fgure 5.. dcdffa dcdffb [A] t [ms] Fgure 5.3: Fault currets dcdffa (sold) ad dcdffb (dashed) for coverter (blac) ad coverter (grey) the case of a groud fault o the DC sde (postve supply ral-to-groud) betwee coverter ad at t. ms. The fault resstace R Fault s equal to. Ω. Note that the rg bus s broe betwee coverters 4 ad 5 due to a prevous fault. The rato betwee the trp curret levels of the scheme where dcdffa ad dcdffb are used compared to the scheme where dcdff ad dcdff are used s gve by I Trp rato (5.75) (.5) where s the umber of cable odes o the sde wth the lowest umber of cable odes at the fault locato. For a ubroe rg bus (5.76) eve f the total umber of cable odes s odd. I the smulato where dcdffa ad dcdffb are used for a fve-coverter system ths meas that the equvalet trp curret level compared to (5.45) s equal to a trp curret rato of /3.e.

111 5.4 Smulatos 3 I C 3 trp p V dc (5.77) For a very hgh umber of cable odes (5.75) approaches.5. Ths meas that a sutable trp lmt for ths scheme s gve by I C 4 trp p V dc (5.78) whch yelds at least the same performace terms of detecto tme as the scheme where dcdff ad dcdff are used.

112

113 Chapter 6 DC trasmsso I the same maer as for preset AC power trasmsso systems DC power trasmsso should be operated at hgh voltage levels order to reduce ohmc losses ad ths s doe for example HVDC. Galvac separato s requred for large DC dstrbuto systems to crcumvet the rs of elevated voltage levels occurrg the low voltage parts of a DC dstrbuto system the case of a groud fault located hgh voltage parts. Also some of the fault detecto methods are oly applcable for a low umber of cable odes due to the relatvely low dfferece betwee comg ad outgog fault curret the case of a large umber of cable odes whch s explaed Chapter 5. I ths chapter two dfferet schemes for DC power trasmsso betwee two DC dstrbuto systems are vestgated. Oe of the schemes s smlar to VSC based HVDC ad the other s based o the double actve brdge (DAB) coverter troduced [8]. The schemes are referred to as the bac-to-bac ad DAB structures respectvely. 6. The bac-to-bac structure The crcut schematc ad cotrol for the bac-to-bac trasmsso structure are dscussed ths secto. Also smulato results for a system of low complexty are show. Crcut schematc The bac-to-bac structure s based o techology smlar to VSC based HVDC. I ths techology the low voltage sdes are equpped wth ductve flters whereas the put flter to the DC bus should be capactve. VSC based 5

114 6 Chapter 6. DC trasmsso HVDC s teded for a AC low voltage sde whereas a DC sde s cosdered here. Eve f bdrectoal power flow s requred sgle halfbrdge trasstor coverters could be used as terface betwee the dfferet voltage levels. However ths could cause eutral curret problems sce oe termal of each DC system coected va the trasmsso bus s commo. Sce the DC-DC full-brdge coverter Fgure 6. ca be cotrolled to have a output prcple free of commo mode compoets t s preferred. L f L f C LV C HV C HV C LV v LV v HV v HV v LV L f L f Fgure 6.: The vestgated bac-to-bac coverter structure teded for DC trasmsso. Cotrol The DC-DC coverters ths scheme are equpped wth basc curret cotrollers smlar to the three-phase curret cotrollers derved Appedx B. Bdrectoal DC bus voltage cotrollers are mplemeted o top. The power flow drecto ca be set two dfferet ways. Oe way s to set the drecto so that oly oe drecto s allowed. The other way whch s mplemeted here s by specfyg the mmum (egatve) ad maxmum (postve) power trasfer lmts. Note that ether of these two could be set to zero to force a udrectoal power flow. For ormal operato the power drecto s set to flow from the hgher (relatve to the referece) to the lower (relatve to the referece) voltage level. As show Chapter 3 a voltage overshoot mght occur whe the source output power chages depedg o the cable parameters. Ths mples that for trasets the sedg ed voltage mght become lower tha the recevg ed voltage. Ths would cause a chage of referece power drecto f o precautos are tae. Also for statoary operato there mght be problems due to the resstve voltage drop of the coverter stage. To crcumvet ths a hysteress cotroller wth deadbad s employed the referece drecto algorthm. The wdth of the deadbad s proportoal to the actual curret flowg the trasmsso bus. The low-pass fltered dfferece p.u. DC bus voltage for the two sdes s compared to a dead-bad wth lmts specfed from v R (6.) dc lmt eq dc

115 - 6. The bac-to-bac structure 7 I ths case the equvalet resstace R eq s gve by the voltage drop of the coverter ad the resstace of the flter ductors ad cosdered as low. For the bac-to-bac scheme ths s ot mportat but for the DAB scheme t s of great mportace due to the trasformer serted betwee the coverter stages. Fgure 6. shows the algorthm for determg power flow drecto. Power flow drecto -to- v dc -to- Fgure 6.: Dead-bad for determato of power flow drecto. Whe the power flow drecto s determed the regular droop referece curret s calculated the same way as Chapter 3. Note that the same type of coverter could be used whe DC electrc eergy storage elemets such as batteres or fuel cells are employed. Smulato Fgure 6.3 shows a smplfed schematc of the smulated trasmsso system. The trasmsso bus has a rated power of W whch yelds DC bus capactors equal to mf for the 75 V sdes ad.3 mf for the 6 V sde accordg to (3.). The flter ductors o each low voltage sde have a total ductace of mh ad a total seres resstace of 5 mω. p p p 3 p 4 + v v v HV v - HV v v Fgure 6.3: Bac-to-bac trasmsso system vestgated smulatos. The smulato results for the bac-to-bac trasmsso system of Fgure 6.3 are show Fgure 6.4 Fgure 6.5 ad Fgure 6.6. All power refereces are postve from left to rght (Fgure 6.3). Sold les are used for DC-DC coverter quattes. For the leftmost AC-DC ad DC-DC coverters (dex ad ) the curves are blac ad for the rghtmost AC-DC ad DC-DC coverters (dex 3 ad 4) the curves are grey. The quattes represetg ut ad 3 are sold ad for ut ad 4 they are dashed.

116 8 Chapter 6. DC trasmsso Fgure 6.4 shows smulated low sde voltage ad power the case of bac-tobac trasmsso. 8 v v v 3 v 4 [V] p p p 3 p 4 [W] Fgure 6.4: t [ms] Smulated voltage (top) ad power (bottom). Due to the hgh curret rpple the ductors the estmated power Fgure 6.4 also has a hgh cotet of swtchg frequecy related harmocs. The varato the rpple of estmated power p 3 s due to ductor curret samplg dstorto causg a dstorto the coverter voltage referece for the low voltage sde of ut 3. The oly dfferece betwee the bac-to-bac coverters ut ad 3 are the samplg ad swtchg frequeces. For ut f s 5 Hz ad f sw 7.5 Hz. For ut 3 f s Hz ad f sw 5 Hz. Cosequetly the bac-to-bac trasmsso scheme s sestve to cotroller parameters. The low-pass fltered estmated power s show Fgure 6.5. p p p 3 p 4 [W] Fgure 6.5: t [ms] Smulated power (low-pass fltered).

117 6. The bac-to-bac structure 9 Fgure 6.6 shows the smulated hgh sde voltage. The voltage drop alog the trasmsso cable s low so the voltages are o top of each other Fgure v HV v HV [V] Fgure 6.6: t [ms] Smulated hgh sde voltage. 6. The DAB structure I ths secto the schematc ad cotrol of the DAB trasmsso system are dscussed. Smulato results for a mmal system are show the same way as for the prevously vestgated bac-to-bac system. Crcut schematc The DAB coverter cossts of two DC-DC full-brdge coverters coected frot-to-frot wth a trasformer coected betwee (Fgure 6.7). T v C dc v T v T C dc v Fgure 6.7: The vestgated DAB structure teded for coecto of two DC rg buses wth galvac separato. The DAB coverter provdes bdrectoal power flow ad also galvac separato due to the trasformer. The DAB coverter s ofte desged to operate at hgh frequeces ad some cases also for resoat operato [69]. I ths chapter the am s to show that the DAB coverter ca be operated for trasmsso wth the proposed voltage cotrol algorthms. Therefore hgh frequecy ad resoat operato are ot cosdered.

118 Chapter 6. DC trasmsso To coect two DC power systems wth galvac solato oly oe DAB coverter s eeded. To coect two such systems wth a hgh voltage DC trasmsso system two DAB coverters.e. four full-brdge coverters ad two trasformers are requred (Fgure 6.8). v LV C LV L L C HV v HV v HV C HV L L C LV v LV Fgure 6.8: The vestgated DC trasmsso structure utlsg DAB coverters. Both the DC rg bus sde ad trasmsso sde of each DAB are truly capactve. Cotrol For a DAB both coverters are operated wth the same cotroller. Ths meas that the recevg ed coverter s ot smply operated as a ucotrolled dode rectfer. Istead the curret cotroller calculates a approprate phase lag betwee the gate sgals of the two coverters. The trasstors of each coverter are operated pars so that the lower or upper trasstors of oe of the coverters of the DAB are ot coductg smultaeously. I statoary codtos the gate pulses of the recevg ed lag the oes of the sedg ed coverter. The tme lag s used as cotrol parameter the smulatos show later ths chapter. The deal waveforms for the DAB coverter gve [8] are show Fgure 6.9 wth referece to Fgure 6.7 to vsualse the basc operato of the coverter. To cotrol the DAB coverter DC trasmsso a cotroller structure smlar to the oe used for three-phase coverters accordg to Appedx B s employed. Smlar to the cotroller foud [8] the relatve delay s used as cotrol varable stead of coverter output voltage. The relatve delay (wth respect to the samplg tme terval T s ) s calculated from K p d ( ) + ( ) + K + ( v v ) ref lp T ref v lp r lp (6.) where lp s a low-pass fltered verso of the curret T Fgure 6.7. The brea-over frequecy of the low-pass flter s 5 Hz.

119 6. The DAB structure The cotroller parameters are K p L Ts.5L T T K ptsr L Kr R s (6.3) where L s the total stray ad leaage ductace ad R s the total resstace referred to the prmary. Note that a postve delay d mples that the prmary sde trasstors should be trgged a tme d T s before the correspodg trasstors of the secodary sde. Cosequetly a egatve delay d mples that the secodary sde trasstors should be trgged a tme -d T s before the trasstors of the prmary sde. v T v -v v T v t t -v T d t t t Fgure 6.9: Ideal waveforms for the vestgated DAB structure teded for coecto of two DC rg buses.

120 - Chapter 6. DC trasmsso The dead-bad s calculated the same way as for the bac-to-bac couterpart.e. v dc lmt R dc (6.4) The dead-bad s of great mportace for ths scheme due to the resstve ad ductve voltage drop across the trasformer especally durg trasets. Smulato of DAB for HVDC trasmsso Fgure 6. shows the smplfed schematc of the smulated HVDC DAB system whch ths schematc form s equal to the bac-to-bac test system. p p p 3 p 4 + v v v HV v - HV v v Fgure 6.: DAB trasmsso system vestgated smulatos. The smulato result for the DAB trasmsso system of Fgure 6. s show ths secto. All power refereces are postve from left to rght see Fgure 6.. The data for the DAB coverters are gve Table 6.. The trasformer short crcut resstace R sc ad self-ductace L s are gve for both the prmary ad secodary. The magetc couplg factor s assumed to be.99 see Table 6.. The DC bus capactace s gve both for the low ad hgh voltage sdes. The cable data s the same as Chapter 3 ad Chapter 4. Table 6.: Smulato model data. DAB o. Rated power P [W].. Swtchg frequecy f sw [Hz] Trasformer resstace R sc [Ω]./ /. Trasformer self-ductace L s [mh] 5/3 3/5 Magetc couplg factor DC bus capactace C dc [mf]./.3.3/. Cable capactace C cable [F] Cable ductace L cable [µh] Cable resstace R cable [mω] DC bus voltage referece (LV) V dcreflv [V] DC bus voltage referece (HV) V dcrefhv [V] 6 6

121 6. The DAB structure 3 Fgure 6. shows smulated voltage ad power for the system the case of a step the output power of the load coverter equal to 5 W at t ms. For the leftmost AC-DC ad DC-DC coverters (dex ad ) the curves are blac ad for the rghtmost AC-DC ad DC-DC coverters (dex 3 ad 4) the curves for each quatty are grey. The quattes represetg ut ad 3 are sold ad for ut ad 4 they are dashed. 8 v v v 3 v 4 [V] p p p 3 p 4 [W] t [ms] Fgure 6.: Smulated low sde voltage (top) ad power (bottom). Fgure 6. shows the low-pass fltered power to be compared wth the correspodg smulato result for the bac-to-bac structure vestgated the prevous secto. The hgh sde voltage the case of DAB trasmsso s show Fgure 6.3. Note that the two voltages show Fgure 6.3 are o top of each other. p p p 3 p 4 [W] t [ms] Fgure 6.: Low-pass fltered smulated power.

122 4 Chapter 6. DC trasmsso 6 v HV v HV [V] t [ms] Fgure 6.3: Smulated hgh sde voltage. 6.3 Proposed tercoecto structure The DAB trasmsso structure s selected for the further aalyss. Ths s due to several reasos. The galvac solato of the DAB s a desrable property sce fault currets should ot propagate through the etre DC dstrbuto system. The DAB structure also provdes a truly capactve terface to the DC bus so that the coverter put ad output mpedaces p.u. are the same for all coverters. The curret rpple s lower tha that of the bac-to-bac structure. Also the thermal desg of the flter ductor could be cumbersome for the bac-to-bac scheme. The DAB structure s also sutable for hgh frequecy ad resoat mplemetato [69]. Smulato of a DAB trasmsso system coectg two DC rg buses Here a system wth two rg buses ad a termedate DAB trasmsso bus s vestgated see Fgure 6.4. Note that a realstc applcato the trasmsso system could be radal ad cosst of more tha two coverters. p p p + v v + - p 5 p 6 v v p 9 p 3 + v v HV v HV - + v 6 p 8 + v 3 v p 4 p 7 + v 7 v Fgure 6.4: Two rg bus DAB trasmsso system vestgated smulatos.

123 6.3 Proposed tercoecto structure 5 Each rg cossts of four grd coected coverters (ot cludg the DAB low voltage coverter) wth data accordg to Table 6.. The DAB coverter data are foud Table 6.. Table 6.: Smulato model data. Coverter o Rated power S [VA]. 5. Le-to-eutral voltage E LN [V] 3 3 Le frequecy f [Hz] 5 5 Swtchg frequecy f sw [Hz] Le ductace L le [mh] Le resstace R le [Ω].5.5 DC bus capactace C dc [mf].. Cable capactace C cable [F] Cable ductace L cable [µh] Cable resstace R cable [mω] DC bus voltage referece V dcref [V] The system s smulated startg from a o-load codto. The power refereces for uts ad 3 are chaged stepwse by. p.u. (ut base) at tme equal to ad ms respectvely. The power refereces for uts 7 ad 8 are chaged stepwse by. p.u. (ut base) at tme equal to ad ms respectvely. The magtudes of the power referece steps are selected such a way sce t s desred to force a chage the drecto of the power flow of the trasmsso bus. The smulato results are show Fgure 6.5 ad Fgure 6.6 where the quattes for ut ad 6 are sold blac ad 7 are sold grey 3 ad 8 are dashed blac 4 ad 9 are dashed grey ad 5 ad are dash-dotted blac. The smulated voltage ad power for the trasmsso bus are show Fgure 6.7. Note that the smulated power s low-pass fltered Fgure 6.7 but ot Fgure 6.5 ad Fgure 6.6. As see the smulato result the DAB trasmsso system operates as teded. The power flowg through the trasmsso bus chages drecto shortly after t ms due to the appled load as teded. Note the oscllatos the rg ad trasmsso bus voltages. Due to the hysteress the algorthm for determg the drecto of power flow t does ot chage the smulato.

124 6 Chapter 6. DC trasmsso The trasmsso bus voltage cotroller preseted here strves to share the total load democratc. To actually cotrol the power flow exteral refereces should be set. Ths mples that supervsory cotrol ad motorg are eeded. 76 v v v 3 v 4 v 5 [V] p p p 3 p 4 p 5 [W] t [ms] Fgure 6.5: Smulated rg bus voltage (top) ad power (bottom). v 6 v 7 v 8 v 9 v [V] p 6 p 7 p 8 p 9 p [W] t [ms] Fgure 6.6: Smulated rg bus voltage (top) ad power (bottom).

125 6.3 Proposed tercoecto structure 7 6 v HV v HV [V] p 5 p 6 [W] t [ms] Fgure 6.7: Top: Smulated DAB trasmsso bus voltages v HV (blac) ad v HV (grey). Bottom: Smulated low-pass fltered power of the DAB trasmsso p 5 (blac) ad p 6 (grey).

126

127 Chapter 7 Measuremets I ths chapter a small expermetal DC dstrbuted power system s mplemeted based o the results of Chapter 3 ad Chapter 5. Parts of the aalyss these chapters are verfed measuremets. The expermets focus o dyamc propertes of a two-coverter system ad load sharg for a threecoverter system. Measuremet result of fault currets the case of a hgh mpedace fault for the three-coverter system s also show. 7. Expermetal set-up The expermetal set-up s formed by three-phase coverters coected to a 3 V 5 Hz three-phase grd. As dscussed the prevous chapters the coverters are galvacally separated o the AC le sdes ad therefore each coverter s coected to the commo three-phase grd through trasformers. The trasformers are coected YNy wth a voltage rato of 3/45. The eutral o the le sde s used oly for measurg the le voltage requred for the curret cotroller (Appedx B). The reaso for selectg such a low coverter sde voltage s that the maxmum allowed DC bus voltage of the coverters s equal to 3 V. Wth the same V dcref /E LL rato as prevous chapters the DC bus voltage equals 7 V for a coverter sde le-to-le voltage of 45 V. The data of the trasformers are ufortuately ot fully ow. To avod over-modulato (Appedx A) due to a trasformer mpedace hgher tha expected the rated droop s reduced to half compared to the prevous chapters.e. the rated droop s set to δ.5. Ths correspods to reducg the dampg to ζ.5. Ths gves the followg specfcato of the voltage cotrollers 9

128 Chapter 7. Measuremets V dc ref 7 V ωlp 3 rad/s 88 rad/s ζ δ.5 (7.) Accordg to (3.) the correspodg DC sde capactace to rated power rato s gve by C dc coverter P coverter 536 F/W (7.) The DC bus voltage cotroller ga for each source coverter s thus gve by K ω lp C dc coverter (7.3) The R- ad S-phase currets flowg out from each coverter are measured together wth the DC bus voltage at each coverter-to-dc bus terface. The coverters are mouted racs wth two coverters each rac. Sce oly two AC voltage measuremet trasducer cards (gvg voltage vectors the statoary αβ-frame) are avalable both coverters of each rac must utlse the same voltage measuremet to create the referece for the rotatg dqframe. Ths measuremet s made o the le sde of the trasformers to avod the voltage drop of the trasformer short crcut mpedace. Le sde flter ductors of 3 mh each are serted betwee each coverter ad trasformer. The short crcut ductace of the trasformer s estmated to 8 mh. The resstaces of the flter ductors ad trasformers are estmated to.5 ad.5 Ω per phase respectvely. The trasformer stray ductace s ot verfed. The trasformer short crcut resstace seems to be hgher tha frst estmated approxmately equal to.9+.4 Ω from a DC measuremet. The data used for the expermetal set-up ad smulato model are lsted Table 7.. I Table 7. both model ad cotroller parameters are gve. The parameters used the cotroller should be equal both smulato ad expermetal set-up. For the expermetal set-up the estmated parameters ad the oes the cotrollers are based o are equal whch s also atural. However as metoed above the parameters are measured more thoroughly after the expermet ad some devatos foud e.g. the short crcut resstace.

129 - 7. Expermetal set-up Table 7.: Measuremet ad smulato model data. System data Measuremet Smulato Estmated Cotroller Estmated Cotroller Le-to-eutral voltage E LN [V] Le frequecy f [Hz] Swtchg frequecy f sw [Hz] Le ductace L le [mh].... Le resstace R le [mω] DC bus voltage referece V dcref [V] Accordg to Table 7. the swtchg frequecy (f sw ) s somewhat lower tha the oe used the vestgatos the prevous chapters. The swtchg frequecy of the laboratory set-up s set by the cotroller hardware. However ths s ot crtcal sce the swtchg frequecy s stll cosderably hgher tha the DC bus voltage cotroller badwdth. All the cotroller algorthms eeded for each coverter are mplemeted IEA-MIMO cotrol computers [9]. The IEA-MIMO s based o the Texas Istrumets TMS3C3 floatg-pot dgtal sgal processor (DSP). Oe of the ey beefts of the IEA-MIMO s the smultaeous samplg of 6 aalogue put chaels wth bts resoluto. Furthermore t provdes 8 aalogue output chaels. The quattes show the fgures ths chapter are actually measured from these output chaels. A Tetrox TDS 64A osclloscope s used for all the measuremets. The IEA-MIMO s also equpped wth a DSPLINK bus for expaso boards e.g. the PWM board. Tragular carrer wave modulato (Appedx A) s carred out o the PWM board. The samplg stats of the IEA-MIMO are sychrosed to the postve ad egatve peas of the carrer va the DSPLINK bus. Cosequetly the samplg frequecy equals twce the swtchg frequecy. 7. Dyamc propertes The dyamc propertes are vestgated the same way as Chapter 3. A smplfed schematc of the expermetal set-up s show Fgure 7.. p s R dc p r + v s L dc + v r - Fgure 7.: Expermetal set-up for vestgato of dyamc propertes.

130 Chapter 7. Measuremets Both coverters are equpped wth DC bus capactors wth a total omal capactace of. mf each whch s used for calculato of the voltage droop ga. Ths gves a rated power for the coverters equal to 76 W. The rated power wth respect to the semcoductor devces the coverter s cosderably hgher. As dscussed Chapter 3 the rated power of the coverter s determed by the DC bus capactor ad rated voltage. Of course the semcoductors of the coverter are selected accordace wth rated power ad DC bus voltage a practcal applcato. Sce the dampg s reduced for the expermetal set-up compared to the aalyss of Chapter 3 the measuremets are asssted wth smulatos. Ideally the smulato model should agree wth the expermetal set-up. Therefore the DC bus capactaces are measured for the smulatos. The measuremet dcates that the source DC bus capactace s.8 mf ad the load coverter DC bus capactace s.3 mf. The cotrollers used the smulato are however stll based o a coverter DC bus capactace of. mf each. The expermets o dyamc performace are coducted wth a DC bus seres resstor R dc Fgure 7. of ether. Ω or 6. Ω together wth a seres ductor L dc of.3 3. or 3 mh. The vestgated combatos of parameters are lsted Table 7.. As show Table 7. the total seres resstace s slghtly hgher due to the ductor wdg resstace. Ths s accouted for the smulato model. Table 7.: Measuremet ad smulato model data. Measuremet o. Measuremet parameters R dc [Ω] L dc [mh] Smulato parameters R dc [Ω] L dc [mh] The vestgatos o dyamc performace ths secto are carred out for a step the output power referece of the load coverter correspodg to omal power.e. 76 W. The root-locus (wth referece to Chapter 3) for R dc. Ω are show Fgure 7. ad Fgure 7.3. The cases actually vestgated.e. L dc.3 3. ad 3 mh are show wth large margs. The other two cases lsted Table 7. are ot cluded the root-locus sce two

131 7. Dyamc propertes 3 poles are real. Oe of the real valued poles s located at a very hgh frequecy (close to a zero) ad therefore the vsblty of the root-locus s lost f these cases are cluded. Note that there s oly a mor dfferece the root-locus at o-load ad rated load. 5 L dc.3 mh Imag Axs 5 L dc 3 mh 5 5 Real Axs Fgure 7.: Root-locus of pole ρ. The dfferece betwee rated load ad o-load s ot vsble ths scale. Imag Axs Fgure 7.3: L dc.3 mh Real Axs L dc 3 mh Root-locus of pole ρ 3 at rated load (blac) ad o-load (grey). Expermetal ad smulato results The measured ad smulated voltage ad power for the sedg ad recevg ed coverters are show Fgure 7.4 (R dc. Ω ad L dc mh) Fgure 7.5 (R dc. Ω ad L dc.3 mh) Fgure 7.6 (R dc. Ω ad L dc 3. mh) Fgure 7.7 (R dc. Ω ad L dc 3 mh) ad Fgure 7.9 (R dc 6. Ω ad L dc 3 mh). Fgure 7.8 shows a te-ru average measuremet wth the same parameters as for Fgure 7.7. I Fgure 7.4 Fgure 7.5 ad Fgure 7.6 (case -3) there s a good agreemet betwee measuremet ad smulato results. However Fgure 7.7 Fgure 7.8 ad Fgure 7.9 (case 4-5) agreemet seems to be poor.

132 4 Chapter 7. Measuremets 8 7 v s v r [V] p s p r [W] Fgure 7.4: 8 7 t [ms] t [ms] Measured (left) ad smulated (rght) sedg ed (blac) ad recevg ed (grey) voltage (top) ad power (bottom) the case of R dc. Ω ad L dc mh (L dc. H for the smulato model). v s v r [V] p s p r [W] Fgure 7.5: t [ms] t [ms] Measured (left) ad smulated (rght) sedg ed (blac) ad recevg ed (grey) voltage (top) ad power (bottom) the case of R dc. Ω ad L dc.3 mh.

133 7. Dyamc propertes v s v r [V] p s p r [W] Fgure 7.6: 8 7 t [ms] t [ms] Measured (left) ad smulated (rght) sedg ed (blac) ad recevg ed (grey) voltage (top) ad power (bottom) the case of R dc. Ω ad L dc 3. mh. v s v r [V] p s p r [W] Fgure 7.7: t [ms] t [ms] Measured (left) ad smulated (rght) sedg ed (blac) ad recevg ed (grey) voltage (top) ad power (bottom) the case of R dc. Ω ad L dc 3 mh.

134 6 Chapter 7. Measuremets 8 7 v s v r [V] Fgure 7.8: p s p r [W] t [ms] Te-ru average measuremet of sedg ed (blac) ad recevg ed (grey) voltage (top) ad power (bottom) for R dc. Ω ad L dc 3 mh. 8 7 v s v r [V] p s p r [W] Fgure 7.9: t [ms] t [ms] Measured (left) ad smulated (rght) sedg ed (blac) ad recevg ed (grey) voltage (top) ad power (bottom) the case of R dc 6. Ω ad L dc 3 mh.

135 7. Dyamc propertes 7 Commets Due to the poor agreemet betwee smulato ad measuremet for case 4 (R dc. Ω ad L dc 3 mh) t s vestgated further. Sce the DC bus voltage cotrollers are mplemeted the same way both smulatos ad expermets t s cocluded less lely that the problem orgate from the DC bus voltage cotroller. Therefore the emphass of the vestgato s put o the AC sde ad ts curret cotroller. The ma reaso s that t seems le the estmated AC sde power appears to have a hgher overshoot the measuremets tha the smulatos. Ths mples that the traset DC bus voltage s lower the measuremets tha the smulatos. The reasos for the devatos betwee measuremet ad smulato results are vestgated the followg. The q-drecto curret referece s calculated from pref q ref (7.4) e where p ref s the power referece ad e qf s the low-pass fltered grd voltage vector. The frst order low-pass flter wth brea-over frequecy of 5 Hz s used to atteuate dsturbaces sce t s foud that they affect the referece to a large extet. The estmated power however s ot used for cotrol purposes ad dsturbaces are ot cosdered as a problem. Therefore t s calculated from est q f p e (7.5) The problem s that the le mpedace s ot modeled the smulato but always preset a expermetal set-up. Cosequetly e q s ot costat the measuremets as the smulatos. Whe the output power from the load coverter creases e q also creases whle e qf remas ualtered tally. Thus qref s ualtered causg the overshoot the estmated power. The expermetal set-up s coected to a AC power outlet equpped wth A fuses. Cosequetly t s lely that the short crcut mpedace of the grd s rather hgh. Therefore a short crcut mpedace of Z sc.5+j.5 Ω s used for the followg smulatos. Moreover the power coverters are coected to the same outlet va the threephase trasformers. Whe the load coverter respods to the step ts power referece t delvers power to the grd. Ths meas that whe the source coverter starts to draw power from the same three-phase grd the loadg of q q

136 8 Chapter 7. Measuremets the outlet s lower tha expected. However durg the voltage trasets the short crcut mpedace of the outlet s mportat. The smulato model used prevously Chapter 3 ad ths secto s altered to comply more wth the expermetal set-up see Fgure 7.. R les L les Cdcs vs Y Y L dc 3 V 5 Hz Z sc R dc R ler Y Y L ler Cdcr vr Fgure 7.: Smulato model for vestgato of dyamc propertes. Ths model comples more wth the expermetal set-up tha the prevously used. Two smulatos are repeated wth ths le mpedace appled to the model Fgure 7.. I Fgure 7. the smulato result wth R dc. Ω ad L dc 3. mh s show. The measuremet ad smulato results for ths case show a good agreemet already Fgure 7.6. The reaso for repeatg the smulato wth the altered model s to verfy that t covers all cases ad ot just the oes wth L dc 3 mh. It s clearly see that the result correspods well wth the measured result of Fgure 7.6. Due to the good agreemet betwee measuremet ad smulato also for the altered model ths case the other smulatos that already show a hgh degree of agreemet s ot repeated. Fgure 7. shows the smulato result for the case wth R dc. Ω ad L dc 3 mh. The smulato result Fgure 7. shows better agreemet wth the measured result Fgure 7.7 compared to the smulato result of Fgure 7.7. Stll the rgg followg the voltage overshoot the smulato s ot apparet the measuremet. Ths s most lely due to the fact that the short crcut mpedace Z sc of the three-phase outlet s ot accurately estmated ad that the dstrbuted mpedace the coverter s ot modeled but preset the expermetal set-up.

137 7. Dyamc propertes v s v r [V] p s p r [W] t [ms] Fgure 7.: Smulated sedg ed (blac) ad recevg ed (grey) voltage (top) ad power (bottom) the case of R dc. Ω L dc 3. mh ad le mpedace equal to Z sc.5 + j.5 Ω per phase. 8 7 v s v r [V] p s p r [W] t [ms] Fgure 7.: Smulated sedg ed (blac) ad recevg ed (grey) voltage (top) ad power (bottom) the case of R dc. Ω L dc 3 mh ad le mpedace equal to Z sc.5 + j.5 Ω per phase.

138 3 Chapter 7. Measuremets 7.3 Load sharg To vestgate load sharg a DC rg bus wth three coverters s studed. The system s show Fgure 7.3. v + - p v + - p v p 3 Fgure 7.3: Expermetal set-up for vestgato of load sharg. Two of the coverters ut ad ut 3 are operated as sources. Ut s operated as load. Addtoal DC bus capactors are coected at the coverters to crease the rated power. Thus the coverters are equpped wth DC bus capactors of.6 mf (ut 4 W). mf (ut 367 W) ad. mf (ut 3 76 W). Sce the ga s calculated based o the DC bus capactace of the sources the total DC bus capactace s overestmated to (.6+.) mf5.4 mf whereas the actual total DC bus capactace s 4.8 mf. However ths s ot adjusted for sce ths s regarded possble also for real stallatos. Each coverter s coected to the DC rg bus through a cable ode wth two µf groudg capactors (Fgure 5.) wth Ω bleeder resstors coected parallel. Resstors of Ω are coected seres wth each groudg capactor to obta a mmum tme costat of ms for the fault currets as descrbed Chapter 5. Curret trasducers are ot mouted. Istead curret probes are used for measurg the dfferetal fault currets. Each cable segmet s modeled by four. Ω resstors (Fgure 5.) to troduce a fault o the mddle. Note that all the measuremets ths secto are averaged from te separate measuremets due to the hgh level of measuremet ose. Accordg to the measured traset respose show Fgure 7.7 ad Fgure 7.8 of the prevous secto the te-ru average measuremet gves a result cosstet wth a sgle measuremet. Therefore t s cocluded that te-ru average measuremets ca be used also whe load sharg s vestgated sce the etwor s more deal ths case ad cosequetly the dyamcs are less proouced.

139 7.3 Load sharg 3 Ths secto s arraged as follows. Frst load sharg s examed for a system where the DC bus voltage measuremets of the sources are offset-adjusted such a way that they are loaded proportoally equal. Measuremets are made for both a ubroe ad broe DC rg bus. The result of a hgh mpedace DC bus groud fault s also examed. Secod load sharg wthout offset-adjusted DC bus voltage measuremets are vestgated. The power referece for the load coverter (ut ) s chaged steps all the expermets o load sharg. The magtude of the step correspods to approxmately 85 W. Load sharg for offset-adjusted DC bus voltage measuremets I the frst expermet o load sharg the DC bus voltage measuremet of ut 3 s adjusted by subtracto of 3.7 V the cotroller to gve the same level as for ut at o-load codtos. Fgure 7.4 shows the voltage ad power for the three uts. Both source coverters are loaded to approxmately.6 p.u. (ut base) ad hece the total load s shared democratc. Note that the load ut has o offset-adjustmet of the DC bus voltage measuremet (Fgure 7.4) whch s also the case the prevous secto. 8 v v v 3 [V] p p p 3 [W] t [ms] t [ms] Fgure 7.4: Measured (left) ad smulated (rght) ut (blac) ut (grey) ad ut 3 (lght-grey) DC bus voltage (top) ad power (bottom) the case of offsetadjusted DC bus voltage measuremets for the source coverters.

140 3 Chapter 7. Measuremets Hgh mpedace DC bus groud fault The dfferetal fault currets the case of a. Ω DC bus groud fault betwee ut ad of the three-coverter system are vestgated. Curret probes wth a trasfer rato of mv/a are used for the dfferetal curret measuremets. The measuremet ose due to swtchg has a hgher magtude tha the fault currets ths case. Therefore the fault currets are measured for a case where the coverters are ot operated. Cosequetly the DC bus voltage equals the pea AC le-to-le voltage.e. 5 V. The dfferetal curret measuremets are show Fgure 7.5. Dfferetal fault currets [ma] dcdff dcdff t [ms] dcdff dcdff t [ms] Fgure 7.5: Measured ut dfferetal curret dcdff (top left) ut dfferetal curret dcdff (top rght) ut dfferetal curret dcdff (bottom left) ad ut 3 dfferetal curret dcdff (bottom rght). The pea fault curret at the fault locato should equal 5 ma whch meas that the pea dfferetal fault curret dcdff equals 68 ma for uts ad accordg to (5.46). The pea value of the dfferetal fault curret dcdff equals 34 ma accordg to (5.6). The levels of the fault currets are thus agreemet of the results of Chapter 5. Sce dcdff s egatve the fault s located betwee the postve DC bus coductor ad groud. The sg combatos of dcdff ad dcdff for uts ad reveal that the fault s located betwee these uts. For ut 3 dcdff s essetally uaffected by the fault sce the commo mode curret flows to both cable segmets for ths cable ode.

141 7.3 Load sharg 33 Note that the swtchg ose problem dscussed earler ths secto dcates that the trasducers for the dfferetal curret measuremet should have a hgher trasfer rato for example V/A to accurately detect hgh mpedace groud faults. They should also be saturable to avod excessve voltages for low mpedace faults. Load sharg for broe DC bus I the ext expermet load sharg the case of a broe DC rg bus for example followg a fault s vestgated. Fgure 7.6 shows the measured DC bus voltage ad estmated power the case that the rg bus s broe betwee coverters ad. Load sharg s oly slghtly degraded compared to the case wth a ubroe DC bus. Ths s due to the low equvalet cable resstace compared to the equvalet resstace of the droop cotrollers R droop. 8 v v v 3 [V] p p p 3 [W] t [ms] t [ms] Fgure 7.6: Measured (left) ad smulated (rght) ut (blac) ut (grey) ad ut 3 (lght-grey) DC bus voltage (top) ad power (bottom) the case of a DC bus broe betwee uts ad. Load sharg for o-offset-adjusted bus voltage measuremets I the last expermet o load sharg the performace s vestgated for a case where the DC bus voltage measuremet of ut 3 s ot offset-adjusted. As see Fgure 7.7 ut delvers power to the DC bus ad ut 3 draws power from the DC bus whe ut operates at o-load.

142 34 Chapter 7. Measuremets 8 v v v 3 [V] p p p 3 [W] t [ms] Fgure 7.7: Measured ut (blac) ut (grey) ad ut 3 (lght-grey) DC bus voltage (top) ad power (bottom) the case of o-offset-adjusted DC bus voltage measuremets for the source coverters. Fgure 7.7 clearly demostrates that oe of the ey problems of coverter desg s that the DC bus voltage measuremet must be accurate to yeld proper load sharg. O the other had t also dcates that DC bus voltage offset cotrol le the oe used the wd power applcato of Chapter 4 s possble.

143 Chapter 8 Coclusos Ths thess presets a possble soluto for corporato of reewable eergy sources the power system. Here local DC dstrbuto systems are proposed whch mght also provde heret UPS propertes f eergy storage elemets or local geeratg uts are employed. A DC dstrbuto system smlar to the oe used for reewable eergy systems preseted here ca also be used for example for telecommucato systems ad dustral multcoverter systems for drves. Moreover DC dstrbuto systems could also be mplemeted for propulso ad tracto applcatos. Frst a summary of the obtaed results s gve. Secod some future research topcs for DC dstrbuted power systems are provded. 8. Summary of results The vestgato o DC dstrbuted power systems has provded results summarsed ths secto. Voltage cotrol ad load sharg Several dfferet methods to acheve voltage cotrol ad load sharg are vestgated. The DC bus voltage droop cotrollers employed do ot heretly requre commucato betwee source ad load coverters to acheve voltage cotrol ad load sharg. Therefore the droop method s selected for the further vestgatos. However applcatos where the avalable power could be lower tha the requested some d of supervsory cotrol or motorg acto s eeded to gve prortes for load sheddg schedules whe requred. 35

144 36 Chapter 8. Coclusos The statoary ad dyamc propertes of a two-coverter system are vestgated. Oe of the coverters s operated as a costat power load ad the other as a source utlsg DC bus voltage droop cotrol. The aalyss provdes a method to select DC bus capactace of each coverter coected to the power system. Ths DC bus capactace s selected based o the droop voltage error ad desred atteuato of the teracto betwee AC ad DC sdes of the coverter. It s foud that stablty s ot the ma lmtg factor for reasoable cable mpedace. The cable resstace s lmted by the rs of coverter over-modulato. The cable ductace ca be equal to or eve hgher tha the AC sde flter ductace wthout compromsg stablty. The the vestgated DC bus voltage cotrollers are compared terms of load sharg for a fve coverter system. I ths vestgato t s foud that the source coverters share the total load democratc for the mplemeted droop cotroller. Load sharg the case of reewable eergy sources DC bus voltage cotrol ad load sharg the case of o-dspatchable sources le wd power are also vestgated. I ths study the avalable put power must exceed the desred output power sce costat power loads are suppled. Most lely o-dspatchable sources requre low badwdth commucato to esure that more power tha avalable s ot delvered to the loads. A system suppled oly by wd power s cosdered to study load sharg the case of o-dspatchable sources. To acheve steady state power balace the wd power aggregates are equpped wth ptch agle cotrol. The vestgated voltage droop cotrol scheme s further developed to clude voltage droop offset.e. speed droop cotrol to hadle traset power varatos ad to obta democratc loadg of the wd power aggregates. The droop offset cotroller acts to reduce the power draw from wd turbes operatg wth lower avalable power tha expected. The sources ad loads operate as autoomous uts whch meas that hgh-speed commucato s ot eeded. The exterally calculated turbe speed refereces are ot updated durg the smulatos. Cosequetly the badwdth of the commucato requred for the vestgated system could be cosderably lower tha the samplg frequecy of the curret cotrollers (at least four orders of magtude the vestgated system). The smulato results verfy that dsturbaces are hadled properly.

145 8. Summary of results 37 Fault detecto Fault detecto ad clearace are mportat for ay electrcal dstrbuto system. For the vestgated DC power dstrbuto system groudg capactors are requred due to the fact that the coverter AC sdes should be galvacally separated to avod groud curret flowg betwee the coverters through protectve earth ad the DC bus. A groudg scheme ad a algorthm for detecto of groud faults ad short crcuts DC dstrbuted power systems are preseted for a system of sources ad loads wth hgh mpedace or o coecto to groud. A grouded system s preferable due to reasos of persoal safety ad protecto of equpmet. For DC dstrbuted power systems operated wth power electroc coverters the commo referece betwee sources ad loads provdes a path for the commo mode or eutral curret. The eutral curret appears sce the coverters have o AC sde termal coected to groud whch meas that groud currets caot be cotrolled. Also zero-sequece currets the form of thrd order harmocs are ofte cluded the modulato sgals to utlse the DC sde voltage more effectvely ad reduce the harmoc cotet (postve- ad egatve-sequece) of the AC sde currets. The scheme preseted here detects groud faults both o the AC ad DC sdes of the dstrbuted power system. I the vestgato groud faults are focused but a smlar algorthm ca be used to detect short crcuts by measurg two of the currets flowg to the cable ode. The selected detecto method reles o commucato betwee earby cable odes for fault localsato sce ths gves possblty to operate the DC dstrbuted power system eve f t s hghly segmeted due to multple faults. DC system tercoecto The groud fault detecto algorthm ot utlsg commucato to locate the fault s sestve to trasducer offset ad learty whe there s a hgh umber of cable odes the DC dstrbuto system. Therefore galvacally separated coecto of DC dstrbuto systems are vestgated. Also coecto of DC dstrbuto systems wth DC trasmsso ls s vestgated. Galvac separato s of great cocer the latter case also sce a groud fault o the trasmsso l would otherwse mpose a hgh voltage potetal the low voltage parts of the system. A exstg DC-DC coverter topology wth galvac separato s therefore adopted for DC trasmsso purposes. Ths s studed smulatos.

146 38 Chapter 8. Coclusos Expermetal results A laboratory set-up s mplemeted based o the results obtaed from the theoretcal aalyss. Frst the dyamc propertes are vestgated for a twocoverter system for several combatos of DC bus seres resstace ad ductace. The measuremets are asssted wth smulatos of a equvalet system. The good agreemet betwee smulato ad measuremet results verfy the dyamc propertes. Secod load sharg s verfed measuremets ad smulatos of a three-coverter DC rg bus system. The mportace of a accurate DC bus voltage measuremet s hghlghted. Thrd the algorthm to detect hgh mpedace groud faults s verfed expermets. The mportace of measuremet ose mmuty s hghlghted. 8. Future wor Oe of the beefts of the adopted voltage cotrol method.e. DC bus voltage droop cotrol s that commucato s ot requred. However the method proposed for selecto of DC bus capactor together wth the adopted requremets result a hgh capactace of the DC bus capactors. If the requremets are less strct the requred capactace s reduced. For example f the rated droop s mataed at.5 as Chapter 3 ad the rated closed loop dampg s reduced to.5 as Chapter 7 the requred DC bus capactace for each coverter s reduced to µf/w for a 75 V system. Furthermore the brea-over frequecy of the DC bus voltage flters mght be creased from the proposed 3 Hz especally f the source frequecy s hgher tha 5 Hz whch also results a reduced DC bus capactace. Ths should be vestgated both smulatos ad expermets. Load sharg the case of o-dspatchable sources should also be vestgated expermets. There are however some obstacles remag before local DC dstrbuto system mght become wdely accepted. Frstly the eed of galvac solato to prevet from zero-sequece dsturbaces results a cosderable cost. Secodly the fusg requred to protect ths d of system at short crcut faults ad the trasducers requred to detect groud faults are also costly. Therefore the system should be vestgated from a ecoomcal pot of vew. Aother safety ssue also eeds further vestgato. Ths ssue s related to the fact that there mght be loads that are oly fed from the DC system. If these are coected va a trasformer to reduce zero-sequece currets there s a potetal rs that faults o the load sde are ot cleared by the fuses ad ot detected by the cable odes f the eergy stored the load s low.

147 Refereces [] M. Bara ad N.R. Mahaja DC Dstrbuto for Idustral Systems: Opportutes ad Challeges IEEE Idustral ad Commercal Power Systems Techcal Coferec I&CPS Cof. Rec. Savaah GA USA May 5-8. pp [] M. Belhayat R. Cooley ad A. Wtuls Large Sgal Stablty Crtera for Dstrbuted Systems wth Costat Power Loads IEEE Power Electrocs Specalsts Coferece PESC 95 Cof. Rec. Atlata GA USA Ju vol. pp [3] A. Berzz A. Slvestr D. Zaell ad S. Massucco Short-Crcut Curret Calculatos for DC Systems IEEE Tras. Id. Applcat. vol. 3 o. 5 pp Sept./Oct [4] F. Blaabjerg U. Jaeger S. Mu-Nelse ad J.K. Pederse Power Losses PWM-VSI Iverter Usg NPT or PT IGBT Devces IEEE Power Electrocs Specalsts Coferece PESC 94 Cof. Rec. Tape Tawa Ju vol. pp [5] M. Bojrup P. Karlsso M. Alaüla ad B. Smosso A Dual Purpose Battery Charger for Electrc Vehcles IEEE Power Electrocs Specalsts Coferece PESC 98 Cof. Rec. Fuuoa Japa May vol. pp [6] M. Bojrup Advaced Cotrol of Actve Flters a Battery Charger Applcato Lcetate s Thess Departmet of Idustral Electrcal Egeerg ad Automato Lud Isttute of Techology Lud Swede Nov

148 4 Refereces [7] U. Borup Jese F. Blaabjerg ad J.K. Pederse Improved Voltage ad Frequecy Restorato Parallel Coected Three Phase Power Coverters IEEE Nordc Worshop o Power ad Idustral Electrocs NORPIE worshop proc. Aalborg Demar Ju. 3-6 pp [8] B.A. Bowles ad C.R. Paul Modellg Iterferece Propertes of SMPS DC Power Dstrbuto Buses IEEE Natoal Symposum o Electromagetc Compatblty Cof. Rec. Dever CO USA May pp [9] A. Carlsso The Bac-to-Bac Coverter; Cotrol ad Desg Lcetate s Thess Departmet of Idustral Electrcal Egeerg ad Automato Lud Isttute of Techology Lud Swede May 998. [] V.M. Caall J.A. Cobos R. Preto J. Uceda ad E. Olas Large- Sgal Modelg ad Smulato of Dstrbuted Power Systems IEEE Iteratoal Coferece o Idustral Electrocs Cotrol ad Istrumetato IECON 96 Cof. Proc. Tape Tawa Aug vol. pp [] I. Celaovc I. Mlosavljevc D. Boroyevch R. Cooley ad J. Guo A New Dstrbuted Dgtal Cotroller for the Next Geerato of Power Electrocs Buldg Blocs IEEE Appled Power Electrocs Coferece ad Exposto APEC Cof. Rec. New Orleas LA USA Feb. 6- vol. pp [] Qg Che Stablty Aalyss of Parallelled Rectfer Systems Iteratoal Telecommucatos Eergy Coferece INTELEC 95 Cof. Rec. Hague The Netherlads Oct. 9-Nov. 995 pp [3] J.-H. Cheg ad A.F. Wtuls Steady-State ad Large-Sgal Desg of Curret-Programmed DC-DC Coverters IEEE Tras. Power Electro. vol. o. 4 pp Jul [4] M. Crappe L. Gertmar A. Haböc W. Leoard ad D. Povh Power Electrocs ad Cotrol by Mcroelectrocs Future Eergy Systems EPE Joural vol. o. pp Apr..

149 Refereces 4 [5] J.C. Creber S. Busquets-Moge R. Gaet ad D. Boroyevch Modelg ad Aalyss of Hgh Frequecy Iteracto Betwee Cascaded Buc Coverters Europea Coferece o Power Electrocs ad Applcatos EPE Cof. Rec. Graz Austra Aug. 7-9 CD-Rom pages 9. [6] E. Dallago ad M. Passo Improvemets Voltage Regulato ad Curret Sharg wth the Droop Fucto Europea Coferece o Power Electrocs ad Applcatos EPE Cof. Rec. Graz Austra Aug. 7-9 CD-Rom pages 5. [7] J.C. Das ad R.H. Osma Groudg of AC ad DC Low-Voltage ad Medum-Voltage Drve Systems IEEE Tras. Id. Applcat. vol. 34 o. pp. 5-6 Ja./Feb [8] R.W. De Docer D.M. Dva ad M.H. Kheraluwala A Three- Phase Soft-Swtched Hgh-Power-Desty DC/DC Coverter for Hgh Power Applcatos IEEE Tras. Id. Applcat. vol. 7 o. pp Ja./Feb. 99. [9] K. Ersso HVDC Lght ad Developmet of Voltage Source Coverters IEEE/PES T&D Coferece & Exposto - Lat Amerca Cof. Rec. Sao Paulo Brasl Mar. 8- CD-ROM pages 5. [] X. Feg Z. Ye K. Xg F.C. Lee ad D. Borojevc Impedace Specfcato ad Impedace Improvemet for DC Dstrbuted Power System IEEE Power Electrocs Specalsts Coferece PESC 98 Cof. Rec. Fuuoa Japa May vol. pp [] X. Feg Z. Ye K. Xg F.C. Lee ad D. Borojevc Idvdual Load Impedace Specfcato for a Stable DC Dstrbuted Power System IEEE Appled Power Electrocs Coferece ad Exposto APEC 99 Cof. Rec. Dallas TX USA Mar vol. pp [] X. Feg Z. Ye K. Xg F.C. Lee ad D. Borojevc Motorg the Stablty of DC Dstrbuted Power Systems 5 th Aual Coferece of the IEEE Idustral Electrocs Socety IECEON 99 Proc. Sa Jose CA USA Nov. 9-Dec vol. pp [3] X. Feg ad F.C. Lee O-le Measuremet o Stablty Marg of DC Dstrbuted Power System IEEE Appled Power Electrocs Coferece ad Exposto APEC Cof. Rec. New Orleas LA USA Feb. 6- vol. pp

150 4 Refereces [4] X. Feg Z. Ye C. Lu R. Zhag F.C. Lee ad D. Boroyevch Fault Detecto DC Dstrbuted Power Systems Based o Impedace Characterstcs of Modules IEEE Idustry Applcatos Coferece IAS Cof. Rec. Rome Italy Oct. 8- vol. 4 pp [5] X. Feg J. Lu ad F.C. Lee Impedace Specfcatos for Stable DC Dstrbuted Power Systems IEEE Tras. Power Electro. vol. 7 o. pp Mar.. [6] K. Flescher ad R.S. Mugs Power Systems Aalyss for Drect Curret (DC) Dstrbuto Systems IEEE Tras. Id. Applcat. vol. 3 o. 5 pp Sept./Oct [7] M. Florez-Lzarraga ad A.F. Wtuls Iput Flter Desg for Multple-Module DC Power Systems IEEE Power Electrocs Specalsts Coferece PESC 93 Cof. Rec. Seattle WA USA Ju pp [8] E.W. Gholdsto K. Karm F.C. Lee J. Rajagopala Y. Paov ad B. Maers Stablty of Large DC Power Systems Usg Swtchg Coverters wth Applcato to the Iteratoal Space Stato Itersocety Eergy Coverso Egeerg Coferece IECEC 96 Proc. Washgto DC USA Aug vol. pp [9] J.S. Glaser ad A.F. Wtuls Output Plae Aalyss of Load-Sharg Multple-Module Coverter Systems IEEE Tras. Power Electro. vol. 9 o. pp Ja 994. [3] A. Grauers Desg of Drect-drve Permaet-maget Geerators for Wd Turbes PhD Thess Departmet of Electrc Power Egeerg Dvso of Electrcal Maches ad Power Electrocs Chalmers Uversty of Techology Gotheburg Swede Nov [3] N. Hadjsad J.-F. Caard ad F. Dumas Dspersed Geerato Icreases the Complexty of Cotrollg Protectg ad Matag the Dstrbuto Systems IEEE Computer Applcatos Power vol. o. pp. -8 Apr [3] L. Harefors O Aalyss Cotrol ad Estmato of Varable- Speed Drves Ph.D. Thess Departmet of Electrcal Power Egeerg Dvso of Electrcal Maches ad Power Electrocs Royal Isttute of Techology Stocholm Swede 997.

151 Refereces 43 [33] C.C. Heath The Maret for Dstrbuted Power Systems IEEE Appled Power Electrocs Coferece ad Exposto APEC 9 Cof. Rec. Dallas TX USA Mar pp [34] S. Ht ad D. Boroyevch Cotrol of Frot-Ed Three-Phase Boost Rectfer IEEE Appled Power Electrocs Coferece ad Exposto APEC 94 Cof. Rec. Orlado FL USA Feb vol. pp [35] J. Holtz Pulsewdth Modulato for Electroc Power Coverso Proc. of the IEEE vol. 8 o. 8 pp Aug [36] G.C. Hua W.A. Tabsz C.S. Leu N. Da R. Watso ad F.C. Lee Developmet of a DC Dstrbuted Power System IEEE Appled Power Electrocs Coferece ad Exposto APEC 94 Cof. Rec. Orlado FL USA Feb vol. pp [37] B.T. Irvg ad M.M. Jovaovc "Aalyss Desg ad Performace Evaluato of Droop Curret-Sharg Method" IEEE Appled Power Electrocs Coferece ad Exposto APEC Cof. Rec. New Orleas LA USA Feb. 6- vol. pp [38] C. Jamerso T. Log ad C. Mullett Seve Ways to Parallel a Magamp IEEE Appled Power Electrocs Coferece ad Exposto APEC 93 Cof. Rec. Sa Dego CA USA Mar pp [39] B.K. Johso R.H. Lasseter ad R. Adapa Power Cotrol Applcatos o a Supercoductg LVDC Mesh IEEE Tras. Power Delvery. vol. 6 o. 3 pp Jul. 99. [4] B.K. Johso ad R.H. Lasseter A Idustral Power Dstrbuto System Featurg UPS Propertes IEEE Power Electrocs Specalsts Coferece PESC 93 Cof. Rec. Seattle WA USA Ju pp [4] B.K. Johso R.H. Lasseter F.L. Alvarado ad R. Adapa Expadable Multtermal DC Systems Based o Voltage Droop IEEE Tras. Power Delvery vol. 8 o. 4 pp Oct. 993.

152 44 Refereces [4] B.K. Johso R.H. Lasseter ad F.L. Alvarado Icorporato of a SMES Col to a Supercoductg LVdc Trasmsso System IEEE Tras. Appl. Supercoductvty vol. 7 o. pp Ju [43] P. Karlsso "Quas Resoat DC L Coverters - Aalyss ad Desg for a Battery Charger Applcato" Lcetate s thess Departmet of Idustral Electrcal Egeerg ad Automato Lud Isttute of Techology Lud Swede November 999. [44] J.W. Km H.S. Cho ad B.H. Cho "A Novel Droop Method for the Coverter Parallel Operato" IEEE Appled Power Electrocs Coferece ad Exposto APEC Cof. Rec. Aahem CA USA Mar. 4-8 vol. pp [45] H. Lauamp The New Germa Electrc Safety Stadard for Resdetal PV Systems Cof. Rec. IEEE Photovoltac Specalsts Coferece Washgto DC USA May pp [46] F.C. Lee P. Barbosa P. Xu J. Zhag B. Yag ad F. Caales Topologes ad Desg Cosderatos for Dstrbuted Power System Applcatos proc. of the IEEE vol. 89 o 6 pp Ju.. [47] F.C. Lee ad J.H.Q. Ly Stablty Robustess Agast Real Parameter Ucertaty of DC Electrcal Power Coverso Systems Cof. Proc. IEEE Regoal Coferece o Aerospace Cotrol Systems May pp. -5. [48] H.D. Lee ad S.K. Sul A Commo Mode Voltage Reducto Boost Rectfer/Iverter System by Shftg Actve Voltage Vector a Cotrol Perod IEEE Tras. Power Electro. vol. 5 o. 6 pp. 94- Nov.. [49] J.-C. Lao ad S.-N. Yeh A Novel Istataeous Power Cotrol Strategy ad Aalytc Model for Itegrated Rectfer/Iverter Systems IEEE Tras. Power Electro. vol. 5 o. 6 pp Nov..

153 Refereces 45 [5] J. Lu X. Feg F.C. Lee ad D. Borojevch Stablty Marg Motorg for DC Dstrbuted Power Systems Va Curret/Voltage Perturbato IEEE Appled Power Electrocs Coferece ad Exposto APEC Cof. Rec. Aahem CA USA Mar. 4-8 vol. pp [5] D.L. Logue ad P.T. Kre Prevetg Istablty DC Dstrbuto Systems by Usg Power Bufferg IEEE Power Electrocs Specalsts Coferece PESC Cof. Rec. Vacouver BC Caada Ju. 7- vol. pp [5] S. Luo Z. Ye R.-L. L ad F.C. Lee A Classfcato ad Evaluato of Parallelg Methods for Power Supply Modules IEEE Power Electrocs Specalsts Coferece PESC 99 Cof. Rec. Charlesto SC USA Ju. 7-Jul. 999 vol. pp [53] R. Madelbaum Reap the Wld Wd IEEE Spectrum vol. 9 o. pp Oct.. [54] J.A. Marrero Uderstad Groud Fault Detecto ad Isolato DC Systems IEEE Power Egeerg Socety Summer Meetg PES Cof. Rec. Seattle WA USA Jul. 6- vol. 3 pp [55] R.D. Mddlebroo Iput Flter Cosderatos Desg ad Applcato of Swtchg Regulators IEEE-IAS Aual Meetg Cof. Rec Oct Chcago IL. USA. Republshed Advaces Swtch-Mode Power Coverso Volumes I ad II d edto TESLAco 983 paper 7 pp [56] R.B. Mddlebroo Null Double Ijecto ad The Extra Elemet Theorem IEEE Tras. Educato vol. 3 o. 3 pp Aug [57] N. Moha T. Udelad ad W.P. Robbs Power Electrocs: Coverters Applcatos ad Desg d edto Joh Wley ad Sos Ic. New Yor NY USA 995. [58] Z. Moussaou I. Batarseh H. Lee ad C. Keedy A Overvew of the Cotrol Scheme for Dstrbuted Power Systems Southco/96 Cof. Rec. Orlado FL USA Ju pp

154 46 Refereces [59] U. Ncola T. Rema J. Petzoldt ad J. Lutz Applcato maual Power Modules Semro Iteratoal" edtor: P.R.W. Mart ISLE Ilmeau. [6] T. Nova L.A. Morley ad F.C. Trutt Sestve Groud-Fault Relayg" IEEE tras. o Id. Appl. vol. 4 o. 5 pp Sept/Oct [6] Y. Paov J. Rajagopala ad F.C. Lee Aalyss ad Desg of N Paralleled DC-DC Coverters wth Master-Slave Curret-Sharg Cotrol IEEE Appled Power Electrocs Coferece ad Exposto APEC 97 Cof. Rec. Atlata GA USA Feb vol. pp [6] J. Rajagopala K. Xg Y. Guo ad F.C. Lee Modelg ad Dyamc Aalyss of Paralleled DC/DC Coverters wth Master-Slave Curret Sharg Cotrol IEEE Appled Power Electrocs Coferece ad Exposto APEC 97 Cof. Rec. Sa Jose CA USA Mar vol. pp [63] R.L. Smth Jr. Cotrol Batteres: Power System Lfe Savers IEEE Idustral Applcatos Magaze vol. o. 6 pp. 8-5 Nov./Dec [64] K. Sr ad J. Bada "Aalyss ad Evaluato of Curret-Sharg Cotrol for Parallel-Coected DC-DC Coverters tag to accout Cable Resstace" IEEE Aerospace Applcatos Coferece Cof. Proc. Aspe CO USA Feb vol. pp [65] S.D. Sudhoff S.F. Glover S.H. Za S.D. Pare E.J. Zv D.E Delsle ad J. Sauer "Cotrol of Zoal DC Dstrbuto Systems: A Stablty Perspectve" IASTED Power ad Eergy Systems Coferece PES Cof. Proc. Mara del Rey CA USA May 3-5 pp [66] W. Tag ad R.H. Lasseter A LVDC Idustral Power Dstrbuto System Wthout Cetral Cotrol Ut IEEE Power Electrocs Specalsts Coferece PESC Cof. Rec. Galway Irelad Ju. 8-3 vol. pp

155 Refereces 47 [67] G.S. Thad R. Zhag K. Xg F.C. Lee ad D. Boroyevch Modelg Cotrol ad Stablty Aalyss of a PEBB based DC DPS IEEE Tras. Power Delvery vol. 4 o. pp Apr [68] Y.-S. Tzeg N. Che ad R.-N. Wu A Detaled R-L Brdge Coverter Model for Power Flow Studes Idustral AC/DC Power Systems IEEE Tras. Idustral Electrocs vol. 4 o. 5 pp Oct [69] K. Vage T. Melaa A.K. Adaes ad P.E. Krstase Dual Actve Brdge Coverter wth Large Soft-Swtchg Rage Europea Coferece o Power Electrocs ad Applcatos EPE 93 Cof. Rec. Brghto UK Sept vol. 3 pp [7] C.M. Wldrc F.C. Lee B.H. Cho ad B. Cho A Method of Defg the Load Impedace Specfcato for A Stable Dstrbuted Power System IEEE Power Electrocs Specalsts Coferece PESC 93 Cof. Rec. Seattle WA USA Ju pp [7] P.-L. Wog F.C. Lee ad X. Zhou Stablty Study of PC Power System IEEE Idustry Applcatos Coferece IAS 99 Cof. Rec. Phoex AZ USA Oct vol. 3 pp [7] K. Xg F.C. Lee J.S. La G. Thad ad D. Borojevc Adjustable Speed Drve Neutral Voltage Shft ad Groudg Issues a DC Dstrbuted Power System IEEE Idustry Applcatos Coferece IAS 97 Cof. Rec. New Orleas LA USA Oct vol. pp [73] K. Xg J. Guo W. Huag D. Peg F.C. Lee ad D. Borojevc A Actve Bus Codtoer for a Dstrbuted Power System IEEE Power Electrocs Specalsts Coferece PESC 98 Cof. Rec. Fuuoa Japa May vol. pp [74] K. Xg S. Mazumder Z. Ye F.C. Lee ad D. Borojevc The Crculatg Curret Paralleled Three-Phase Boost PFC Rectfers IEEE Power Electrocs Specalsts Coferece PESC 98 Cof. Rec. Fuuoa Japa May vol. pp

156 48 Refereces [75] Z. Ye K. Xg S. Mazumder D. Borojevc ad F.C. Lee Modelg ad Cotrol of Parallel Three-Phase PWM Boost Rectfers PEBB- Based DC Dstrbuted Power Systems IEEE Appled Power Electrocs Coferece ad Exposto APEC 98 Cof. Rec. Aahem CA USA Feb vol. pp [76] Z. Ye D. Boroyevch K. Xg F.C. Lee Desg of Parallel Sources DC Dstrbuted Power Systems by Usg Ga-Schedulg Techque IEEE Power Electrocs Specalsts Coferece PESC 99 Cof. Rec. Charlesto SC USA Ju. 7-Jul. 999 vol. pp [77] Z. Ye D. Boroyevch K. Xg F.C. Lee Parallelg No-Isolated Mult-Phase PWM Coverters IEEE Idustry Applcatos Coferece IAS Cof. Rec. Rome Italy Oct. 8- vol. 4 pp [78] R. Zhag V.H. Prasad D. Boroyevch ad F.C. Lee Aalyss ad Desg of a Three-Phase Iverter wth Neutral Leg Europea Coferece o Power Electrocs ad Applcatos EPE 97 Cof. Rec. Trodhem Norway Sept vol. pp [79] E. Zhou ad A. Nasle Smulato of DC Power Dstrbuto Systems IEEE Idustral ad Commercal Power Systems Techcal Coferec I&CPS 94 Cof. Rec. Irve CA USA May pp [8] K.J. Åström ad T. Hägglud PID Cotrollers: Theory Desg ad Tug d edto Istrumet Socety of Amerca Research Tragle Par NC USA 995. [8] K.J. Åström ad B. Wttemar Computer Cotrolled Systems; Theory ad Desg d edto Pretce Hall Ic. Eglewood Clffs NJ USA 99.

157 Appedx A Modulato Modulato meas brg order or agreemet wth. For power electroc swtch mode coverters ths s terpreted as the creato of a pulse patter where the average voltage ( the case of voltage source coverters) equals the desred output voltage. Here oly carrer wave modulato [35] s dscussed. Other methods exsts maly tolerace or dead-bad cotrol but are left out here. Aother lmtato made s that oly tragular carrer based modulato s dscussed ad saw-tooth carrer modulato left out. Frst dfferet types of referece waveforms for the sub-oscllato ad modfed sub-oscllato methods [35] are dscussed. These are: the susodal symmetrcal ad bus-clamped referece waveforms. The ma dffereces betwee these are frstly to what extet they are able to utlse the DC l voltage ad secodly the harmoc curret spectrum they produce. Both the dfferetal mode ad commo mode spectrums for the output voltages are vestgated ad compared. Also typcal curret spectrums are vestgated. Secod examples of the swtchg patter for each modulato referece are examed detal by meas of curret space vectors. Here t s foud that the oly dfferece betwee the carrer refereces s how log each zero voltage vector s appled. A. Modulato methods As prevously metoed three dfferet carrer wave modulato methods are vestgated. Tolerace bad cotrol where the curret s allowed to vary a bad ± aroud the curret referece s ot dscussed here. However t should be clear that tolerace bad cotrol of course gves a hgh dyamc performace at the expese of a varyg swtchg frequecy. A varyg 49

158 5 Appedx A. Modulato swtchg frequecy s ot desrable sce ths maes semcoductor swtchg loss approxmato cumbersome. Also the hgh frequecy harmoc curret cotet strogly affects the desg of the output flter ductors. Especally the losses due to ro core eddy currets are complcated to estmate f the harmoc cotet s varyg. I the case of carrer wave modulato o the other had the swtchg frequecy s well determed sce t equals the fudametal frequecy of the carrer. Stll the ampltude of the curret harmocs vares wth the loadg of the coverter but the frequeces at whch the harmocs appear are fxed. The oly dfferece betwee the vestgated carrer wave modulato schemes s the referece waveforms. To be more correct the oly dfferece s whether a zero-sequece sgal s added or ot ad f added what the zero-sequece loos le [35]. A zero-sequece compoet the refereces does ot show up the output voltage sce the coverter s ot coected to the eutral. Therefore the coverter caot produce ay voltage affectg the eutral. A zero-sequece voltage per defto results a zero-sequece curret ad sce o eutral s coected there s o path for the zero-sequece (or sometmes called eutral) curret to flow through. Ths meas that all the referece waveforms cosdered ca be treated as beg orgally susodal but later altered wth a zero-sequece compoet. The referece waveforms are altered to affect the harmoc curret spectrum or to crease the utlsato of the coverter by creasg the maxmum allowable modulato dex for whch lear modulato s obtaed. The modulato dex m a s defed as m u ref where a b c (A.) V / a dc where u s the coverter output phase potetal ad V dc the DC bus voltage. The reaso why m a s calculated usg V dc / s that most cases the tragular carrer has a DC level equal to zero ad ampltude proportoal to V dc /. Here the ampltude s equal to V dc /. Ths s because otherwse the referece sgals should be scaled by the same factor as the carrer pea-to-pea level order to get a accurate modulato. Note that for full-brdge coverters the carrer DC level s ot crtcal sce the output voltages are dfferetal.e. le-tole voltages.

159 A. Modulato methods 5 Whe m a hgher tha occurs the swtchg of the partcular phase s hbted sce o crossgs betwee the carrer ad the referece waveforms occur. Ths stuato s termed over-modulato. Over-modulato s equal to actuator saturato ad should be avoded at least for statoary operato. The problem s ot oly that the cotroller commad sgals are ot obeyed by the power electroc coverter but also that the output curret harmoc cotet creases strogly [35][57]. The most mportat ssue for all the vestgated modulato methods s that the le-to-le output voltage should be equal for the dfferet referece sgals. As metoed earler the voltage refereces are modfed by a zerosequece sgal such a way that the maxmum m a s altered. The dfferet voltage refereces are show Fgure A. for a tme equal to oe perod of the fudametal. 4 u aref u azref [V] t [ms] Fgure A.: Carrer wave modulato: susodal (blac) symmetrcal (grey) ad busclamped (lght-grey) voltage refereces. The le-to-le output voltage resultg from these refereces equals 4 V 5 Hz all the cases. For susodal modulato the refereces are ept as they are.e. as susodal phase potetals. For symmetrcal refereces the refereces are altered such a way that the most postve ad most egatve referece s made equal but wth opposte sg. For bus-clamped modulato the referece wth the hghest stataeous value (postve or egatve) s clamped to ± / depedet o whch s the closest. V dc For susodal refereces t s clear that over-modulato.e. m a occurs whe the referece pea equals half the DC l voltage. Therefore u Vdc where a b c (A.) ref max

160 5 Appedx A. Modulato for susodal modulato. For symmetrcal modulato the zero-sequece sgal s calculated from ( max( u u u ) + m( u u u ) (A.3) u z a ref b ref c ref a ref b ref c ref For /6 th of the fudametal perod where u aref s the most postve ad u bref s the most egatve referece statoary codtos the resultg referece for the half-brdge coected to the a-phase s wrtte 3 π uaz ref ua ref uz uˆ cos ωt (A.4) 6 As the prevous case over-modulato occurs whe the referece equals half the DC l voltage whch gves u Vdc where a b c (A.5) 3 z ref max For bus-clamped modulato the trasto betwee two bus-clamped refereces s vestgated. Assume that the b-phase has bee clamped to V dc / ad that the a-phase s gog to be clamped to + V dc /. Whe ths occurs 3 3 ua ref uˆ ad ub ref uˆ (A.6) Ths meas that the zero-sequece voltage to be set equals Ths gves ad 3 V ˆ dc u z u < (A.7) 3 3 V ˆ ˆ dc Vdc u az ref u u (A.8)

161 A. Modulato methods 53 u 3 3 Vdc Vdc uˆ uˆ 3 uˆ (A.9) bz ref The lmt for over-modulato s gve by u bz ref Vdc V 3 ˆ dc u (A.) whch gves u Vdc where a b c (A.) 3 z ref max Ths meas that modulato wth symmetrcal or bus-clamped refereces provdes a 5 % hgher marg to over-modulato compared to modulato wth susodal refereces. The harmoc cotet of the output voltage depeds o the waveform of the referece voltage. Both the dfferetal mode (DM) harmocs.e. the harmoc cotet u u u where j a b c (A.) j z jz ad the commo mode (CM) harmoc cotet.e. the harmoc cotet u z are of great mportace. For example the DM harmocs result losses flter ductors etc. The CM harmocs ca also result parastc curret through capactve couplg betwee coductors ad groud. I tur ths results malfucto of earth protectors ad the occurrece of bearg currets motors. The DM ad CM harmoc cotet for the dfferet modulato refereces Fgure A. are show Fgure A. ad Fgure A.3 respectvely. For a purely ductve flter the dampg s proportoal to the frequecy sce the mpedace s gve by Z L jω L (A.3) The resultg harmoc cotet the output currets s show Fgure A.4 the case of LL le.7 mh. Ths flter ductace s sutable for a W coverter wth 75 V DC bus voltage coected to a 4 V three-phase AC grd [6]. Note that the harmoc curret cotet s calculated from the DM spectrum of the output voltage.

162 54 Appedx A. Modulato u DMp [V] u DMp [V] u DMp [V] h Fgure A.: Dfferetal mode output voltage spectrum for susodal (top) symmetrcal (mddle) ad bus-clamped modulato (bottom). The fudametal frequecy s 5 Hz ad the spectrums are show as a fucto of harmoc order h where deotes the fudametal. u CMp [V] u CMp [V] u CMp [V] h Fgure A.3: Commo mode output voltage spectrum for susodal (top) symmetrcal (mddle) ad bus-clamped modulato (bottom). The fudametal frequecy s 5 Hz ad the spectrums are show as a fucto of harmoc order h where deotes the fudametal.

163 A. Modulato methods 55 3 p [A] 3 p [A] 3 p [A] 3 4 h Fgure A.4: Output curret spectrum for susodal (top) symmetrcal (mddle) ad busclamped modulato (bottom). The fudametal frequecy s 5 Hz ad the spectrums are show as a fucto of harmoc order h where deotes the fudametal. A. Vector represetato A space vector s rαβ s defed from stataeous three-phase values s a s b ad s c accordg to r s π 4π j j αβ j sa e + sb e 3 + sc e 3 sα + For symmetrcal three-phase quattes.e. f s s s sˆ cos ( ω t) sˆ cos ωt sˆ cos ωt the power-varat trasformato s gve by a b c π 3 4π 3 js β (A.4) (A.5)

164 56 Appedx A. Modulato s s α β 3 s a ( s s ) b c (A.6) It s mportat to uderstad that the last expresso caot be used for swtched quattes sce these are ot symmetrcal. I the statoary αβframe the same calculato methods as used for regular three-phase calculatos ca be used. Krchoff s voltage law space coordates appled to a three-phase coverter wth ductve flter coected to a three-phase grd gves r u αβ L d dt r αβ r R αβ r e αβ r u αβ L Ths meas that the curret dervatves are expressed as d dt r αβ r e αβ (A.7) dα dt L dβ dt L ( u e ) α ( u e ) β α β (A.8) Assumg that the swtchg frequecy perod tme T sw s much loger tha the tme costat of the ductve flter.e. Tsw / fsw << τ el L R mples that the curret dervatves ca be approxmated accordg to α t L β t L ( u e ) α ( u e ) β α β α β L L ( u e ) α ( u e ) β α β t t (A.9) Sce tragular carrer modulato s utlsed the durato of each terval ca be calculated from ther carrer crossgs. For oe half perod (egatve slope) of the carrer the followg expresso s vald u ref V dc V T dc s t u t V ref dc T s (A.)

165 A. Vector represetato 57 Note that t s the tme durato for whch a certa voltage vector s appled other words the dstace betwee two cosecutve carrer crossgs for the dfferet referece voltages. Actually for the vestgated carrer wave modulato strateges the oly dfferece s the tme durato for whch each dfferet voltage vector s appled. The samplg tme T s s selected as half the swtchg frequecy tme perod.e. s T sw T. Furthermore the samplg stats are sychrosed wth the carrer such a way that the samplg stats cocde wth the carrer peas. Ths s doe order to perform the samplgs whe the currets pass ther average to avod samplg dstorto. The grd s cosdered as beg symmetrcal.e. ( ) 3 4 cos ˆ 3 cos ˆ cos ˆ π ω π ω ω t e e t e e t e e c b a (A.) The stataeous grd voltages for 4 t ω are gve by + e e e e e e c b a ˆ 3 ˆ 3 ˆ (A.) Ths gves ( ) e e e e e e e c b a ˆ 3 ˆ 3 3 β α (A.3)

166 58 Appedx A. Modulato To calculate the coverter output voltage (whch s ot a symmetrcal threephase quatty) equato (A.4) has to be used. The swtches are cosdered as beg deal.e. the output voltage assumes the two dscrete levels ± V dc. The voltage vectors appled for ω t 4 are show Fgure A.5. q u e d u u u Fgure A.5: The grd voltage vector e r ad the coverter output voltage vectors appled at ω tπ/4. The voltage vectors are calculated Table A.. Table A.: Voltage vectors used at ω tπ/4. Swtch state u α u β 3 V dc 6 V dc V dc I the followg sectos the swtchg behavor s vestgated for the dfferet modulato strateges. As the prevous secto the vestgato s performed uder the codtos lsted Table A.. Table A.: Coverter specfcato. DC l voltage V dc 75 V Grd pea voltage ê 35 V Grd frequecy f 5 Hz Swtchg frequecy f sw 5 Hz Le flter ductace L.7 mh

167 A. Vector represetato 59 Susodal modulato I the case of susodal refereces o-load codto the statoary voltage referece for each phase s gve by the stataeous grd voltage. At ω t 4 ths meas that u u u a ref b ref c ref eˆ 9.8 V 3 eˆ 84.V 3 + eˆ 33.9 V (A.4) The carrer ad the coverter output voltage refereces the case of susodal modulato are show Fgure A.6. Fgure A.6 also shows the swtchg states appled. Note that oly the vectors depcted Fgure A.5 are used as expected. +V dc/ u carrer u aref u bref T s T s t -V dc/ u cref s a s b s c Fgure A.6: The modulato carrer ad the voltage refereces at ω tπ/4 the case of modulato wth susodal refereces. The lower part shows the appled swtch states. The correspodg carrer wave crossgs occur at (calculated for the egatve slope)

168 6 Appedx A. Modulato V V V s s dc ref c c s s dc ref b b s s dc ref a a T T V u t T T V u t T T V u t (A.5) The correspodg durato of each voltage vector (durg the egatve slope of the carrer) are thus equal to + V 8. V 53. V 9.4 V 9.4 s dc ref c c s s dc ref c dc ref b b c s dc ref b dc ref a a b s dc ref a a T V u t T t T V u V u t t t T V u V u t t t T V u t t (A.6) Applyg ths to equato (A.9) gves curret vector varato accordg to Table A.3. Table A.3: Curret vector crease. Swtch state α [A] β [A] Note that the sum of the varatos equals zero. Ths s approxmately true f the pulse umber m f.e. the rato betwee swtchg frequecy ad fudametal of the output voltage s hgh. Also f m f s hgh the grd voltage vector does ot chage much durg the followg carrer half perod sce the

169 A. Vector represetato 6 sampled grd voltages are almost ualtered. Ths yelds that the same coverter output voltage vectors appear the opposte order for approxmately the same durato as for the prevous samplg terval. The space vector curret trajectory for oe swtchg terval s show Fgure A.7. Fgure A.7: Curret vectors for modulato wth susodal refereces at ω tπ/4. Symmetrcal modulato For symmetrcal refereces o-load operato the statoary voltage referece for each phase s ot gve by the stataeous grd voltage. Istead the most postve referece ad the most egatve referece are altered to have the same magtude. Ths s doe the followg maer ad gves for t 4 ω uz max( ua ref ub ref uc ref ) + m( ua ref ub ref uc ref ) ( ) ( u + u ) ( ) V 4.5 V a ref c ref Ths gves the voltage refereces (A.7) u u u az ref bz ref cz ref u u u a ref b ref c ref u u u z z z 7.85 V 6.5 V 7.85 V (A.8) The correspodg swtchg tmes (calculated for the egatve slope of the carrer) are

170 6 Appedx A. Modulato t t t a b c uaz V ubz V ucz V ref dc ref dc ref dc T T T s s s.38 T.33 T.863 T s s s V V V (A.9) The correspodg durato of each voltage vector (durg the egatve slope of the carrer) s thus equal to t t t t t t t a b c T s uaz V t t a b t c uaz V ubz V ref dc ref dc ucz + V ref dc T ubz V ucz V ref dc ref dc ref dc s T s 3.8 V T T s s V V V (A.3) Applyg ths to equato (A.9) gves curret varato accordg to Table A.4. Table A.4: Curret vector crease. Swtch state α [A] β [A] Also ths case the sum of the varatos equals zero. The space vector curret trajectory for oe swtchg terval.e. both the postve ad the egatve slope of the carrer s show Fgure A.8.

171 A. Vector represetato 63 Fgure A.8: Curret vectors for modulato wth symmetrcal refereces at ω tπ/4. Bus-clampg modulato For bus-clamped refereces o-load codto the statoary voltage referece for each phase s ot gve by the stataeous grd voltage. Istead the referece wth the most postve or egatve stataeous voltage s clamped to a level equal plus or mus half the DC l voltage.e. ± V dc. As for symmetrcal modulato ths s equal to calculatg a eutral pot voltage dfferg from zero. Ths s doe the followg maer u z max m Vdc ( u u u ) f max( u ) > m( u ) a ref Vdc ( u u u ) + f max( u ) < m( u ) a ref b ref b ref For ω t 4 ths yelds c ref c ref ref ref ref ref Vdc V ( u u u ) + u + 6.V (A.3) u z m a ref b ref c ref c ref (A.3) The resultg voltage refereces are calculated accordg to dc u u u az ref bz ref cz ref u u u a ref b ref c ref u u u z z z 68.7 V 3. V 375. V (A.33) The correspodg swtchg tmes (calculated for the egatve slope of the carrer):

172 64 Appedx A. Modulato t t t a b c uaz V ubz V ucz V ref dc ref dc ref dc T T s T s s.75 T.469 T. T s s s V V V (A.34) The correspodg durato of each voltage vector (durg the egatve slope of the carrer) s equal to t t t t t t t a b c T s uaz V t t a b t c uaz V ubz V ref dc ref dc ucz + V ref dc T ubz V ucz V ref dc ref dc ref dc s T s 7.5 V T T s s V V V (A.35) Applyg ths to equato (A.9) gves curret crease accordg to Table A.5. Table A.5: Curret vector crease. Swtch state α [A] β [A] As before the sum of the varatos equals zero. The space vector curret trajectory for oe swtchg terval.e. both the postve ad the egatve slope of the carrer s show Fgure A.9.

173 A. Vector represetato 65 Fgure A.9: Curret vectors for modulato wth bus-clamped refereces at ω tπ/4.

174

175 Appedx B Vector cotrol A model-based cotroller s derved for a grd coected voltage source coverter. The cotroller s model-based the sese that the cotroller parameters are depedet o the grd parameters.e. L (L le ) ad R (R le ). The curret cotroller for three-phase coverters dscussed here s based o the sychroously rotatg (dq) referece frame. Sychroously rotatg refers to that the referece frame s rotatg wth the same speed as the grd voltage αβ vector e r. The rotatg referece system has two axes deoted d ad q. The grd voltage vector e rαβ cocdes wth the q-axs ths case whch meas that e (Fgure A.5). The trasformato expressos are wrtte d v dq vαβ jω t v αβ v dq s s e ad s s e jω t (B.) The cotroller s based o a model of the grd together wth the coverter output flter r u αβ L d dt r αβ r R αβ r e Ths s trasformed to dq-coordates by use of the trasformato above.e. r u dq e jω t d dt αβ r r dq jωt dq jωt rdq jωt ( e ) R e e e L (B.) (B.3) whch gves r u dq e jω t L d dt r dq e jω t jω r dq jω t r dq jω t jω t L e R e e e r dq (B.4) 67

176 68 Appedx B. Vector cotrol Smplfyg the last expresso gves dq dq dq dq dq e R L j dt d L u r r r r r ω (B.5) If ths s dvded to ts compoets.e. real ad magary parts the resultg expressos are q d q q q d q d d d e L R dt d L u e L R dt d L u ω ω (B.6) Note the cross-couplg terms. A dscrete-tme dead-beat PI-cotroller s desged for each compoet based o the last two expressos. The output from the cotroller s two voltage refereces oe d- ad oe q-drecto. The frst step s to use bacward Euler approxmato [8] for the curret dervatves. Ths gves s q q q s d d d T dt d T dt d (B.7) Furthermore t s assumed that the currets ca be approxmated wth ther average values the partcular samplg terval + + q q q d d d (B.8) It s also assumed that the grd voltage does ot chage betwee two samples. Cosequetly q q d d e e e e (B.9)

177 Appedx B. Vector cotrol 69 Ths gves the followg result q d d q q s q q q d q q d d s d d d e L R T L u e L R T L u ω ω (B.) Sce a dead-beat cotroller s cosdered t s assumed that ref q q ref d d (B.) gvg q d ref d q ref q s q ref q q d q ref q d ref d s d ref d d e L R T L u e L R T L u ω ω (B.) Ths gves a P-cotroller accordg to ( ) ( ) q d ref d q q ref q s ref q d q ref q d d ref d s ref d e L R R T L u e L R R T L u ω ω (B.3) The resstve voltage drop term ca be terpreted as a tegral part assumg that the curret equals the sum of all the prevous curret errors.e. ( ) ( ) q ref q q d ref d d (B.4) Ths gves a PI-cotroller

178 7 Appedx B. Vector cotrol ( ) ( ) ( ) ( ) q d ref d c q ref q q ref q ref q d q ref q c d ref d d ref d ref d e K T K u e K T K u (B.5) where L K RT L R T L R T R T L K c s s s ω (B.6) The mpact of the oe-sample delay troduced by DSP-cotrol (Chapter ) s reduced by applcato of a Smth-predctor [6]. The Smth predctor calculates curret refereces accordg to [6] + q s d s q s q smth d s q s d s d smth u L T s T s L RT u L T s T s L RT ω ω (B.7) q s d s q s q d s q s d s d u L T s T s L RT s u L T s T s L RT s ω ω (B.8) The curret refereces above are added to the curret refereces based o desred output power. The resultg voltage refereces dq coordates are trasformed to the fxed αβ-frame. The the αβ-refereces are trasformed to three-phase referece voltages. If the modulato s based o susodal refereces the three-phase voltage refereces are used as they are. Otherwse they are mapulated for example to become symmetrcal or bus-clamped ad the passed o to the modulator.

179 Appedx C Coverter losses I ths appedx a aalytcal method for estmato of the semcoductor losses of a self-commutated three-phase VSC s descrbed. A smlar method s foud [59]. The calculatos are made for a sgle half-brdge see Fgure C.. Sce the output from a three-phase VSC s a le-to-le voltage the correspodg le-to-eutral voltage has to be calculated f oly a sgle halfbrdge s cosdered. The orgal susodal voltage refereces are used eve though they are phase potetals. Ths s applcable sce the average losses are calculated oly for the fudametal curret compoet.e. eglectg the rpple. T D V dc C dc L le R le T D u e LN Fgure C.: Oe half-brdge of a three-phase voltage source coverter. The calculatos are based o data sheet formato whch s usually oly vald for ductve load currets. For a VSC utlsg hard-swtchg ths s ot a lmtato sce the AC sde flters are ductve ths case. Furthermore the calculatos oly tae the fudametal curret to accout.e. the curret rpple s ot cosdered. Fgure C. shows the fudametal compoets of the output voltage ad curret for oe half-brdge of the coverter. The coverter output curret lags the voltage wth a agle ϕ. 7

180 7 Appedx C. Coverter losses u T t Fgure C.: Coverter output voltage ad curret. The curret s dsplaced by a agle ϕ relatve to the voltage. For the IGBTs of oe half-brdge the swtchg losses are estmated from P T sw T T E V o fsw ( P + P ) dt ( E + E ) o + E I dc off E π V o off + E dc Vdc f T I off sw T V T dc I T f sw o off dt ˆ s( ω t ϕ ) dt (C.) where E o ad E off are the tur-o ad tur-off eergy loss per swtchg cycle specfed data sheets for DC l voltage V dc ad ductvely clamped output curret I. The swtchg losses for the freewheelg dodes of a halfbrdge are calculated a smlar maer. The tur-o loss for a swtchg dode s usually eglgble whereas the tur-off losses are almost completely due to reverse recovery (E Drr ). Ths gves P fsw ( P + P ) dt ( E + E ) D sw o off T T T T E π V off dc I V dc I f sw o off E π V Drr dc dt I V dc I f sw (C.) The coducto losses are more complcated to calculate. The forward voltage drop of a IGBT ad a freewheelg dode are gve by

181 Appedx C. Coverter losses 73 V V T ( o) D( o) V V T D + R + R T ( o) T D( o) D (C.3) For the half perod where the curret s postve.e. the terval ω t [ϕ..π+ϕ] of Fgure C. the trasstor T ad the freewheelg dode D are coductg. The duty cycle d T for T ths terval s gve by d T The correspodg duty cycle for D s dc ( t) u uˆ s + + ω (C.4) V V dc ( ω t) uˆ s (C.5) dd dt Vdc The coducto losses for oe IGBT ad freewheelg dode are wrtte P P T cod D cod V V d T ( o) d D( o) T D (C.6) The average losses for oe perod of the output fudametal are foud by tegrato. Note that T ad D are oly coductg whe the output curret s postve.e. the terval ω t [ϕ..π+ϕ]. Ths gves P T cod V π + V 4 T T ˆ + R 8 ˆ + R 3π ˆ T ( o) ˆ T ( o) + uˆ cos V dc ( ϕ) (C.7) ad P D cod V π V 4 D D ˆ + R 8 ˆ + R 3π ˆ D( o) ˆ D( o) uˆ cos V dc ( ϕ ) (C.8)

182 74 Appedx C. Coverter losses For oe half-brdge the coducto losses are twce the losses of a sgle IGBT ad dode.e. P T cod V π + V T T I + R 4 I + R 3π T ( o) T ( o) I I + U cos Vdc ( ϕ ) (C.9) ad P D cod V π V D D I + R 4 I + R 3π D( o) D( o) I I U cos Vdc ( ϕ ) (C.) Note that the coverter output RMS voltage U ad curret I for phase are used the two last expressos. I statoary codtos the RMS sgle le equato U jω LI ELN (C.) apples. By separato of the real ad magary parts ωli cos U ωli s ( ϕ ) E s ( δ ) LN ( ϕ ) E cos( δ ) LN load load (C.) s obtaed. By puttg the load agle equal to the phase lag.e. δ ϕ load (C.3) equvalet to uty power factor for the source or load t s foud that arcta ω ϕ LI (C.4) E LN

183 Appedx C. Coverter losses 75 for verter operato. For rectfer operato the same expresso s vald but wth egatve le curret. The coverter output voltage s gve by ( ω LI ) ELN + U ELN cos( δ load ) + ωli s ( ϕ ) cos( ϕ ) (C.5) E whch meas that the RMS output voltage of the coverter s equal both cases. The phase dsplacemet s also equal but wth opposte sg. Ths s compared to measuremet results of [43] where the losses of a battery charger cosstg of four half-brdges are measured. The fourth half-brdge operates as a step-dow coverter wth the output coected to the batteres va a ductve flter. The losses of the battery sde half-brdge are gve by LN P T V E batt off ( ) o + E V I + R ( ) I + VdcIbatt fsw T batt T o batt (C.6) V V I dc dc for the IGBT ad P Vbatt EDrr ( V I + R ( ) I ) VdcIbatt fsw D D batt D o batt V + dc Vdc (C.7) I for the freewheelg dode. All the half-brdges of the battery charger are Semro SKM5GB3D modules wth approxmate data accordg to Table C.. Table C.: Semro SKM5GB3D data. V T R T(o) E o +E off V D R D(o) E Drr. V 7 mω.5 mws. V.7 mω.9 mws Data vald for: T jucto 5 C V dc 6 V I 4 A R Gate Ω The battery charger operates at V dc 65 V. The put ad output power eglectg the flters are P 5765 W ad P out 558 W. The put ad output power are measured smultaeously wth a four-chael Norma 6 wde bad power aalyzer. The three-phase boost rectfer s coected to a 4 V 5 Hz grd. Cosequetly U33 V. The step dow coverter s coected

184 76 Appedx C. Coverter losses to a battery wth V batt 43 V. The calculated losses equal 59 W whereas the measured are 84 W. Note that the losses of DC l bleeder resstors wth a total resstace of Ω ad the resstors seres wth the LEM LV5P DC bus voltage trasducer wth a resstace of 75 Ω are ot cluded. The total power loss these resstors equals 5 W whch s also equal to the dfferece betwee the calculated ad measured losses. Note that the losses the DC bus capactors are ot cluded the calculato. I [43] the smulated DC l capactor losses for a W hard-swtched battery charger s foud to be approxmately 5 W or.5% of the output power. I ths case ths correspods to approxmately 3 W. Thus the estmated coverter losses equal 87 W.

185 Appedx D Normalsato I ths appedx the ormalsato bases used the thess are gve. Also the mpact o coverter DC bus voltage caused by ubalaced AC sde loadg s vestgated. Ths method ca be appled to select approprate DC l capactors [6]. D. Base system for a sgle coverter Ths secto gves two per ut base systems. The oe used mostly the thess s based o coverter DC sde data. There s however aother based o AC data whch s used for two purposes ths thess amely to calculate approprate le sde flter ductace for VSC based HVDC ad geerator ductace for wd power geerators. Normalsato based o DC sde data C base I base R C V base V dc ref base (D.) P I dc (D.) V dc ref dc ref V R (D.3) P dc ref lp ζ P (D.4) V ω ( δ ) δ 77

186 78 Appedx D. Normalsato τ base ω R base base C base ζ (D.5) ω lp ( δ ) δ ( δ ) δ ωlp (D.6) τ ζ base L base R ω base base V dc ref ζ P ω lp ( δ ) δ (D.7) Normalsato based o AC sde data S base S (D.8) P base S (D.9) V base E ELL (D.) Sbase S I base I 3V 3E base (D.) base base base Vbase Sbase 3Ibase Sbase 3Ibase V X Z (D.) ω (D.3) base ω f L base X (D.4) ω base base D. Coverter data expressed per ut The DC l capactor ca be specfed from the rated power ad the allowed dsturbace for o-symmetrcal loadg [6]. The DC l capactor s selected based o the requremet that the DC l voltage must ot vary wth ampltude hgher tha ±.5V dc for sgle-phase operato at rated AC sde curret. The rated power determes the mmum coverter DC sde equvalet resstace.

187 D. Coverter data expressed per ut 79 Selecto of coverter DC sde capactor Assume that the three-phase coverter s coected to a AC power system wth the grd voltages gve by e e e a b c eˆcos eˆcos eˆcos ( ω t) ( ω t π 3) ( ω t 4π 3) (D.5) Ths gves the power-varat trasformato to the statoary αβ-referece frame accordg to rαβ 3 e eα + jeβ eˆ s ( cos( ω t) + j ( ω t) ) Ths s trasferred to the rotatg dq-referece frame by r e dq j e θ r e αβ ( cosθ jsθ ) ( e + je ) ( eα cosθ + eβ sθ ) + j( eα sθ + eβ cosθ ) ed + jeq α β (D.6) (D.7) If the defto e e d q > (D.8) s used t s foud that θ ω t π (D.9) whch specfes the rotatg coordate system (Fgure A.5). Now t s assumed that the coverter s operatg wth curret flowg oly two phases. Ths ca be the case f for example oe of the AC sde fuses has faled. Ths mples that the curret o the AC sde s wrtte

188 8 Appedx D. Normalsato a b c ˆcos a ( ω t ϕ ) ˆcos ( ω t ϕ ) (D.) I the statoary αβ-coordate system the curret vector s expressed as (power varace) r 3 ˆcos t ( ω t ϕ ) j ˆ ( ω ϕ ) αβ α + jβ cos whch for the rotatg dq-referece system gves dq j r e θ rαβ + j d q (D.) (D.) where d q ˆ ˆ ( s ( ϕ + π 6) + s ( ω t ϕ + π 6) ) ( cos( ϕ + π 6) + cos( ω t ϕ + π 6) ) (D.3) From the expresso above t s foud that f the le-to-le voltage ( ϕ + 6) eab ea eb 3eˆcos π (D.4) s phase wth the correspodg curret.e. f The curret compoets are gve by ϕ π 6 (D.5) The put power s wrtte d q ˆ s ˆ ( ω t + π 3) ( + cos( ω t + π 3) ) (D.6)

189 D. Coverter data expressed per ut 8 3 ˆ p eq q eˆ ( + cos( ω t + π 3) ) 3ELN I( + cos( ωt + π 3) ) (D.7) If the curret the a- ad b-phases has a magtude correspodg to rated codtos the power s thus wrtte ( + cos( ω + 3) ) p E t LL I π (D.8) Note that for rated codtos wth equal curret all three phases the power s wrtte 3 3 ˆ ˆ I (D.9) P eq q e 3ELL For the case wth the c-phase curret equal to zero the costat term of the put power s trasferred to the DC etwor. The tme depedet term of the power results a oscllato the DC bus voltage at least close to the DC bus capactor of the coverter drawg a usymmetrcal curret. The power fed to the DC l capactor s wrtte dvcdc pcdc vcdc Cdc vcdc Cdc 3ELN I cos( ω t + π 3) (D.3) dt Assumg a DC bus voltage equal to gves ( ω + 3) vcdc Vdc + vcdc s t π (D.3) p Cdc v Cdc 3E C LN dc dv dt I cos Cdc ω C ( ω t + π 3) dc V dc v Cdc cos ( ω t + π 3) (D.3) For a a- ad b-phase coverter curret ad a grd voltage correspodg to rated codtos a crtero gvg the maxmum DC bus voltage varato ca be formulated accordg to C dc P 3 ωv dc Vdcmax (D.33)

190 8 Appedx D. Normalsato whch s rewrtte as C dc 3 V ω V C base 3 V V dc dc dc dc max max P V dc 3 V ω V dc dc max Z base (D.34) I p.u. ths s thus expressed as C dc( pu) (D.35) 3 ( vdc ) max For a gve coverter the equvalet resstace for a certa load s wrtte R eq dc V P dc V P dc v p Z base r eq (D.36) Note that ths quatty s ot costat sce t depeds o the DC bus voltage whch s a dyamcal state ad the output power whch s a put sgal. The tme costat ths correspods to s gve by req τ dc( pu) (D.37) 3 dc ( v ) max Note that the tme costat s load depedet whch mples that t must be treated wth care. For rated codtos s vald. τ dc( pu) (D.38) 3 ( vdc ) max

191 Appedx E Nomeclature Abbrevatos CM Commo mode CSC Curret source coverter DAB Double actve brdge DM Dfferetal mode DPS Dstrbuted power system EMC Electro magetc compatblty EMI Electro magetc terferece ESR Equvalet seres resstace HVDC Hgh voltage drect curret IGBT Isulated gate bpolar trasstor LVDC Low voltage drect curret MVDC Medum voltage drect curret PEBB Power electroc buldg bloc PFC Power factor corrector PMSM Permaet-maget sychroous mache SMPS Swtch mode power supply UPS Uteruptable power supply VSC Voltage source coverter ZVS Zero voltage swtchg ZVT Zero voltage trasto 83

192 84 Appedx E. Nomeclature Symbols a b c Coverter phase order C base Per ut base capactace C cable DC sde capactace of cable segmet C dc DC sde capactace C fac AC sde harmoc flter capactace of a HVDC coverter C fdc DC sde dfferetal mode flter capactace of a HVDC coverter C fvar AC sde shut reactve power compesato capactace of a HVDC coverter C f AC sde shut harmoc flter capactace for VSC based HVDC coverters C f DC sde dfferetal mode flter capactace for VSC based HVDC coverters C f3 DC sde commo mode flter capactace for VSC based HVDC coverters C p Groudg capactors C r DC sde capactace of the recevg ed coverter C s DC sde capactace of the sedg ed coverter d Istataeous duty cycle or relatve delay betwee DAB coverters d D Istataeous duty cycle for the lower freewheelg dode of the half-brdge coected to phase d T Istataeous duty cycle for the upper trasstor of the halfbrdge coected to phase E LL AC grd le-to-le RMS voltage geeral E LN AC grd le-to-eutral RMS voltage geeral E Rated AC grd le-to-le voltage E Drr Freewheelg dode reverse recovery eergy loss E off IGBT tur-off eergy loss E o IGBT tur-o eergy loss e LL Istataeous or p.u. AC grd le-to-le voltage Istataeous or p.u. AC grd le-to-eutral voltage e LN

193 Appedx E. Nomeclature 85 e d e q e α e β f f f sw f G cl (s) H I base I Cdc (s) I Cdcref (s) I dc I dc I dcrefext I I dcdff I dcdff I le I I r I r (s) I s I s (s) I Trp I t Cdc Cdcref Cp Istataeous coverter AC grd voltage the d-drecto Istataeous coverter AC grd voltage the q-drecto Istataeous coverter AC grd voltage the α-drecto Istataeous coverter AC grd voltage the β-drecto Frequecy geeral Rated AC grd or mache frequecy Swtchg frequecy Fudametal frequecy Voltage closed loop trasfer fucto V s /V dcref Wd power aggregate erta costat Per ut base curret Laplace trasform of the total DC bus capactor curret Laplace trasform of DC bus capactor curret referece from DC bus voltage cotroller Steady state DC sde curret Nomal steady state DC sde curret Exteral DC sde curret referece Coverter AC sde RMS curret for phase Itegral of dfferetal currets for groud fault detecto Le sde RMS curret compoet of harmoc of order Nomal AC sde RMS curret Steady state DC sde curret of the recevg ed Laplace trasform of DC sde curret of the recevg ed Steady state DC sde curret of the sedg ed Laplace trasform of DC sde curret of the sedg ed Trp level for tegrated dfferetal fault currets Fuse curret-tme wthstadg capablty Istataeous total DC bus capactor curret Istataeous DC bus capactor curret referece from DC bus voltage cotroller Groudg capactor curret

194 86 Appedx E. Nomeclature D d dc dcap dca dcbp dcb dcdff dcdff dcdffa dcdffb Fault q qdcref qvref q ref r s T T α β J m K K fw K ptch Istataeous dode curret Istataeous coverter AC sde curret the d-drecto Istataeous DC sde curret Istataeous curret the postve ral of the A-terface of a cable ode Istataeous curret the egatve ral of the A-terface of a cable ode Istataeous curret the postve ral of the B-terface of a cable ode Istataeous curret the egatve ral of the B-terface of a cable ode Dfferetal currets for groud fault detecto Dfferetal currets of the A- ad B-terfaces of cable ode I Fault curret Istataeous coverter AC sde curret for phase Istataeous coverter AC sde curret the q-drecto Istataeous DC bus curret referece from DC bus voltage cotroller ad trasferred to AC sde dq-refereces Istataeous rectfer curret referece based o verter output power for a VSC based HVDC trasmsso system Istataeous AC sde curret referece the q-drecto Istataeous DC sde curret of the recevg ed Istataeous DC sde curret of the sedg ed Istataeous trasstor curret Istataeous prmary curret of DAB trasformer Istataeous DAB coverter currets Istataeous coverter AC sde curret the α-drecto Istataeous coverter AC sde curret the β-drecto Wd power aggregate momet of erta Cotroller ga geeral Feld weaeg cotroller ga Ptch agle cotroller ga

195 Appedx E. Nomeclature 87 K wd K ω L L base L cable L cf L dc L d L Fault L f L f L f3 L cable L le L s L q l cable m a m f P P base P D P ge P coverter P s P s (s) Proportoalty costat betwee wd speed ad power Speed droop ga Curret cotroller ga factor or fault curret factor AC sd e flter ductace (used oly Appedxes) Per ut base ductace DC sde cable ductace DC sde cable ductace the fault curret path DC sde ductace of physcal ductor PMSM stator ductace d-drecto Fault ductace AC sde shut harmoc flter ductace for VSC based HVDC coverters DC sde dfferetal mode flter ductace for VSC based HVDC coverters DC sde commo mode flter ductace for VSC based HVDC coverters DC sde ductace of cable segmet AC le ductace Trasformer wdg self-ductace PMSM stator ductace q-drecto DC sde cable ductace (p.u.) Modulato dex Pulse umber Number of cable odes or omal codtos (f dex) Steady state or Laplace trasform of actve power geeral Per ut base actve power Average dode power losses Geerator power of wd power aggregate Rated power of a coverter Steady state power of the sedg ed Laplace trasform of the sedg ed power

196 88 Appedx E. Nomeclature P Nomal actve power P ptch Power lost due to ptch agle cotrol P r Steady state power of the recevg ed P refext Exteral power referece P r (s) Laplace trasform of the recevg ed power P T Average IGBT power losses P wd Avalable wd power P Ital power p(s) Desred characterstc polyomal p Cdc Istataeous power suppled to the total DC bus capactace p dc Istataeous DC sde power p verter Istataeous output power of the coverter operated as verter for a VSC based HVDC trasmsso system p r Per ut DC sde curret of the recevg ed p s Per ut DC sde curret of the sedg ed p -p Istataeous power of DC bus coverters Q Reactve power geeral R S T AC le phase order R AC sde flter resstace (used oly Appedxes) R base Per ut base resstace R cable DC sde resstace of cable segmet R cf DC sde cable resstace the fault curret path R dc DC sde resstace of physcal resstor R D(o) O-state resstace of freewheelg dodes R droop Equvalet droop resstace R ESR Equvalet seres resstace of a capactor R eq Equvalet DC sde resstace of load coverter R Fault Fault resstace R Faulteq Equvalet fault resstace R Gate Resstace of IGBT gate resstor AC le resstace of cludg flter ductor wdg resstace R le

197 Appedx E. Nomeclature 89 R R r R s R sc R T(o) r cable r eq r r S S base S s T T fw T ge T T s T sw T ptch T wd t t detect U U u u CM u DM u d u Equvalet DC sde resstace of a coverter at omal load Equvalet resstace of the recevg ed coverter PMSM stator wdg resstace Trasformer short crcut resstace O-state resstace of IGBTs DC sde cable resstace (p.u.) Equvalet resstace of load coverter (p.u.) Equvalet resstace of the recevg ed coverter (p.u.) Steady state apparet power geeral Per ut base apparet power Nomal apparet power Swtch state Perod tme correspodg to the fudametal frequecy Feld weaeg cotroller tegrato tme costat Geerator mechacal torque for wd power aggregate Cotroller tegrato tme costat geeral Samplg terval Swtchg terval Mechacal torque lost due to ptch agle cotrol Avalable mechacal torque for wd power aggregate Tme geeral Tme requred for fault detecto Coverter AC sde RMS le-to-eutral voltage Coverter AC sde RMS le-to-eutral (vrtual eutral) voltage for phase Istataeous coverter AC sde le-to-eutral voltage Coverter AC sde commo mode voltage Coverter AC sde dfferetal mode voltage Istataeous coverter AC sde voltage the d-drecto Istataeous coverter AC sde voltage for phase

198 9 Appedx E. Nomeclature u j u ref u z u zref u q u z u α u β V base V D V dc V dc (s) V dcref V dcref V dcrefhv V dcreflv V r V r (s) V s V s (s) V T v Cp v cable v dc v HV v T v T Istataeous coverter AC sde le-to-le voltage betwee phases ad j Istataeous coverter AC sde referece voltage for phase Istataeous coverter AC sde le-to-vrtual eutral voltage the case a zero-sequece sgal s added for phase Istataeous coverter AC sde referece voltage wth zerosequece sgal added for phase Istataeous coverter AC sde voltage the q-drecto Istataeous coverter AC sde zero-sequece voltage Istataeous coverter AC sde voltage the α-drecto Istataeous coverter AC sde voltage the β-drecto Per ut base voltage O-state freewheelg dode forward voltage for zero curret Steady state DC sde voltage Laplace trasform of DC sde voltage geeral DC sde referece voltage Ital DC sde referece voltage Hgh voltage sde DC referece voltage Low voltage sde DC referece voltage Steady state DC sde voltage of the recevg ed coverter Laplace trasform of DC sde voltage of the recevg ed coverter Steady state DC sde voltage of the sedg ed coverter Laplace trasform of DC sde voltage of the sedg ed coverter O-state IGBT forward voltage for curret equal to zero Groudg capactor voltages Istataeous cable voltage of HVDC coverter geeral Istataeous DC sde voltage of coverters geeral Istataeous trasmsso bus voltage at a coverter Istataeous prmary ad secodary sde voltages of a DAB trasformer

199 Appedx E. Nomeclature 9 v wd v -v X base x le Z Z base Z cable Z L Z r Z sc z p Wd speed Istataeous coverter DC sde voltage Per ut base reactace Le flter reactace (p.u.) Impedace geeral Per ut base mpedace Cable mpedace Iductve flter mpedace Equvalet mpedace of the recevg ed coverter Short crcut mpedace PMSM umber of pole pars Gree symbols α Thyrstor coverter cotrol agle α d Weghtg factor for the feld weaeg cotroller ga α Coverter AC sde curret rpple the α-drecto β Coverter AC sde curret rpple the β-drecto Coverter DC bus voltage varato V dc V dcref v dc ω el ω m δ δ r δ s δ load γ γ γ ϕ λ λ DC bus voltage droop referece offset Coverter DC bus voltage varato (p.u.) PMSM electrcal agular frequecy varato PMSM mechacal agular frequecy varato Voltage droop geeral Voltage droop of the recevg ed Voltage droop of the sedg ed AC system load agle Fault detector forgettg factor PMSM speed estmator adaptato gas AC system phase lag betwee voltage ad curret Egevalues for both closed loop feld weaeg ad fault currets

200 9 Appedx E. Nomeclature θ ρ ρ -ρ 4 ρ s τ base τ cable τ cable(pu) τ dc(pu) τ coverter τ system τ ptch τ r τ r(pu) ω base ω el ω f ω lp ω lpd ω m ω mref ω ω o ω o(pu) ω Ψ m ζ ζ o Rotatoal agle betwee the rotatg (dq) ad the fxed (αβ) referece systems PMSM speed estmator badwdth Closed loop poles of two-coverter systems cludg cable PMSM speed cotroller badwdth Per ut base tme costat Tme costat of the cable Tme costat of the cable (p.u.) Equvalet tme costat of coverter DC sde (p.u.) Nomal equvalet tme costat of coverter Nomal equvalet tme costat of coverter system Equvalet tme costat of ptch agle cotroller Equvalet tme costat of the recevg ed coverter Equvalet p.u. tme costat of the recevg ed coverter Per ut base agular frequecy PMSM electrcal agular frequecy PMSM low-pass fltered electrcal agular frequecy DC bus low-pass flter brea-over frequecy Feld weaeg low-pass flter brea-over frequecy PMSM mechacal agular frequecy PMSM mechacal agular frequecy referece Closed loop omal characterstc frequecy of DC bus voltage cotrol Characterstc agular frequecy of the sum of the cable ad the equvalet recevg ed mpedace Characterstc p.u. agular frequecy of the sum of the cable ad the equvalet recevg ed mpedace Fudametal agular frequecy of AC system PMSM magetsg flux-lage Closed loop omal dampg of DC bus voltage cotrol Dampg of the sum of the cable ad the equvalet recevg ed mpedace