PCI Express Gen 2 Deep Dive on Power Architecture Based Products
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1 June, 2010 PCI Express Gen 2 Deep Dive on Power Architecture Based Products FTF-NET-F0685 Richard Nie Sr. Systems and Application Engineer, NMG, NSD and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.
2 Agenda Legacy PCI and PCI Express Technology Overview PCI Express Gen2 vs. Gen1 Highlights PCI Express Gen2 on Freescale P4080 and P4040 and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 2
3 The Legacy PCI Bus Quick Overview Parallel shared bus 32-/64-bit multiplexed bus Defined in early 1990s (Rev.2.0 Spec released in 1993) CPU Local Bus Bridge/ Memory Ctrl Memory PCI Bus 0 Bridge Periph Periph PCI Bus 1 Periph Periph and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 3
4 PCI Bus Commands C/BE#[3:0] PCI Bus Command 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0110 Memory Read 0111 Memory Write 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1101 Dual Address Cycle 1110 Memory Read Line 1111 Memory Write and Invalidate and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 4
5 PCI Read Transaction and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 5
6 PCI Write Transaction and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 6
7 PCI Bus Transaction Termination Master-initiated Completion normal termination Timeout controlled by latency timer Master-abort no target device claimed the transaction Target-initiated Disconnect target is temporarily unable to continue the transaction With or without data transfer Retry target is temporarily unable to begin the transaction Target-abort target will never be able to service the transaction Fatal error Target does not want the transaction retried and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 7
8 Limitation of PCI Architecture Slow device arbitration consumed bandwidth due to wait state insertion Transfer size unknown Delayed transactions are inefficient Retries use up bus time No transfer count Bus master doesn t identify itself Interrupt handling is inefficient Since INT# is wired OR together, it takes quite a lot of time to figure out which device caused interrupt Slow clock speed The reflection nature makes it slow, reaching the ceiling limit of its bandwidth To increase performance, increase speed to 66 MHz, which lowers load to 1 to 2 slots If you want to connect more devices, you would see more and more hub-link interface (most likely 64-bit width) on the system... causing board routing: a headache. Detected error results in system shutdown and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 8
9 PCI Express Architecture Overview CPU RCRB Memory Bus# 0 Virtual PCI Bridge Virtual PCI Bridge Virtual PCI Bridge Bus# 1 PCIe Root Complex (RC) Bus# 6 Bus# 7 PCIe Endpoint Bus# 3 Bus# 2 Switch PCIe Endpoint PCIe-PCI/PCI-X Bridge Bus# 8 Bus# 4 Bus# 5 PCIe Endpoint PCIe Legacy Endpoint and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 9
10 PCI Express Topology-Related Terminology Root Complex Device Downstream Port Upstream Port Links Switch Downstream Port Endpoint Endpoint Upstream Port Endpoint and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 10
11 PCI Express Physical Layer Terminology Link Collection of two ports and their interconnecting lanes Upstream Device Lane TX0 P N RX0 P N TXn P N RXn P N Downstream Port A set of differential signal pairs: one pair for Tx and another for Rx. Lane 0 Lane n Port Link Physically, a group of transmitters and receivers located on the same chip that define a link Logically, an interface between a component and a PCI Express Link Channel (P-N Pair) P N RX0 P N TX0 Downstream Device P N P N RXn TXn Upstream Port x1, x2, x4, x8, x16,.. xn (Link) A by-n link is composed of N lanes and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 11
12 PCI Express Layered Architecture (Software and Hardware) Config/OS PCI PnP Model (init, enum, config) No OS Impact Software/Driver PCI Software/Driver Model Transaction Packet-based Protocol Data Link Data Integrity Physical Point-to-point, serial, differential, hot-plug, configurable width, inter-op form factors Future speeds and encoding techniques only impact the physical layer and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 12
13 PCI Express Data Transmission Model Point-to-point connection Serial bus significantly reduces number of pins requires only 4 pins for a x1 link Scalable: x1, x2, x4, x8, x16, x32 Dual simplex connection 2.5 Gbits/s per direction (Gen 1) Packet based transaction protocol Link Width x1 x2 x4 x8 x12 x16 x32 Aggregate Raw Bandwidth (Gbits/sec) - Pair(s) of lane (Rx & Tx) Packet PCI Express RC Link (x1, x2, x4, x8, x12, x16, or x32) PCI Express EP Packet and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 13
14 PCI Express Architecture Highlights Extension of PCI architecture for PCs and servers Maintains BIOS-level compatibility with PCI Load-store architecture bytes maximum payload size Layered protocol divided into three layers Transaction (TL) Fulfill the data transaction goal of many types: (Memory, configure, I/O) read/write Data link (DLL) Ensures data integrity with the ack/nack, retry, flow control DLLPs Physical (PL) Establish and maintain the link and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 14
15 PCI Express Architecture Highlights (Cont.) Serial differential interface 2.5 Gbits/sec per lane (Gen 1) Scalable width: x1, x2, x4, x8, x12, x16, x32 Embedded clocking; 8B/10B encoding Lane reversal and polarity inversion New features over PCI Message transactions Configuration address space extended from 256B to 4KB Improved error handling and data transfer robustness (LCRC, ECRC) Power management and hot plug/swap support QoS support and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 15
16 Transaction Layer Highlights Packet-based split transaction protocol Provides R/W logical transactions to software 4 basic transaction types: memory, I/O, configuration and message 32-bit and 64-bit memory addressing Three routing methods Address routing (memory and I/O) ID routing (configuration) Implicit routing (messages) Transactions are carried by Transaction Layer Packets (TLPs) Root Complex or Switch Ack Req D DLLP FC Update DLLP Req 4 TLP Req C TLP Ack Req C DLLP Ack Req 3 DLLP Req 3 TLP Req D TLP FC Update DLLP Ack Req 4 DLLP End point and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 16
17 PCI Express Transaction Types Transaction Completion Request Type Request TLP Non-Posted or Posted Required Packet Type Memory Read MRd Non-Posted Yes CplD, Cpl (error) Memory Write MWr Posted NO Memory Read Lock MRdLk Non-Posted Yes CplD, Cpl (error) IO Read IORd Non-Posted Yes CplD, Cpl (error) IO Write IOWr Non-Posted Yes Cpl Configuration Read CfgRd0, CfgRd1 Non-Posted Yes CplD, Cpl (error) Configuration Write CfgWr0, CfgWr1 Message w/o Data Msg Posted Message w/data MsgD Posted Non-Posted Yes Cpl and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 17
18 PCI Express TLP (Transaction Layer Packet) Assembly Data to be transferred comes from device s Internal HW or SW Serial bit transmit direction Framing (Start) Sequencer Number Header Data ECRC LCRC Framing (End) 1B 2B 3-4 DW DW 1DW 1DW 1B Created by Transaction Layer Appended by Data Link Layer Appended by Physical Layer and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 18
19 Serial bit transmit direction toward receiver Data to be received will be sent to device s Internal HW or SW PCI Express TLP Disassembly Framing (Start) Sequencer Number Header Data ECRC LCRC Framing (End) Stripped by Transaction Layer Stripped by Data Link Layer Stripped by Physical Layer and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 19
20 PCI Express TLP Generic Header Fields Transaction Layer Packet (TLP) Framing (Start) Sequencer Number Header Data Digest LCRC Framing (End) Byte 0 R Fmt Type R TC R T D E P Attr R Length DW0 Byte 4 (Fields in bytes 4 7 vary with TLP type) Last DW BE 1 st DW BE DW1 Byte 8 (Fields in bytes 8 11 vary with TLP type) DW2 Byte 12 (Fields in bytes vary with TLP type)* DW3 * Only applicable for 4 DW TLP headers and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 20
21 PCI Express TLP Fmt[1:0] and Type Encoding and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 21
22 Gen2 base spec was publicly released on Jan. 15, 2007 Higher speed (5.0 GT/s) supported: Selectable de-emphasis levels Selectable transmitter voltage swing Runtime bandwidth changes Power savings and flexible bandwidth Software notification of changes IO virtualization support Access control services Function level reset Other new features Completion timeout control Modified compliance pattern for testing PCI Express Gen2 vs. Gen1 and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 22
23 PCI Express Gen2 vs. Gen1 (continued) Improved performance, reduced pin count Bandwidth based on 8b/10b encoding, aggregate bandwidth will be: Gen1: 0.5 GB/s per lane Gen2: 1.0 GB/s per lane and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 23
24 Brief De-Emphasis Review Higher frequency means greater sensitivity to jitter De-emphasis helps by reducing transmitter power during repeated bits Goals: Reduced data-dependent jitter Alleviate ISI (inter-symbol interference) and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 24
25 ISI (Inter-Symbol Interference) and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 25
26 Selectable De-Emphasis Gen1 de-emphasis was always -3.5dB Gen2 de-emphasis is selectable: At 2.5 GT/s: -3.5 db At 5.0 GT/s: -6.0 db (-3.5 db optional) and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 26
27 PCIe Gen2 Support on Freescale QorIQ Products P4080 and P4040 and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 27
28 P4080 and P4040 PCI Express Gen2 Feature Highlights Three PCI express controllers: Support both 2.5 GT/s and 5.0 GT/s speed Support up to x4 5.0 GT/s maximum bandwidth for each controller 5.0 GT/s per lane x4 lanes = 20 GT/s per direction for each controller Initial flow control credit advertisement increased for PH and PD Now up to 6 posted credits (header and corresponding data credits) for inbound posted transactions, when SRIO is not used Other major changes: Only one change in transaction layer good news for software folks! Few changes in PCIe controller registers Some change in POR SerDes and clock ratio setup Major change in electrical area challenge for board guys! and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 28
29 Register Change #1: PEX_CONFIG 2-bit Fields Added PCI Express Configuration Register (PEX_CONFIG) Posted credit 100: 4 posted credits (default). 110: 6 posted credits, only if SRIO is not used! Good for Gen1 x8 or Gen2 x4 Outbound transaction address checking against base/limit register setup 0 : Default, same as Gen1 parts, no checking. 1 : Enable checking. If no hit flag error! and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 29
30 Register Change #2: Dedicated MSI Inbound Window in RC Add a dedicated inbound window for MSI in RC Mode Added 4 registers: PEXMSIITAR, PEXMSIIWBAR, PEXMSIIWBEAR, PEXMSIIWAR Old usage model MSI is handled by one of the P4080 core Translation Address must be configured to point to one of the three registers (MSIIRA, MSIIRB, MSIIRC) in MPIC New usage model MSI can be handled by other device Set the translation address and target interface to route inbound MSI to a device connected to one of the SRIO port or a different PCIe port on P4080 and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 30
31 Register Change #3: PCIe Capabilities Register PCI Express Capabilities Register The Version bit field = 0010b = 0x2h this is a PCIe Gen2 device But, this doesn t necessary mean it supports 5 GT/s Gen2 speed Check the Link Capabilities Register to confirm! and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 31
32 Register Change #4: PCIe Link Capabilities Register PCI Express Link Capabilities Register The MAX_LINK_SP bit field = 0010b = 0x2h Yes! This PCIe Gen2 device supports both 2.5 GT/s and 5 GT/s speed But, this doesn t necessary mean it actually operates at 5 GT/s speed Check the Link Status Register to confirm! Link bandwidth notification capable (LBWN) LBWN=1 indicates P4080 supports Link Bandwidth Notification status and interrupt mechanisms and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 32
33 Register Change #5: PCIe Link Control Register PCI Express Link Control Register Hardware autonomous width disable (HWAWD) When set, disables HW from changing the link width for reasons other than attempting to correct unreliable link operation by reducing link width Link bandwidth management interrupt enable (LBMIE) Only applicable for RC or switch downstream port When set, enables interrupt generation if Link Status Register [LBMS] is set Link autonomous bandwidth interrupt enable (LABIE) Only applicable for RC or Switch downstream port When set, enables interrupt generation if Link Status Register [LABS] is set and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 33
34 PCI Express Link Status Register Negotiated link speed (LINK_SP) 0001 : Default, 2.5 GT/s Register Change #6: PCIe Link Status Register 0010 : 5.0 GT/s (final proof that the link is operating at Gen2 speed) Negotiated link width (NEG_LINK_W) Link bandwidth management status (LBMS) for RC/Switch downstream port Set by hardware to indicate either of following occurred on downstream port without transitioning through DL_Down status: A link training has completed following a write of 1b to Retrain Link bit HW has changed link speed or width to attempt to correct unreliable link Link autonomous bandwidth status (LABS) for RC/Switch downstream port Set by HW to indicate that HW has autonomously changed link speed or width on downstream port without transitioning through DL_Down status, for reasons other than attempt to correct unreliable link operation and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 34
35 Register Change #7: PCIe Device Capabilities 2 Register PCI Express Device Capabilities 2 Register (Read-Only) Completion timeout range supported (CPL_TO_RS) Value reflects completion timeout programmability supported by this device Purpose Allows system software to modify completion timeout value Completion timeout disable supported (CPL_TO_DS) 1: indicates this device supports completion timeout disabling mechanism and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 35
36 Register Change #8: PCIe Device Control 2 Register PCI Express Device Control 2 Register Completion timeout value (CPL_TO_VAL) Completion timeout disable (CPL_TOD) Purpose: Allows software to dynamically disable or enable completion timeout detection mechanism 0 : Default, Completion timeout detection is enabled 1 : Completion timeout detection is disabled and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 36
37 PCI Express Link Control 2 Register Target link speed (T_LS) Register Change #9: PCIe Link Control 2 Register Operation mode: used to set downstream port s link operation speed upper limit Compliance mode: used to set both upstream and downstream ports target compliance mode speed when software uses EC to force a link into compliance mode Enter compliance (EC) Software can set this bit to force a link to enter compliance mode at the speed indicated in T_LS Hardware autonomous speed disable (HWASD) When set, disables HW from changing link speed for device specific reason other than attempting to correct unreliable link operation by reducing link speed Selectable de-emphasis (SDE) applicable for downstream port of RC/Switch Selects downstream port s de-emphasis level when link is operating at 5 GT/s 1 : -3.5 db 0 : -6 db and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 37
38 Register Change #10: PCIe Link Status 2 Register PCI Express Link Status 2 Register (Read-Only) Current de-emphasis level (DE_LVL) Applicable only when the link is operating at 5 GT/s 1 : -3.5 db 0 : -6 db and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 38
39 P4080 PCI Express Major Steps for Bring-up Brief POR pin configuration Most POR configuration is stored in RCW now POR configuration pins to be configured: RCW source, DRAM type, flash ECC Configure all other proper POR values in RCW HOST_AGT_B1, HOST_AGT_B2 set PCIe RC or EP mode for Bank 1 & 2 SRDS_PRTCL select SerDes lane/protocol usage based on allowed mapping SRDS_RATIO_Bn select SerDes clock ratio for Bank 1 & 2 SRDS_DIV_Bn select SerDes PLL clock divider for Bank 1 & 2 SRDS_EN set to 1 to enable SerDes and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 39
40 P4080 PCI Express Major Steps for Bring-up (continue) Configure all SerDes registers in RCW s PBI section Please only touch those that really need to be changed and leave as much in default as possible! SerDes registers you might need to touch: SRDSBnPLLCR0 selects ref. CLK frequency other than 100 MHz SRDSGR0 selects the DDR supply voltage that the SerDes uses Other registers called out by the workaround section of the errata document Configure LAW and AU windows P4080 offers 32 LAWs Each PCIe controller offers: 4 AU outbound windows in addition to OW#0, and 3 AU inbound windows in addition to the dedicated one for MSI Configure major registers required for the PCIe controller Both configuration space and memory-mapped space and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 40
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