UM1653 User manual. STM32 Advanced NAND Flash Driver for SLC NAND. Introduction

Transcription

1 UM653 User manual STM32 Advanced NAND Flash Driver for SLC NAND Introduction The NAND driver library for STM32 is a generic library from which STM32 can access NAND with advanced features like garbage collection, wear leveling, bad block management, ECC checking etc. The NAND Flash driver supports dynamic NAND Flash detection based on the Device ID. The driver automatically detects the mounted SLC NAND Flash and works accordingly (described in more detail in Section 2.8). This solution runs on the STM32F, STM32F2 & STM32F4 series of microcontrollers using the FSMC interface. The board can run in two modes: USB Mass Storage mode and Standalone mode. In USB Mass Storage mode, the NAND Flash works as USB mass storage media. In Standalone mode, the.bmp images stored in the pics folder of the root directory are read using FatFS file system, and displayed on the onboard TFT LCD. Six evaluation boards are available for this SLC NAND FLASH Driver: STEVAL_CCM006V: USB mass storage mode demo using STM32F03ZET6 STEVAL_CCM006V2: Standalone mode demo using STM32F03ZET6 STEVAL_CCM007V: USB Mass Storage mode Demo using STM32F205ZET6 STEVAL_CCM007V2: Standalone mode Demo using STM32F205ZET6 STEVAL_CCM008V: USB Mass Storage mode Demo using STM32F405ZGT6 STEVAL_CCM008V2: Standalone mode Demo using STM32F405ZGT6 NAND is a non-volatile Flash memory device where address lines are multiplexed with data input/output and commands input. The NAND driver library has the following features:. Supports both FAT file system and USB MSC device. 2. Supports SLC NAND with page size of 52 Bytes & 2 KBytes. 3. Garbage collection. 4. Wear leveling. 5. Bad block management. 6. ECC check. This document applies to the following microcontrollers: STM32L5xD, STM32L52xD, STM32L562xD. STM32F405/45, STM32F407/47, STM32F427/437, STM32F429/439 lines. STM32F2 Series. STM32F03xC, STM32F03xD and STM32F03xE, STM32F03xF, STM32F03xG, STM32F0xC, STM32F0xD and STM32F0xE, STM32F0xF, STM32F0xG, STM32F00xC, STM32F00xD, STM32F00xE. November 203 DocID Rev /45

2 Contents UM653 Contents STM32 NAND driver blocks STM32 USB peripheral USB mass storage FSMC NAND architecture NAND pin mapping NAND driver firmware modules Garbage collection Wear leveling ECC Hamming code for NAND Flash Error detection and correction Bad block management Look up table (LUT) File system NAND driver files nand_drv.c, nand_drv.h functions fsmc_nand_if.c, fsmc_nand_if.h functions Supported NAND Flash NAND evaluation board Working with evaluation boards Running in USB Mass Storage mode (STEVAL-CCM006/7/8V) Running in Standalone mode (STEVAL-CCM006/7/8V2) Schematics NAND evaluation board images Revision history /45 DocID Rev

3 UM653 List of tables List of tables Table. Spare area format for small NAND Flash Table 2. Spare area format for large NAND Flash Table 3. File system interface functions Table 4. NAND_Init Table 5. NAND_Write Table 6. NAND_Read Table 7. NAND_WriteECC Table 8. NAND_PostWriteECC Table 9. NAND_CleanLUT Table 0. NAND_WearLeveling Table. SBLK_NAND_WearLeveling Table 2. LBLK_NAND_WearLeveling Table 3. NAND_GetFreeBlock Table 4. SBLK_NAND_ReadSpareArea Table 5. LBLK_NAND_ReadSpareArea Table 6. WriteSpareArea Table 7. NAND_Copy Table 8. NAND_CopyBack Table 9. NAND_Format Table 20. NAND_PostWrite Table 2. SBLK_NAND_PostWrite Table 22. LBLK_NAND_PostWrite Table 23. NAND_GarbageCollection Table 24. NAND_UpdateWearLevelCounter Table 25. NAND_ConvertPhyAddress Table 26. NAND_BuildLUT Table 27. SBLK_NAND_BuildLUT Table 28. LBLK_NAND_BuildLUT Table 29. GetParity Table 30. Swap Table 3. WritePage Table 32. SBLK_NAND_WritePage Table 33. LBLK_NAND_WritePage Table 34. ReadPage Table 35. SBLK_NAND_ReadPage Table 36. LBLK_NAND_ReadPage Table 37. BitCount Table 38. FSMC_SelectNANDType Table 39. FSMC_NAND_NON_ONFI_Compliance Table 40. FSMC_NAND_Init Table 4. FSMC_NAND_ReadID Table 42. FSMC_NAND_WriteSmallPage Table 43. FSMC_NAND_ReadSmallPage Table 44. FSMC_NAND_WriteSpareArea Table 45. FSMC_NAND_ReadSpareArea Table 46. FSMC_NAND_EraseBlock Table 47. FSMC_NAND_Reset Table 48. FSMC_NAND_GetStatus DocID Rev 3/45 4

4 List of tables UM653 Table 49. FSMC_SBLK_NAND_CopyBack Table 50. FSMC_LBLK_NAND_CopyBack Table 5. FSMC_NAND_ReadStatus Table 52. FSMC_NAND_AddressIncrement Table 53. FSMC_NAND_ONFI_Compliance Table 54. FSMC_SBLK_NAND_SendAddress Table 55. FSMC_LBLK_NAND_SendAddress Table 56. Supported NAND Flash Table 57. NAND Flash driver file code size Table 58. Document revision history /45 DocID Rev

5 UM653 List of figures List of figures Figure. Application architecture Figure 2. BOT protocol architecture Figure 3. NAND block architecture Figure 4. Flow of wear leveling mechanism for STEVAL-CCM006V Figure 5. Flow of wear leveling mechanism for STEVAL-CCM007V/ 008V Figure 6. Example of decomposition of a data packet Figure 7. Flow chart for error detection and correction Figure 8. Flow chart for bad block management Figure 9. Flow chart for File System Figure 0. Evaluation board: top side Figure. Evaluation board: bottom side Figure 2. Demo running in Standalone mode Figure 3. Microcontroller schematic Figure 4. USB Full Speed schematic Figure 5. USB High Speed schematic Figure 6. Touch Screen schematic Figure 7. TFT Connector schematic Figure 8. Power schematic Figure 9. NAND Flash schematic Figure 20. NAND Flash Signals schematic Figure 2. JTAG schematic Figure 22. Top side of PCB Figure 23. Bottom side of PCB DocID Rev 5/45 5

6 STM32 NAND driver blocks UM653 STM32 NAND driver blocks This document describes how to connect a NAND Flash device to an STM32 family microcontroller and communicate using FSMC. NAND driver library for STM32 is a generic library where STM32 can access NAND with some advanced features like garbage collection, wear leveling, bad block management, ECC checking etc. The library supports both FAT file system and USB MSC device. Figure. Application architecture STM32 Lib File System Flash translation layer FTL Interface Garbage collection Wear Leveling Hardware Adaption Layer LLD ECC BBM ECC: Error correction code BBM: Bad block management LLD: Low level driver NAND Flash Device MS3325V. STM32 USB peripheral The STM32F embeds a USB peripheral that supports USB full-speed and high speed. The development of Endpoint and support suspend / resume are configured by software. The USB device provides a connection between the host and the function implemented by the microcontroller. Data transfer between the host and the memory system is through a dedicated packet buffer memory accessed directly from the USB device. The size of buffer memory is dependent on the number of endpoints used and the maximum packet size. This dedicated memory is 52 bytes. 6/45 DocID Rev

7 UM653 STM32 NAND driver blocks.2 USB mass storage The USB device is provided to the host as a particular class, which determines how the host cross reacts with the embedded system. In our case, the USB device must appear in the driver as a Mass Storage Class USB, which defines that SCSI commands will be used with the protocol bulk-only transport (BOT). Bulk-only-transport (BOT) A general BOT transaction is based on a simple basic state machine. It begins with ready state (idle state) and if a CBW is received from the host three cases can be managed: DATA-OUT-STAGE: when direction flag is set to 0, Device shall prepare itself to receive an amount of data indicated in dcbwdatatransferlength in the CBW block. At the end of data transfer a CSW is returned with the remaining data length and the STATUS field. DATA-IN-STAGE: when direction flag is set to, Device shall prepare itself to send an amount of data indicated in dcbwdatatransferlength in the CBW block. At the end of data transfer a CSW is returned with the remaining data length and the STATUS field. ZERO DATA: no data stage is needed so CSW block is sent immediately after CBW. The BOT transport protocol encapsulates SCSI commands and transfers them in three steps:. Send the command block CBW. 2. Transfer data. 3. Return the status of the block CSW. Figure 2. BOT protocol architecture Ready Command transport CBW Data Out Data In Status Transport MS3326V DocID Rev 7/45 44

8 STM32 NAND driver blocks UM653 Bulk-Only Transport State machine #define BOT_IDLE 0 //Idle state #define BOT_DATA_OUT //Data Out state #define BOT_DATA_IN 2 //Data In state #define BOT_DATA_IN_LAST 3 //Last Data In Last #define BOT_CSW_Send 4 //Command Status Wrapper #define BOT_ERROR 5 //error state #define BOT_CBW_SIGNATURE 0x //st 4 bytes of CBW pkt #define BOT_CSW_SIGNATURE 0x //st 4 bytes of CSW pkt #define BOT_CBW_PACKET_LENGTH 3 #define CSW_DATA_LENGTH 3 CSW Status Definitions #define CSW_CMD_PASSED 0x00 #define CSW_CMD_FAILED 0x0 #define CSW_PHASE_ERROR 0x02 #define SEND_CSW_DISABLE 0 #define SEND_CSW_ENABLE #define DIR_IN 0 #define DIR_OUT #define BOTH_DIR 2.3 FSMC The FSMC block is able to communicate with the synchronous and asynchronous memory. Its main purpose is to: Translate the AHB protocol transactions of external devices Respect the access time of external devices The FSMC provides a single access to an external device. The FSMC has four blocks: AHB Interface Controller NOR Flash / PSRAM Controller NAND Flash / PC Card Interface to external device The FSMC generates the appropriate signals to drive the NAND Flash memory. The FSMC controller consists of two blocks of code error correction hardware. They reduce the workload on the host processor when processing code error correction by the system software. These two blocks are identical and are respectively associated with banks 2 and 3. The ECC algorithm used in the FSMC can perform - and 2-bit error detection. 8/45 DocID Rev

9 UM653 STM32 NAND driver blocks.4 NAND architecture NAND is a non-volatile Flash memory device where address lines are multiplexed with data input/output as well as with commands input. NAND Flash consists of a number of blocks. Each block consists of a number of pages, typically 32 or 64. Pages can be written individually, one at a time. When writing to a page, bits can only be written from to 0. The erase operation is done by block. Erase operation makes all the memory bits of all the pages in the block to logical. The small NAND Flash contains 528-byte pages (52 data area and 6 byte spare area). The page size for 2K NAND is 22 (2048 data and 64 spare area). The page size for 4K NAND is 4224 (4096 data and 28 spare area). The page size for 8K NAND is 8448 (892 data and 256 spare area). Figure 3. NAND block architecture Block 0 Block Page 0 Page Data + Spare area 0x000 Block N Block N- Physical zone Page m Physical block 0x83F 2K Physical pages or 0X000 Data Spare area 0x200 0x20F 52 Physical page (unit) MS3327V The spare area contains information about the page and the code error correction: For small page ( Byte) NAND Flash: Table. Spare area format for small NAND Flash Logical Index Block Status Data Status Wear Leveling counter ECC For Large page ( Byte) NAND Flash: Table 2. Spare area format for large NAND Flash Block Status Data Status Logical Index Wear Leveling counter ECC DocID Rev 9/45 44

10 STM32 NAND driver blocks UM653 The Logical Index contains the logical address of the block. The Block Status returns the status of the block if it is valid or not. The Data Status informs if the page is valid or invalid. Wear Leveling Counter is the number of times the block has been erased. The ECC is the error correction code calculated for each page. NAND INTERFACE x8 or x6 bus width Multiplexed Address/ Data Pinout compatibility for all densities SUPPLY VOLTAGE.8V device: VCC =.65 to.95v 3.0V device: VCC = 2.7 to 3.6V PAGE SIZE x8 device: ( spare) Bytes x6 device: ( spare) Words x8 device: ( spare) Bytes x6 device: ( spare) Words.5 NAND pin mapping I/O 8-5 I/O 0-7 ALE CLE CE/ RE/ RB/ WE/ WP/ Data Input/Outputs: for x6 devices. The I/O pins are used to input data, address, command and output data during read operation. Data Input/Outputs: Address Inputs, or Command Inputs for x8 and x6 devices. Address Latch Enable: When active, an address can be written. Command Latch Enable: This pin should be LOW while writing commands to the command register. Chip Enable: The CE input enables the device. Signal is active low. If the signal is inactive the device will be in standby. Read Enable: The RE input is the serial data out control. Signal is active low to out data. Ready/Busy (open-drain output) The RB output provides the status of the device operation. It is an open drain output, hence should be connected to a GPIO with pull-up. LOW: a program, erase or read operation is in process. HIGH: the process is complete. Write Enable: The WE input controls write operations to I/O port. Commands, data and address are latched on the rising edge of WE. Write Protect: Typically connected to Vcc, but may also be connected to a GPIO. 0/45 DocID Rev

11 UM653 NAND driver firmware modules 2 NAND driver firmware modules The NAND driver library has the following modules:. Garbage collection 2. Wear leveling 3. Bad block management 4. ECC check 5. LUT 6. FAT file system 2. Garbage collection The Garbage Collection software copies the valid data into a new (free) area and erases the original invalid data. Garbage Collection is performed when a virtual block is full or the number of free pages in the whole device is lower than a specified threshold value. The basic operations involved in Garbage Collection are the following:. The virtual blocks meeting the conditions are selected for erasure. 2. The valid physical pages are copied into a free area. 3. The selected physical blocks are erased. As virtual blocks can contain more than one physical block, the Garbage Collection may erase more than one physical block. 2.2 Wear leveling Wear leveling is a technique to increase the lifetime of NAND Flash memory. The number of reliable write cycles in NAND Flash is 00,000 erase/write cycles. If some of the blocks are written repeatedly, wearing of these blocks will happen earlier than other blocks. To balance the erase cycles over all the blocks, a wear leveling technique is introduced. All new data is written to the empty blocks. The memory controller selects the new empty block based on the number of write / erase cycles it has experienced. After the new data is written, the controller updates the LUT to point to the position of the selected physical block. The block containing the old data is erased and the number of write/erase cycles increments. DocID Rev /45 44

12 NAND driver firmware modules UM653 Figure 4. Flow of wear leveling mechanism for STEVAL-CCM006V main Set_SystemA CTR_LP Write_Memory USB_Istr MAL_Config MAL_Init NAND_Init MAL_Write NAND_Write NAND_CleanLUT Yes Is another Zone requested? NAND_WearLeveling No No LBLK_NAND_WearLeveling Small Block NAND? Yes Write in current Zone of NAND Flash SBLK_NAND_WearLeveling MS3328V 2/45 DocID Rev

13 UM653 NAND driver firmware modules Figure 5. Flow of wear leveling mechanism for STEVAL-CCM007V/ 008V OTG_FS_IRQHandler main USBD_OTG_ISR_Handler DCD_HandleOutEP_ISR NAND_Init USBD_DataOutStage NAND_CleanLUT Yes Is another Zone requested? USBD_MSC_DataOut No NAND_WearLeveling Write in current Zone of NAND Flash MSC_BOT_Data_Out SCSI_ProcessCmd No LBLK_NAND_WearLeveling Small Block NAND? Yes SCSI_Write0 SCSI_ProcessWrite SBLK_NAND_WearLeveling STORAGE_Write NAND_Write MS3329V The above figure gives an overview of the firmware flow with respect to the way the Wear Leveling Mechanism is implemented. Let us consider a scenario in which the host is trying to send the data to the controller via USB and write it to the NAND Flash. The corresponding CBW has to be decoded. The function given below is called in such a case, to write to the memory which uses the information provided from the CBW void SCSI_Write0_Cmd(uint8_t lun, uint32_t LBA, uint32_t BlockNbr) This function has the following arguments, the logical unit number, Logical block address (LBA) and the block number. The LBA passed from the host is sequential and maps to the address of the block in NAND Flash memory which comes out to be sequential. A structure is used to store the address: typedef struct { uint6_t Zone; uint6_t Block; uint6_t Page; } NAND_ADDRESS; DocID Rev 3/45 44

14 NAND driver firmware modules UM653 NAND_ADDRESS NAND_GetAddress (uint32_t Address) The above function translates a logical address into a physical one and stores it in a structure element of type NAND_ADDRESS. While writing to the NAND, the wear level algorithm should return the block to be written of which the erase count is least. To maintain the list of USED, FREE and BAD blocks an array is maintained: LUT[ ]. The previously fetched address for writing, and the free block obtained with least erase counts are swapped in LUT and updated, this ensures that the write takes place at the block with least erase count. uint6_t NAND_GetFreeBlock (void) The above function is called to get the free block for swap. The function returns the first free block it finds in the LUT[ ]. This implies that the LUT[ ] should have the free blocks arranged in the increasing order of erase count. The LUT[ ] is updated by the following function. uint6_t NAND_BuildLUT (uint8_t ZoneNbr) The above function arranges the bad block at the bottom of the array and the used and free blocks are located in the upper part of the array. uint6_t NAND_WearLeveling (void) The above function sorts the free blocks in the ascending order based on the wear level count. Now, the free block used for writing in the NAND would be the one with the least erase count. 2.3 ECC Unlike NOR Flash memory that does not require error correction code, NAND memory needs to ensure data integrity. The disadvantage of the NAND configuration is that when a cell is read, the sense amplifier detects a signal much lower than for the NOR configuration because many transistors are in series. Therefore access to a cell is not straightforward and must necessarily go through all the cells in series which reduces precision and makes code error correction required. There are three error correction codes: The Hamming code can correct only one bit error. The Reed Solomon code can correct more errors. The BCH code can correct many errors and is more efficient than Reed Solomon Hamming code for NAND Flash The Hamming code algorithm used by NAND Flash-based applications calculates two values of ECC for a data packet. Each bit in the values of ECC parity represents half of the bits of the data packet. 4/45 DocID Rev

15 UM653 NAND driver firmware modules For one byte The trick is how the data bits are partitioned for each of the parity calculations. To calculate ECC, the data bits are first divided into halves, quarters, eighths and so on until you reach the bit unit. Figure 6. Example of decomposition of a data packet Bit position Even bits 0 0 Even quarters 0 0 Even halves Data packet Odd bits 0 0 Odd quarters Odd halves MS33220V After the partition of the data packet, the parity of each group is calculated to generate two values of ECC. The results are concatenated to form the ECC values. ECC even = 0 ^ ^ 0 ^, 0 ^ ^ 0 ^, ^ ^ ^ = 000 ECC odd = 0 ^ ^ 0 ^, 0 ^ ^ 0 ^, 0 ^ 0 ^ 0 ^ 0 = 000 These ECC bits allow us to identify the error position when the data packet is analyzed at a later date. Data packets require larger number of ECC values. Each data packet of 2n-bit ECC requires a value of n bits. Based on this calculation, both the data packet and the ECC values are programmed into the NAND Flash memory. Later, when the data packet is read from the NAND, the ECC values are recalculated. Data corruption is indicated when the values of the newly calculated ECC differ from those programmed into the NAND Flash. Applying exclusive or to all four values of ECC (two old and two new), one can determine whether one or more bits have been corrupted. If the result is 000 there is no corruption. If the result is then a single bit is wrong. If two or more bits were damaged, this code allows the detection of two errors and the correction of only one bit. ECCeven (old) ^ ECCodd (old) ^ ECCeven (new) ^ ECCodd (new) When the result shows that a bit has been corrupted, the address of this bit can be identified by the application of exclusive or on both ECC odd values ECCodd (old) ^ ECCodd (new) The erroneous bit position is identified by the position of the in the "exclusive or" value. For a package of several bytes As the size of data packets increases, the Hamming algorithm becomes more efficient. Each doubling of the data packet requires two additional bits in the ECC. A data packet size of 52 bytes (the size of a page of the NAND memory used) requires 24 bits of ECC. The extension of a byte packet to a 52 byte packet requires only a change to the size of data partitions, the algorithm remains the same. DocID Rev 5/45 44

16 NAND driver firmware modules UM Error detection and correction Figure 7. Flow chart for error detection and correction New ECC generated during read XOR previous ECC with new ECC All results = zero? No > bit = zero? No Yes 2 bit = one? No 24 bit data = 0 2 bit data = All other 23 bit data = No Error Correctable error Non Correctable error ECC Error MS3322V 6/45 DocID Rev

17 UM653 NAND driver firmware modules 2.4 Bad block management Bad blocks contain one or more invalid bits whose reliability is not guaranteed. They may be present when the device is shipped, or may develop during the lifetime of the device. Figure 8. Flow chart for bad block management Start Block address = Block 0 Increment block address Block status =FFh? Yes No Update bad block table Last block? Yes No End MS33222V 2.5 Look up table (LUT) The LUT is used to find the Application Block Number corresponding to the Logical address (SCSI_LBA). All blocks are scanned and User data is read from the Spare area of each block of NAND Flash to build the LUT. 2.6 File system The free file system used in the NAND library is FAT_FS_ELM from ChaN. The NAND file system interface module ff_user_interface.c allows interfacing of file systems with the NAND driver. In standalone mode it displays the.bmp images stored in the pics folder of NAND Flash. This module should be ported to the selected file system. Table 3. File system interface functions Function disk_initialize disk_read disk_write disk_status disk_ioctl Description Initialize disk drive. Interface function for a logical page read. Interface function for a logical page write. Interface function for testing if unit is ready. Control device-dependent features. DocID Rev 7/45 44

18 NAND driver firmware modules UM653 Figure 9. Flow chart for File System NAND Main USB Set_System FAT_FS not defined USB_Disconnect_Config FAT_FS MAL_Config FSMC Clock Enable MAL_Init Set_USBClock USB_Interrupts_Config USB_Init NAND_Init FAT_FS not defined disk_initialize read write disk_read disk_write NAND_Read(sector, buff, 52); NAND_Write(sector, (BYTE*)buff, 52); NAND_Post_Write PreCopy old first pages PostCopy remaining Pages Assign LBA to New block MS3285V 8/45 DocID Rev

19 UM653 NAND driver firmware modules 2.7 NAND driver files 2.7. nand_drv.c, nand_drv.h functions NAND_Init. Table 4. NAND_Init uint6_t NAND_Init(void) Initializes NAND Interface Status of NAND Initialization. This parameter can be: NAND_OK: when the NAND is OK. NAND_FAIL: when NAND fails to initialize. Table 5. NAND_Write NAND_Write. uint6_t NAND_Write(uint32_t Memory_Offset, uint8_t *Writebuff, uint6_t Transfer_Length) Writes one sector at once Memory_Offset: Memory Offset. Writebuff: Pointer to the data to be written. Transfer_Length: Number of byte to write. Status of NAND Write. This parameter can be: NAND_OK: when the NAND Write is successful NAND_FAIL: when NAND fails to Write. Table 6. NAND_Read NAND_Read. uint6_t NAND_Read(uint32_t Memory_Offset, uint8_t *Readbuff, uint6_t Transfer_Length) Reads sectors. Memory_Offset: Memory Offset. Readbuff: Pointer to store the read data. Transfer_Length: Number of byte to read. Status of NAND Read. This parameter can be: NAND_OK: when the NAND Read is successful. NAND_FAIL: when NAND fails to Read. DocID Rev 9/45 44

20 NAND driver firmware modules UM653 NAND_WriteECC. Table 7. NAND_WriteECC uint6_t NAND_WriteECC(uint32_t Memory_Offset, uint8_t *Writebuff, uint6_t NumByte) Writes one sector & copy rest Block during ECC Correctable Error Case. Memory_Offset: Memory Offset. Writebuff: Pointer to the data to be written. Transfer_Length: Number of byte to write. Status of NAND Write. This parameter can be: NAND_OK: when the NAND Write is successful NAND_FAIL: when NAND fails to Write. Table 8. NAND_PostWriteECC NAND_PostWriteECC. uint6_t NAND_PostWriteECC(void) Copies whole block after writing corrected page in ECC Correction. Status of NAND Write. Table 9. NAND_CleanLUT NAND_CleanLUT. uint6_t NAND_CleanLUT (uint8_t ZoneNum) Rebuilds the Look Up Table. ZoneNbr: Zone Number to Rebuild the Look Up Table. Status of NAND Build look up table. This parameter can be: NAND_OK: when the NAND Clean is successful. NAND_FAIL: when NAND fails to clean look up table. Table 0. NAND_WearLeveling NAND_WearLeveling. uint6_t NAND_WearLeveling (uint8_t ZoneNumber) Builds the Look Up Table According to the Wear Count. ZoneNumber: Zone Number. Status of NAND wear Leveling. This parameter can be: NAND_OK: when the NAND wear leveling is successful. NAND_FAIL: when NAND fails to wear leveling. 20/45 DocID Rev

21 UM653 NAND driver firmware modules Table. SBLK_NAND_WearLeveling SBLK_NAND_WearLeveling. uint6_t SBLK_NAND_WearLeveling (uint8_t ZoneNumber) Builds the Look Up Table According to the Wear Count. ZoneNumber: Zone Number. Status of SBLK_NAND_WearLeveling. This parameter can be: NAND_OK: when the NAND wear leveling is successful NAND_FAIL: when NAND fails to wear leveling. Table 2. LBLK_NAND_WearLeveling LBLK_NAND_WearLeveling. uint6_t LBLK_NAND_WearLeveling (uint8_t ZoneNumber) Builds the Look Up Table According to the Wear Count. ZoneNumber: Zone Number. Status of LBLK_NAND_WearLeveling. This parameter can be: NAND_OK: when the NAND wear leveling is successful NAND_FAIL: when NAND fails to wear leveling. Table 3. NAND_GetFreeBlock NAND_GetFreeBlock. uint6_t NAND_GetFreeBlock (void) Looks for a free Block for data exchange from Look Up Table. Logical Block Number of free Block. Table 4. SBLK_NAND_ReadSpareArea SBLK_NAND_ReadSpareArea. SPARE_AREA SBLK_NAND_ReadSpareArea (uint32_t address) Page Number in multiple of 52 Byte per Page. address: Corresponding Page Number of Spare Area to be read. SPARE AREA after reading. Table 5. LBLK_NAND_ReadSpareArea LBLK_NAND_ReadSpareArea. LBLK_SPARE_AREA LBLK_NAND_ReadSpareArea (uint32_t address) Page Number in multiple of 52 Byte per Page. address: Corresponding Page Number of Spare Area to be read. LBLK_SPARE_AREA after reading. DocID Rev 2/45 44

22 NAND driver firmware modules UM653 WriteSpareArea. Table 6. WriteSpareArea uint6_t WriteSpareArea (uint32_t address, uint8_t *buff) Page Number in multiple of 52 Byte. address: Corresponding Page Number of Spare Area to be read. buff: Pointer to the data to be written in SPARE AREA. Status of WriteSpareArea. This parameter can be: NAND_OK: when Write SPARE AREA is successful. NAND_FAIL: when Write SPARE AREA fails to Write. Table 7. NAND_Copy NAND_Copy. uint6_t NAND_Copy (NAND_ADDRESS Address_Src, NAND_ADDRESS Address_Dest, uint6_t PageToCopy) Copies pages from source to destination. Address_Src: Source Address. Address_Dest: Destination Address. PageToCopy: Number of Page to copy. Status of NAND Copy. This parameter can be: NAND_OK: when the NAND copy is successful NAND_FAIL: when NAND fails to copy. Table 8. NAND_CopyBack NAND_CopyBack. uint6_t NAND_CopyBack (NAND_ADDRESS Address_Src, NAND_ADDRESS Address_Dest, uint6_t PageToCopy) Copies pages from Source to Destination. (Source & Destination address must have same page number). Address_Src: Source Address. Address_Dest: Destination Address. PageToCopy: Number of Page to copy Status of NAND Copy. This parameter can be: NAND_OK: when the NAND copy is successful NAND_FAIL: when NAND fails to copy. 22/45 DocID Rev

23 UM653 NAND driver firmware modules NAND_Format. Table 9. NAND_Format uint6_t NAND_Format (void) Format the entire NAND Flash. Status of NAND Format. This parameter can be: NAND_OK: when the NAND Format is successful NAND_FAIL: when NAND fails to Format. Table 20. NAND_PostWrite NAND_PostWrite. uint6_t NAND_PostWrite (void) NAND Post Write. Status of NAND Post Write. This parameter can be: NAND_OK: when the NAND Post Write is successful NAND_FAIL: when NAND fails to Post Write. Table 2. SBLK_NAND_PostWrite SBLK_NAND_PostWrite. void SBLK_NAND_PostWrite (void) Small Block NAND_PostWrite. Table 22. LBLK_NAND_PostWrite LBLK_NAND_PostWrite. void LBLK_NAND_PostWrite (void) Large Block NAND Post Write. DocID Rev 23/45 44

24 NAND driver firmware modules UM653 Table 23. NAND_GarbageCollection NAND_GarbageCollection. uint6_t NAND_GarbageCollection(void) Erases Blocks every time the write operation is stopped. Status of NAND Garbage collection. This parameter can be: NAND_OK: when the NAND Garbage collection is successful NAND_FAIL: when NAND fails to Garbage collection. Table 24. NAND_UpdateWearLevelCounter NAND_UpdateWearLevelCounter. uint6_t NAND_UpdateWearLevelCounter (NAND_ADDRESS Address) Increments the value of Wear Level counter after every erase. Address: Logical Address. Status of NAND Update Wear Level. This parameter can be: NAND_OK: when the NAND Update Wear Level is successful NAND_FAIL: when NAND fails to Update Wear Level. Table 25. NAND_ConvertPhyAddress NAND_ConvertPhyAddress. NAND_ADDRESS NAND_ConvertPhyAddress (uint32_t Address) Converts Memory Offset into Physical Address. Address: Memory Offset in Multiple of 52B(0,52/52,024/52...). Physical Address. Table 26. NAND_BuildLUT NAND_BuildLUT. uint6_t NAND_BuildLUT (uint8_t Zone) Builds the Look Up Table. ZoneNbr: The Zone Number. Status of NAND Build Look Up Table. This parameter can be: NAND_OK: when the NAND Build Look Up Table is successful NAND_FAIL: when NAND fails to Build Look Up Table. 24/45 DocID Rev

25 UM653 NAND driver firmware modules Table 27. SBLK_NAND_BuildLUT SBLK_NAND_BuildLUT. uint6_t SBLK_NAND_BuildLUT (uint8_t ZoneNumber) Builds the Look Up Table. ZoneNbr: The Zone Number. Status of NAND Build Look Up Table. This parameter can be: NAND_OK: when the NAND Build Look Up Table is successful NAND_FAIL: when NAND fails to Build Look Up Table. Table 28. LBLK_NAND_BuildLUT LBLK_NAND_BuildLUT. uint6_t LBLK_NAND_BuildLUT (uint8_t ZoneNbr) Builds the Look Up Table. ZoneNbr: The Zone Number. Status of NAND Build Look Up Table. This parameter can be: NAND_OK: when the NAND Build Look Up Table is successful NAND_FAIL: when NAND fails to Build Look Up Table. Table 29. GetParity GetParity. uint8_t GetParity (uint6_t in_value) Calculate parity. in_value: 6-bit value. Status. Table 30. Swap Swap. uint6_t Swap (uint6_t in) Swaps a 6-bit. in: 6-bit value. swapped value. DocID Rev 25/45 44

26 NAND driver firmware modules UM653 WritePage. Table 3. WritePage void NAND_WritePage(NAND_ADDRESS Address, uint8_t *buff, uint6_t len) Writes a page & Corresponding SPARE AREA. Address: The address of the page to write. *buff: The buffer to write in. len: The Number of page to write. Table 32. SBLK_NAND_WritePage SBLK_NAND_WritePage. void SBLK_NAND_WritePage(NAND_ADDRESS Address, uint8_t *buff, uint6_t len) Writes page & Corresponding ECC in SPARE AREA in Small Block NAND. Address: The address of the page to write. *buff: The buffer to write in. len: The Number of page to write. Table 33. LBLK_NAND_WritePage LBLK_NAND_WritePage. void LBLK_NAND_WritePage(NAND_ADDRESS Address, uint8_t *buff, uint6_t len) Write a page & Corresponding ECC in SPARE AREA in Small Block NAND. Address: The address of the page to write. *buff: The buffer to write in. len: The Number of page to write. 26/45 DocID Rev

27 UM653 NAND driver firmware modules ReadPage. Table 34. ReadPage void NAND_ReadPage (NAND_ADDRESS Address, uint8_t *buff, uint6_t len) Reads a page considering Error correction code( bit per 52 Byte). Address: The address of the page to read. *buff: The buffer to read from. len: The number of page to read. Table 35. SBLK_NAND_ReadPage SBLK_NAND_ReadPage. void SBLK_NAND_ReadPage (NAND_ADDRESS Address, uint8_t *buff, uint6_t len) Reads a page considering Error correction code ( bit per 52 Byte) in Small Block NAND. Address: The address of the page to read. *buff: The buffer to read from. len: The number of page to read. Table 36. LBLK_NAND_ReadPage LBLK_NAND_ReadPage. void LBLK_NAND_ReadPage (NAND_ADDRESS Address, uint8_t *buff, uint6_t len) Reads a page considering Error correction code ( bit per 52 Byte) in Large Block NAND. Address: The address of the page to read. *buff: The buffer to read from. len: The number of page to read. Table 37. BitCount BitCount. uint8_t BitCount(uint32_t num) Counts the number of 's in 32 bit Number. num: The number in which number of 's to be counted. The number of one in 32 bit number. DocID Rev 27/45 44

28 NAND driver firmware modules UM fsmc_nand_if.c, fsmc_nand_if.h functions Table 38. FSMC_SelectNANDType FSMC_SelectNANDType. void FSMC_SelectNANDType(void) Selects the NAND Type & sets the Required Parameter accordingly. NAND may be SBLK_NAND or LBLK_NAND. Table 39. FSMC_NAND_NON_ONFI_Compliance FSMC_NAND_NON_ONFI_Compliance. void FSMC_NAND_NON_ONFI_Compliance(void) Selects the NON ONFI NAND Type & sets the Required Parameter accordingly. NAND may be SBLK_NAND or LBLK_NAND. Table 40. FSMC_NAND_Init FSMC_NAND_Init. void FSMC_NAND_Init(void) Configures the FSMC and GPIOs to interface with the NAND memory. This function must be called before any write/read operation. Table 4. FSMC_NAND_ReadID FSMC_NAND_ReadID void FSMC_NAND_ReadID(NAND_IDTypeDef* NAND_ID) Reads NAND memory's Manufacturer and Device ID. NAND_ID: pointer to a NAND_IDTypeDef structure 28/45 DocID Rev

29 UM653 NAND driver firmware modules Table 42. FSMC_NAND_WriteSmallPage FSMC_NAND_WriteSmallPage. uint32_t FSMC_NAND_WriteSmallPage(uint8_t *pbuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite) Writes one or several 52 Bytes Page size. pbuffer: pointer on the Buffer containing data to be written. Address: First page address. NumPageToWrite: Number of page to write. New status of the NAND operation. This parameter can be: NAND_TIMEOUT_ERROR: when the previous operation generate a Timeout error. NAND_READY: when memory is ready for the next operation New status of the increment address operation. It can be: NAND_VALID_ADDRESS: When the new address is valid. NAND_INVALID_ADDRESS: When the new address is invalid. Table 43. FSMC_NAND_ReadSmallPage FSMC_NAND_ReadSmallPage. uint32_t FSMC_NAND_ReadSmallPage(uint8_t *pbuffer, NAND_ADDRESS Address, uint32_t NumPageToRead) Sequential read from one or several 52 Bytes Page size. pbuffer: pointer on the Buffer to fill. Address: First page address. NumPageToRead: Number of page to read. New status of the NAND operation. This parameter can be: NAND_TIMEOUT_ERROR: when the previous operation generate a Timeout error. NAND_READY: when memory is ready for the next operation. New status of the increment address operation. It can be: NAND_VALID_ADDRESS: When the new address is valid. NAND_INVALID_ADDRESS: When the new address is invalid. DocID Rev 29/45 44

30 NAND driver firmware modules UM653 Table 44. FSMC_NAND_WriteSpareArea FSMC_NAND_WriteSpareArea. uint32_t FSMC_NAND_WriteSpareArea(uint8_t *pbuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite) Writes spare area information for specified page addresses. pbuffer: pointer on the Buffer containing data to be written. Address: First page address. NumSpareAreaTowrite: Number of Spare Area to write. New status of the NAND operation. This parameter can be: NAND_TIMEOUT_ERROR: when the previous operation generate a Timeout error. NAND_READY: when memory is ready for the next operation New status of the increment address operation. It can be: NAND_VALID_ADDRESS: When the new address is valid. NAND_INVALID_ADDRESS: When the new address is invalid. Table 45. FSMC_NAND_ReadSpareArea FSMC_NAND_ReadSpareArea. uint32_t FSMC_NAND_ReadSpareArea(uint8_t *pbuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead) Reads the spare area information from the specified page addresses. pbuffer: pointer on the Buffer to fill. Address: First page address. NumSpareAreaToRead: Number of Spare Area to read. New status of the NAND operation. This parameter can be: NAND_TIMEOUT_ERROR: when the previous operation generated a Timeout error. NAND_READY: when memory is ready for the next operation New status of the increment address operation. It can be: NAND_VALID_ADDRESS: When the new address is valid. NAND_INVALID_ADDRESS: When the new address is invalid. Table 46. FSMC_NAND_EraseBlock FSMC_NAND_EraseBlock. uint32_t FSMC_NAND_EraseBlock(NAND_ADDRESS Address) Erases complete block from NAND FLASH. Address: Any address into block to be erased. New status of the NAND operation. This parameter can be: NAND_TIMEOUT_ERROR: when the previous operation generate a Timeout error. NAND_READY: when memory is ready for the next operation. 30/45 DocID Rev

31 UM653 NAND driver firmware modules Table 47. FSMC_NAND_Reset FSMC_NAND_Reset. uint32_t FSMC_NAND_Reset(void) Resets the NAND FLASH. NAND_READY. Table 48. FSMC_NAND_GetStatus FSMC_NAND_GetStatus. uint32_t FSMC_NAND_GetStatus(void) Gets the NAND operation status. New status of the NAND operation. This parameter can be: NAND_TIMEOUT_ERROR: when the previous operation generate a Timeout error. NAND_READY: when memory is ready for the next operation. Table 49. FSMC_SBLK_NAND_CopyBack FSMC_SBLK_NAND_CopyBack. uint32_t FSMC_SBLK_NAND_CopyBack(NAND_ADDRESS src, NAND_ADDRESS dest) Copies One Page from Source Address to Destination Address without utilizing external Memory. src: Source Address. dest: Destination Address. The status of the NAND memory. This parameter can be: NAND_BUSY: when memory is busy. NAND_READY: when memory is ready for the next operation. NAND_ERROR: when the previous operation generates error. DocID Rev 3/45 44

32 NAND driver firmware modules UM653 Table 50. FSMC_LBLK_NAND_CopyBack FSMC_LBLK_NAND_CopyBack. uint32_t FSMC_LBLK_NAND_CopyBack(NAND_ADDRESS src, NAND_ADDRESS dest) Copies One Page from Source Address to Destination Address without utilizing external Memory. src: Source Address. dest: Destination Address. The status of the NAND memory. This parameter can be: NAND_BUSY: when memory is busy. NAND_READY: when memory is ready for the next operation. NAND_ERROR: when the previous operation generates error. Table 5. FSMC_NAND_ReadStatus FSMC_NAND_ReadStatus. uint32_t FSMC_NAND_ReadStatus(void) Reads the NAND memory status using the Read status command. The status of the NAND memory. This parameter can be: NAND_BUSY: when memory is busy. NAND_READY: when memory is ready for the next operation. NAND_ERROR: when the previous operation generates Error. Table 52. FSMC_NAND_AddressIncrement FSMC_NAND_AddressIncrement. uint32_t FSMC_NAND_AddressIncrement(NAND_ADDRESS* Address) Increments the NAND memory address. Address: address to increment. The new status of the increment address operation. It can be: NAND_VALID_ADDRESS: When the new address is valid address. NAND_INVALID_ADDRESS: When the new address is invalid address. Table 53. FSMC_NAND_ONFI_Compliance FSMC_NAND_ONFI_Compliance. void FSMC_NAND_ONFI_Compliance(void) Selects the ONFI NAND Type & sets the Required Parameter accordingly. NAND may be SBLK_NAND or LBLK_NAND. 32/45 DocID Rev

33 UM653 NAND driver firmware modules Table 54. FSMC_SBLK_NAND_SendAddress FSMC_SBLK_NAND_SendAddress. void FSMC_SBLK_NAND_SendAddress(NAND_ADDRESS Addr) Sends the address for Small Block NAND. Addr: NAND_ADRESS to be sent.. Table 55. FSMC_LBLK_NAND_SendAddress FSMC_LBLK_NAND_SendAddress. void FSMC_LBLK_NAND_SendAddress(uint32_t row, uint32_t column) Sends the row & column address for Large Block NAND. row: Row Address. column: Column address.. DocID Rev 33/45 44

34 NAND driver firmware modules UM Supported NAND Flash Below is the list of supported NAND Flash in our firmware. Table 56. Supported NAND Flash Supported NAND Capacity Tested Small block NAND NAND28R3A 28 Mbits Y 2 NAND28W3A 28 Mbits Y 3 NAND256R3A 256 Mbits Y 4 NAND256W3A 256 Mbits Y 5 NAND52R3A 52 Mbits Y 6 NAND52W3A 52 Mbits Y 7 NAND0GR3A Gbits Y 8 NAND0GW3A Gbits Y 9 K9F5608U0A 256 MBits Y Large block NAND NAND52R3B 52 Mbits N 2 NAND52W3B 52 Mbits N 3 NAND0GR3B Gbits Y 4 NAND0GW3B Gbits Y 5 NAND02GR3B 2 Gbits N 6 NAND02GW3B 2 Gbits N 7 NAND04GR3B 4 Gbits N 8 NAND04GW3B 4 Gbits N 9 NAND08GR3B 8 Gbits N 0 NAND08GW3B 8 Gbits N H27U4G8F2DTR Gbits Y 2 TC58NVG0S3BFT00 4 Gbits Y The firmware supports other manufacturer's NAND Flash with same device ID without any change to hardware or firmware. The code size for the NAND Flash Driver files (nand_drv.c & fsmc_nand_if.c) is Table 57. NAND Flash driver file code size Code Size Flash RAM With Optimization (High size) 6.5 KB 5 KB Without Optimization.7 KB 5 KB 34/45 DocID Rev

35 UM653 NAND evaluation board 3 NAND evaluation board 3. Working with evaluation boards The evaluation boards STEVAL-CCM006V, STEVAL-CCM007V and STEVAL- CCM008V work in USB Mass Storage mode. In this mode NAND Flash behaves as mass storage media. The evaluation boards STEVAL-CCM006V2, STEVAL-CCM007V2 and STEVAL- CCM008V2 work in Standalone mode. In this mode, the bmp images stored in the pics folder of root directory are displayed using the File System on the mounted TFT. Figure 0 & Figure show the component layout to help the user locate the various components and sections on the board. Figure 0. Evaluation board: top side JTAG connector Touch screen controller TFT connector MS33246V DocID Rev 35/45 44

36 NAND evaluation board UM653 Figure. Evaluation board: bottom side RESET switch Mini USB Port (Full Speed) STM32 Voltage Regulator Micro USB Port (High Speed) NAND Flash NAND Flash socket footprint USB High Speed PHY* MS33245V Note: The USB High Speed section is only present in STEVAL-CCM007V, STEVAL-CCM007V2, STEVAL-CCM008V and STEVAL-CCM008V Running in USB Mass Storage mode (STEVAL-CCM006/7/8V) The STEVAL-CCM006V, STEVAL-CCM007V, STEVAL-CCM008V boards are programmed for USB Full Speed by default. To run USB High Speed, you must program the board using proper firmware using available tool chain.. Connect the mini-usb cable between a jumper on the PCB and the Host (PC) J4 for USB FS Demo. J7 for USB HS Demo. 2. The device is detected as a USB mass storage device in Device Manager of Host (PC). 3. The device appears as a Removable Drive on the Host (PC). 36/45 DocID Rev

37 UM653 NAND evaluation board 4. This drive can be used as Mass Storage Media Running in Standalone mode (STEVAL-CCM006/7/8V2) The STEVAL-CCM006V2, STEVAL-CCM007V2, STEVAL-CCM008V2 boards run in Standalone mode.. By default TFT is mounted on J6. 2. Connect mini-usb cable between J4 on the PCB and the Host (PC). 3. The bmp images stored in the "pics" folder of root directory are displayed on the TFT. Figure 2. Demo running in Standalone mode DocID Rev 37/45 44

38 NAND evaluation board UM653 38/45 DocID Rev 3.2 Schematics Figure 3. Microcontroller schematic Figure 4. USB Full Speed schematic VCAP PH0_OSC_IN PH_OSC_OUT NRST VCAP VCAP PE3 PB8 PE2 PB9 PB5_OTG_HS_ULPI_D7 PA3_OTG_HS_ULPI_D0 PH0_OSC_IN PB0_OTG_HS_ULPI_D PH_OSC_OUT PA0_OTG_FS_ID_USB PE2 PB_OTG_HS_ULPI_D2 PC0_OTG_HS_ULPI_STP PA3_JTAG_JTMS PA_OTG_FS_DM_USB PG8_USB_PU PB8 PA5_JTAG_JTDI PA2_OTG_FS_DP_USB PB9 PA4_JTAG_JTCK PB3_OTG_HS_ULPI_D6 PD0_FSMC_D2 PE3 PD_FSMC_D3 PB2_OTG_HS_ULPI_D5 PF0_FSMC_ADDR_A0 PB7_I2C_SDA PD4_FSMC_D0 PD5_FSMC_D PB6_I2C_SCL PE7_FSMC_D4 PE0_FSMC_D7 PE9_FSMC_D6 PE8_FSMC_D5 PD5_FSMC_NWE PD_FSMC_ADDR_A6 PE_FSMC_D8 PD2_FSMC_ADDR_A7 PE4_FSMC_D PE3_FSMC_D0 PE2_FSMC_D9 PD8_FSMC_D3 PE5_FSMC_D2 PD0_FSMC_D5 PD9_FSMC_D4 PD4_FSMC_NOE PB0_OTG_HS_ULPI_D3 NRST PC3_OTG_HS_ULPI_NXT PC2_OTG_HS_ULPI_DIR PB3_JTAG_JTDO PB4_JTAG_JNTRST PA9_OTG_FS_VBUS_USB PB_OTG_HS_ULPI_D4 PA5_OTG_HS_ULPI_CK PG0_FSMC_NE3 PG7_FSMC_INT3 PG4_TSCREEN_INT PG6_FSMC_INT2 PD6_FSMC_NWAIT PD7_FSMC_E2 PG9_FSMC_E3 For STM32F0xx Mount --- R,R8,R DNM --- R3,R9 For STM32F2xxx & STM32F4xxx Mount --- R3,R9 DNM --- R,R8,R For STM32F0xx Y MHz For STM32F2xxx & STM32F4xxx Y MHz STM32F03ZET6/ STM32F205ZET6/ STM32F405ZGT6 U U PB4 75 PB3 74 PB2 73 VDD_ 72 VCAP_ 7 PB 70 PB0 69 PE5 68 PE4 67 PE3 66 PE2 65 PE 64 PE0 63 VDD_7 62 VSS_7 6 PE9 60 PE8 59 PE7 58 PG 57 PE4 3 PE5 4 PE6 5 VBAT 6 PC3-TAMPER-RTC 7 PC4-OSC32_IN 8 PC5-OSC32_OUT 9 PF0 0 PF PF2 2 PF3 3 PF5 5 PF4 4 PE2 PE3 2 PF7 9 VSS_5 6 PC2 28 VDD_5 7 PF6 8 PF8 20 PF9 2 PF0 22 OSC_IN 23 OSC_OUT 24 NRST 25 PC0 26 PC 27 PC3 29 VDD_2 30 VSSA 3 VREF+ 32 VDDA 33 PA0_WKUP 34 PA 35 PA2 36 PA3 37 VSS_4 38 VDD_4 39 PA4 40 PA5 4 PA6 42 PA7 43 PG0 56 PF5 55 PF4 54 PF3 53 VDD_6 52 VSS_6 5 PF 49 PB2-BOOT 48 PF2 50 PB 47 PB0 46 PC5 45 PC4 44 PB5 76 PD8 77 PD9 78 PD0 79 PD 80 PD2 8 PD3 82 VSS_8 83 VDD_8 84 PD4 85 PD5 86 PG2 87 PG3 88 PG4 89 PG5 90 PG6 9 PG7 92 PG8 93 VSS_9 94 VDD_9 95 PC6 96 PC7 97 PC8 98 PC9 99 PA8 00 PA9 0 PA0 02 PA 03 PA2 04 PA3 05 VCAP_2 06 VSS_2 07 VDD_2 08 PA4 09 PA5 0 PC0 PC 2 PC2 3 PD0 4 PD 5 PD2 6 PD3 7 PD4 8 PD5 9 VSS_0 20 VDD_0 2 PD6 22 PD7 23 PG9 24 PG0 25 PG 26 PG2 27 PG3 28 PG4 29 VSS_ 30 VDD_ 3 PG5 32 PB3 33 PB4 34 PB5 35 PB6 36 PB7 37 PB8 39 PB9 40 BOOT0 38 PE0 4 PE 42 VDD_3 43 VDD_SA 44 R 0 Ohm 0 R6 K C4 00nF C2 00nF C3 20pF C3 00nF K Y 25MHz C 00nF C0 00nF R7 390 R4 0K R C8 00nF C2 20pF TP TEST POINT J2 CONN TRBLK 3 J C7 00nF R0 0K R0 0K C6 00nF R8 0 Ohm D2 TEST_LED2 D2 C5 2.2uF R9 0 Ohm R 0 Ohm R3 0 Ohm C4 2.2uF C 00nF R5 K C5 00nF R2 0K R2 0K R3 K J CONN TRBLK D TEST_LED SW PUSH BUTTON C7 00nF C6 00nF C9 00nF MS33224V MS33225V USB5V_FS PA_OTG_FS_DM_USB PA2_OTG_FS_DP_USB PA2_OTG_FS_DP_USB PA9_OTG_FS_VBUS_USB PA0_OTG_FS_ID_USB PG8_USB_PU C22 0uF C22 0uF J4 USB_MINIA/B TYPE J4 USB_MINIA/B TYPE USB_VCC USBDM 2 USBDP 3 USB_ 5 SHELL 6 SHELL 7 SHELL 8 ID 4 SHELL 9 R32 22 R32 22 R4.5k R4.5k C23 4.7nF C23 4.7nF U4 USBLC6-2P6 U4 USBLC6-2P6 I/O2 4 VBUS 5 I/O 6 I/O 2 I/O2 3 R3 M R3 M D3 LED_GREEN D3 LED_GREEN R34 22 R34 22 R36 0 R36 0 R40 k R40 k

39 UM653 NAND evaluation board Figure 5. USB High Speed schematic _HS XTAL XTAL2 9 6 C27 C28 C29 0.uF 0.uF 0.uF C30 0.uF R43 0K C36 4.7uF PA3_OTG_HS_ULPI_D0 PB0_OTG_HS_ULPI_D PB_OTG_HS_ULPI_D2 PB0_OTG_HS_ULPI_D3 PB_OTG_HS_ULPI_D4 PB2_OTG_HS_ULPI_D5 PB3_OTG_HS_ULPI_D6 PB5_OTG_HS_ULPI_D U6 DATA0 DATA DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 REG_EN 3 6 VDD3.3 VDD VDD VDD3.3 XO XI RESET NXT DIR STP CLKOUT VDD.8 VDDA.8 VDD.8 PAD 33 2 CPEN 3 EXTVBUS 0 RBIAS 32 VBUS 4 DM 8 DP 7 ID 5 R46 2K R R44 K D6 LED_GREEN USB5V_HS USB_VCC USBDM USBDP ID USB_ J7 SHELL SHELL 6 7 L BEAD USB C4 33pF C45 33pF XTAL Y2 24MHz XTAL2 R50 M PC3_OTG_HS_ULPI_NXT PC2_OTG_HS_ULPI_DIR PC0_OTG_HS_ULPI_STP PA5_OTG_HS_ULPI_CK C46 4.7uF C42 0.uF C43 0.uF C44 4.7uF R52 0 _HS MS33226V Figure 6. Touch Screen schematic A A C3 2pF C32 2pF C33 2pF C34 2pF TSC_YU TSC_XR TSC_YD TSC_XL A R57 0 A A C37 uf C38 00nF A L2 BEAD TSC_XR TSC_YU TSC_XL U7 3 X+ STMPE8 Y- INT A0 SCLK IN0 8 VCC 6 5 SDAT SDAT IN3 4 IN2 0 9 IN 4 VIO 5 DATA_IN 7 Y+ 6 X- C39 00nF A C40 0uF TSC_YD PG4_TSCREEN_INT A SCLK R54 0k SCLK SDAT R5 R PB6_I2C_SCL PB7_I2C_SDA R48 4.7K R49 4.7K A C47 00nF MS33227V DocID Rev 39/45 44

40 NAND evaluation board UM653 PG0_FSMC_NE3 PD5_FSMC_NWE NRST PD5_FSMC_D PD_FSMC_D3 PE8_FSMC_D5 PE0_FSMC_D7 PE2_FSMC_D9 PE4_FSMC_D PD8_FSMC_D3 PD0_FSMC_D5 5V0 TSC_XL TSC_YD Figure 7. TFT Connector schematic J PF0_FSMC_ADDR_A0 PD4_FSMC_NOE PD4_FSMC_D0 PD0_FSMC_D2 PE7_FSMC_D4 PE9_FSMC_D6 PE_FSMC_D8 PE3_FSMC_D0 PE5_FSMC_D2 PD9_FSMC_D4 5V0 TSC_XR TSC_YU CONNECTOR20x2 MS33228V Figure 8. Power schematic USB5V_FS D4 USB5V_HS STPSL30U D5 STPSL30U 5V0 C48 0uF C35 00nF U5 VOUT VOUT VIN 8 7 VOUT C26 6 0uF VOUT 5 LD7D33TR R45 D7 k LED_GREEN MS33229V 40/45 DocID Rev

41 UM653 NAND evaluation board Figure 9. NAND Flash schematic R55 _NAND 0 Ohm _NAND _NAND C8 C9 R9 R20 00nF 00nF 0K 0K PG6_FSMC_INT2 PD6_FSMC_NWAIT R25 0 Ohm U2 48 R PD7_FSMC_E2 R26 0 Ohm 4 45 PG9_FSMC_E PE0_FSMC_D7 22 Ohm I/O I/O6 PE9_FSMC_D RB PE8_FSMC_D5 R33 I/O5 PD4_FSMC_NOE 8 4 R I/O4 PE7_FSMC_D4 _NAND 9 E 40 _NAND K 38 _NAND 2 VDD VDD 37 _NAND 3 VSS VSS PD_FSMC_ADDR_A6 6 CL 33 PD2_FSMC_ADDR_A AL I/O3 PD_FSMC_D3 PD5_FSMC_NWE 8 3 W I/O2 PD0_FSMC_D PD5_FSMC_D R4 WP I/O I/O0 PD4_FSMC_D0 _NAND 2 28 C K 00nF NAND52B R56 _NAND2 0 Ohm _NAND2 _NAND2 C20 C2 R2 R22 00nF 00nF 0K 0K PG7_FSMC_INT3 PD6_FSMC_NWAIT R27 0 Ohm U3 _NAND2 R29 22 Ohm R35 0K PD4_FSMC_NOE _NAND2 PD_FSMC_ADDR_A6 PD2_FSMC_ADDR_A7 PD5_FSMC_NWE R42 0K R30 0 Ohm C25 00nF RB R E VDD VSS CL AL W WP I/O7 43 I/O6 42 I/O5 4 I/O VDD 37 VSS I/O3 3 I/O2 30 I/O 29 I/O NAND52B PE0_FSMC_D7 PE9_FSMC_D6 PE8_FSMC_D5 PE7_FSMC_D4 _NAND2 PD_FSMC_D3 PD0_FSMC_D2 PD5_FSMC_D PD4_FSMC_D0 MS33230V DocID Rev 4/45 44

42 NAND evaluation board UM653 42/45 DocID Rev Figure 20. NAND Flash Signals schematic Figure 2. JTAG schematic MS3323V PD5_FSMC_D PD0_FSMC_D2 PD_FSMC_D3 PD5_FSMC_NWE PD2_FSMC_ADDR_A7 PD_FSMC_ADDR_A6 PD4_FSMC_NOE PE0_FSMC_D7 PE7_FSMC_D4 PE8_FSMC_D5 PE9_FSMC_D6 PD4_FSMC_D0 PD7_FSMC_E2 PD6_FSMC_NWAIT PG6_FSMC_INT2 PG9_FSMC_E3 PG7_FSMC_INT3 J3 CON20 J MS33232V PB3_JTAG_JTDO PA3_JTAG_JTMS PB3_JTAG_JTDO PA4_JTAG_JTCK PB4_JTAG_JNTRST PA5_JTAG_JTDI NRST DBGRQ RTCK DBGACK PA3_JTAG_JTMS PA5_JTAG_JTDI PB4_JTAG_JNTRST NRST PA4_JTAG_JTCK PB3_JTAG_JTDO PA4_JTAG_JTCK PB4_JTAG_JNTRST PA3_JTAG_JTMS NRST PA5_JTAG_JTDI NRST R8 0k R8 0k R7 0k R7 0k R39 0k R39 0k R23 0 R23 0 R6 0k R6 0k R38 0k R38 0k R5 0k R5 0k R24 0k R24 0k R37 0k R37 0k J5 JTAG_CONN J5 JTAG_CONN

43 UM653 NAND evaluation board 3.3 NAND evaluation board images Figure 22. Top side of PCB Figure 23. Bottom side of PCB DocID Rev 43/45 44

44 Revision history UM653 4 Revision history Table 58. Document revision history Date Revision Changes 28-Nov-203 Initial release. 44/45 DocID Rev

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