AND8280/D. NCP1351 Modeling Using the PWM Switch Technique APPLICATION NOTE

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1 NP5 Modeling Using the PWM Switch Technique Prepared by: Stéphanie onseil ON Semiconductor APPLIATION NOTE This document describes the average modeling of the NP5 a fixed on time / variable off time controller. The advantage of using an average model is that you can perform ac simulations of your power supply to study the stability of your system. Another advantage is that transient simulations with the averaged model are faster compared to transient simulations with a cycle by cycle model. The model is very simple to use and can be downloaded from ON website. Presentation of the PWM Switch Technique The Pulse Width Modulation switch model was developed by Vatché Vorpérian (Jet Propulsory Laboratory, Passadena, A) in 98. His approach consisted in modeling the switch network alone (power switch diode) by averaging the voltage and current waveform in the circuitry. He obtained a terminal model (node A, and P) where: Node A represents the active node, the switch terminal not connected to the diode Node is the common node, the junction between the power switch and the diode Node P is the passive node, the diode terminal not connected to the switch The input variables are the current in node A, the voltage V ap ; the output variables are the current in node and the voltage V ap (Figure ). I a A I c V ap V ap P Figure. PWM Switch and its Variables The PWM switch is invariant i.e. the PWM switch electrical structure is the same whatever converter we consider. For this reason, we will use a buck boost converter for the study, because of simplicity but also because the flyback topology where the NP5 is used is derived from buck boost. Modeling the Switching Network Figures and show the switching network in the buck boost circuit and its equivalent implementation in PWM switch. V in SW D PWM L Figure. Buck Boost onverter R Semiconductor omponents Industries, LL, 00 January, 00 Rev. 0 Publication Order Number: AND880/D

2 V in 8 X PWMVM c a d L PWM PWM Switch VM 0 R load Figure. PWM Switch in the Buck boost onverter p Once the switch network has been identified in the original circuit, a simple rotation of the PWM switch model leads to the final implementation. This step is necessary to unveil the various variables in play. Averaging the PWM Switch Waveforms NP5 is a fixed peak current variable t off current mode converter without internal ramp compensation. We will first consider the DM mode to derive the equations since further developments will show that the model automatically toggles from DM to M. The method consists of identifying current, voltage waveforms in the switch terminals (Figure and Figure 5) and averaging them over one switching period. I a (t) I pk V S /R sense I a (t) I pk V S /R sense V ac /L V ac /L I c (t) I pk V S /R sense I c (t) I pk V S /R sense V ac /L V cp /L V ac /L V cp /L d /T SW d /T SW d /T SW d /T SW d /T SW Figure. The urrent Waveforms in DM: I a, I c The average current flowing in the terminal is given by the following equation []: I V S Rsense d TSW V P L d d (eq. ) According to Figure, the following expressions for the terminal voltages and currents can be easily verified []: Vac L Vcp L IPK dtsw IPK dtsw (eq. ) (eq. ) Ia I PK d (eq. ) Ic I PK (d d) (eq. 5) The average current in terminal A is deduced from equations () and (5): Ia Ic d d d (eq. ) Figure 5. The urrent Waveforms in M: I a, I c The average on time duty cycle d is solved from Equations () and () It is necessary to clamp the duty cycle d value between 0.0 and 0.9 ( to 90% duty cycle) to avoid convergence issues. d d Vcp Vac d expression is derived from Equations () and (5) d (eq. ) LI c dtswvac d (eq. 8) We clamp d value between 0.0 and ( d ). When d is equal to ( d ), we are in M []. In the NP5, the loop controls the switching frequency by adjusting the end of charge voltage threshold of the t capacitor (see Figure ). The capacitor is charged by a constant current source I t and the threshold voltage V fbint is proportional to the feedback current injected into the pin by the optocoupler. The switching period equation is: TSW tvfbint Ict (eq. 9)

3 V T V Minimum Frequency V fbint 0.5 V Maximum Frequency T SW T SW Figure. The Switching Frequency is ontrolled by the harge of t apacitor NP5 is a current mode converter without ramp compensation. The controller is thus subject to subharmonic oscillations when operating in M. The subharmonic oscillations are modelled by a capacitor connected between and P terminal during M. The capacitor value is frequency dependent and is calculated by the following expression []: S L( FSW) (eq. 0) A separate in line equation disconnects the capacitor during DM. The electrical implementation of all the equations derived above is shown on Figure. Modeling the Section To avoid acoustic noise problems, the NP5 compresses the peak current as the load becomes lighter. From the datasheet, we can extract the values of S current as a function of current. 50 A if Ifb 0 A IS 90 A 9Ifb if 0 A Ifb 80 A 0 A if Ifb 80 A (eq. ) A behavioral current source is used to model I S. The model for the peak current compression is shown on Figure 8. The feedback current controls the switching frequency by changing the timing capacitor end of charge voltage V fbint. To do so, the optocoupler injects current into the pin which is actually a bipolar current mirror input. This current is then adjusted by the feedback loop depending on the operating region (full power, compression or standby). The resulting current flows into a 5 k resistor which develops a voltage proportional to the current. This signal becomes the t capacitor ending voltage. Thus, the relation between feedback current I fb and V fbint is: Vfbint Voffset 5 ki (eq. ) It is also important to model the pin current mirror because the dynamic resistance of the input mirror transistor directly influences the loop gain. Figure shows the way we implemented the model of the modulator. V int V offset 0.5 D N8 Vcl_Vfb B urrent R 5 k l(vlfb) < 80 p 0. : l(vlfb). Vlfb 0 9 X5 NPNV Figure. Feedback Modulator Model

4 omplete Average Model and Application The complete averaged model of NP5 is shown below. A VM I a urrent I(VM)*V(d))/ (V(d)V(d) ) I pk urrent I urrent V(S)/(R sense ) Power Section ( (V(d)V(d))/)* V(c,p)*V(d)*V(T S )/(Lpri) P M = losed M = 0 Open Parameters Lpri = 5 R sense = 0.5 t = 00 p It = 0 = *V(Ts)^/((Lpri)*.8^) Time Variable alculation T S T S Voltage (t)*v(vfb)/(it) d 0.0 dx Voltage V(d)*V(c,p)/ (V(a,c) ) X cl_d 0.99 d d Dx Voltage dx dn d X onfig_ *I(VM)*(Lpri)/(V(d)*V(T S ) *V(a,c) ) V(d) d d 0. d dc d M B state Voltage V(dx) < ( V(d)) 0: Feedback Section Vfb V offset 0.5 D N8 Vcl_Vfb B B B S urrent urrent urrent 9 R l(vlfb) > 0 l(vlfb) < 80 l(vlfb) < 5 k I(V): 90 9*I(Vlfb): 80 p 0. : 50 0 l(vlfb). X5x R NPNV (R S ) Vlfb 0 V 0 V DD V DD Figure 8. omplete Averaged Model of NP5

5 All the elements in Figure 8 are encapsulated into a subcircuit as shown below: 5 A S T S PWM Switch M DM M Figure 9. The PWM Switch Encapsulated into a Sub ircuit P X NP5_av L pri = R sense = 0. R S =.9 k T = 00 p A, and P are the power terminals. is the feedback input. onnect it to optocoupler emitter. The M pin indicates the operating mode (M or DM): T S M PWM Switch M DM V IN 5 A = 0 A S P X XFMR RATIO = 0.5 L (Lpri) V S X5 PWMMTS L pri = 50 R sense = 0.9 R S =.9 k T = 0 p 8 L 0.5 R 0.0 AND880/D R 0.09 out 880 I = if equal to, the converter is in M. if equal to 0, the converter is in DM Ts and S respectively indicate the switching period ( V = s) and the S level. Place voltage probes on the schematic to see their values or display the operation bias points The model expect the values of your primary inductance, sense and S resistors and the value of the timing capacitor t. Defaults values for these parameters are indicated on Figure 9. The Model in a Flyback onverter The following schematic describes the NP5 averaged model implementation in a flyback converter. This schematic can be downloaded from the website. Then, you will just need to enter your own power supply design values in the different components. R load V out V out Rp.5 k Vac A = V 8 9 X Optocoupler pole =.8 n TR = 0.8 V in P 00 n R fb k 0 X TL_G R bias 50 Z 00 n R upper 8 k R lower 0 k Figure 0. The NP5 Model in a Flyback onverter As an example we implemented a V, A flyback converter with secondary output filter. For the feedback, we have chosen a TL, but you can also use a zener diode. R p is the optocoupler pulldown resistor and p places a pole in the compensation transfer function. Typical values for these components are shown on the schematic. We have also represented the ESR of output capacitors to be closer to real application and also because it influences the ac response of the power stage. Validating the Model: Model versus Reality In order to test the model, we built a 0 W buck boost converter with NP5 as the MOSFET controller. The design specifications are: Input voltage: V 0 V dc Output voltage: A As we used a P channel MOSFET for the power switch, the DRV signal from NP5 needs to be inverted. We selected a M5 for that purpose. The output power is regulated with a zener diode and an optocoupler. The optocoupler simplifies the path as we need to pull the up from a negative output voltage. 5

6 X MTD955 D MBRD50T TP R0 0 R 0 Loop Output TP V IN 000 R.9 k 00 p R k X5 NP5 00 n n R. k 00 n R drv 00 k 8 5 M5 Lbb 0 R5 0 8 SFH0A 8 Loop Input D AZ V OUT GND R 0. Figure. The Buck boost Board Application Schematic Shows an Optocoupler in the hain V IN 8. T S M PWM Switch M DM in 000 A S L (Lpri) R 5 m V S X NP5_av P IP V R 0.5 out 0 I = Parameters R S =.9 k L pri = R sense = 0. V out R load 8. V out R8 88 m p Rp k Vac A = X Optocoupler pole =.8 n TR = 0.8 V in 0 R fb 0 D AZ Figure. The Buck boost Model Implemented in SPIE

7 As we said in the previous section, it is important to include the dc resistance of the self and the ESR of the capacitors in the model to better fit reality. Operating Point We ran operating point simulations for different loads. We obtain the following results for the switching period: Load urrent I load Simulated Period T sw Measured Period T sw. A. s. s 0. A s. s 0.09 A. s s In high current conditions, the forward drop voltage in the diode and the ohmic losses in the MOSFET can degrade the bias point as these effects are not taken into account in our model. However, at a low output current, these losses become negligible and the simulation better fits the measurement. Load Step Response We compared the simulated and the measured response for a load step from 0.5 A to. A swept with a slew rate of 0 ma/ s (Figure and Figure ). V out Scale : Y = 0 mv / div, X = ms / div Figure. Simulated Load Step Response The simulated results are very close to measurements. The first voltage peak corresponding to a transition from 0.5 A to. A is well predicted with a simulated value of 80 mv versus 0 mv for the measurement. For a transition from. A to 0.5 A, the model is less precise and the simulation response is 0 mv higher than the measurement. This may come from the internal s capacitor that is brutally disconnected between and P terminal since we are Scale : Y = 0 mv / div, X = ms / div Figure. Measured Load Step Response toggling from M to DM. A solution would be to disconnect this capacitor for transient simulations only. Measuring the Loop Response The loop measurement represents an important task to confirm the validity of the assumptions during the theoretical design stage. The measurement principle is shown below: Power Stage ontroller NP5 SFH0A V OUT R load R 0 R5 0 D AZ Loop Output TP TP Loop Input Isolator Figure 5. Loop Response Measurement Principle Network Analyzer

8 The voltage injection source is implemented with a wide band isolation device together with a 0 ohm resistor. See reference [] for more information about this technique. Voltage probes are used to measure the loop input and output signals with respect to ground on either side of the injection point. Results in M To obtain correct measurements, it is necessary to choose an operating point outside the peak current compression zone. We have selected V in = 8 V and a output current of. A. The switching frequency is khz. The below figures represent the measured and simulated loop gain and phase for a. A output current. Low Frequency Gain : 50 db Gain Phase 0 db Phase Margin :. khz rossover Frequency Figure. Measured Loop Response in M Resonance due to subharmonic oscillations phase gain Low Frequency Gain : 5 db Gain Plot phase in degrees 0 gain in db(volts).0 0 db Phase Margin : Phase khz rossover Frequency 0 00 k 0k 00k frequency in hertz Resonance due to subharmonic oscillations Figure. Simulated Loop Response in M The simulated loop response is very close to reality. We have a variation of 0% between measurement and reality, which is acceptable because what we need is an indication about phase margin (greater than 55) and crossover frequency to be sure we will remain stable in all operating cases. In our example, we have a phase margin smaller than 55. This is clearly not acceptable as a design goal but as our primary aim was to validate the model, we did not pay a particular attention to improve this figure. Results in DM We also compared the simulated and measured loop response in DM for a 0.0 A output current. The input voltage is 8 V and the switching frequency is khz (Figure 8 and Figure 9). 8

9 Low Frequency Gain : 0 db Noise Measurement 0 db Gain Phase Margin : 50 Phase Switching Frequency 0 Hz rossover Frequency Figure 8. Measured Loop Response in M Low frequency Gain 9 db Plot phase_dcm in degrees gain_dcm in db(volts) db Phase Margin 50 Phase Gain rossover Frequency 0 00 Hz k 0k 00k FREQUENY (Hz) Figure 9. Measured Loop Response in DM Again, we have a good correlation between measured and simulated loop response in DM. The error ratio between simulation and measurement is less than %, the model is thus accurate to predict the DM behavior. Here, we have a greater phase margin because the right half plane zero in the control to output transfer function of the buck boost disappears, thus improving the system stability. onclusion An averaged model of NP5 has been derived using the PWM Switch modeling technique. The model has been validated by experimental measurements on a buck boost converter using NP5 as the controller. Several aspects of the model have been tested and compared to measurements: operating point, load step, and loop gain and phase response. There is a good correlation between the model and the measurements. We can conclude that the model is a good tool to predict the small signal response of a NP5 based power supply. This model has been derived using INTUSOFT s IsSpice and ADENE s OrAD. Both versions are uploaded on ON Semiconductor website ( A cycle by cycle model also exists and is available from the same location. 9

10 References. hristophe Basso, The PWM Switch concept included in mode transitioning SPIE models, PIM 005. Vatché Vorpérian, Simplified Analysis of PWM converters using the model of the PWM switch, Part I (M) and II (DM), Transactions on Aerospace and Electronics Systems, Vol, N, May Vatché Vorpérian, Analysis of current mode controlled PWM converters using the model of the current controlled PWM switch, Power onversion October 990 proceedings.. ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any license under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. Box 5, Denver, olorado 80 USA Phone: or Toll Free USA/anada Fax: 0 5 or Toll Free USA/anada orderlit@onsemi.com N. American Technical Support: Toll Free USA/anada Europe, Middle East and Africa Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative AND880/D