Sony ISX014 ¼ Inch 8 Mp, 1.12 µm Pixel Size Exmor RS Stacked Back Illuminated CIS

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1 ¼ Inch 8 Mp, 1.12 µm Pixel Size Exmor RS Stacked Back Illuminated CIS Imager Process Review 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel:

2 Imager Process Review Some of the information in this report may be covered by patents, mask, and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. Chipworks Inc all rights reserved. Chipworks and the Chipworks logo are registered trademarks of Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. IPR JMPJ Revision 1.0 Published: March 28, 2013

3 Imager Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Downstream and Package Overview 2.2 Back of CIS Die Photograph and Die Features 2.3 Front of CIS Die Photograph and Die Features 3 Die Utilization Analysis 3.1 Die Overview 4 Process Analysis 4.1 Overview 4.2 General Structure ISP Die 4.3 General Structure CIS Die 4.4 CIS Substrate and Wells 4.5 CIS Substrate Isolation 4.6 CIS Peripheral Transistors and Poly 4.7 CIS Front Dielectrics 4.8 CIS Front Metallization 4.9 CIS Front Vias and Contacts 4.10 Wafer Bonding Region 4.11 CIS Back Dielectrics and TSVs 4.12 CIS Die Back Metals, Color Filters, and Microlenses 4.13 Bond Pads 5 Pixel Analysis 5.1 Pixel Overview and Schematic 5.2 Pixel Plan-View Analysis 5.3 Pixel Cross-Sectional Analysis Diagonal Across FD and Transfer Gate 5.4 Pixel Cross-Sectional Analysis Parallel to Row Select Lines 5.5 Pixel Cross-Sectional Analysis Parallel to Column Out Lines

4 Imager Process Review 6 Critical Dimensions 6.1 Package Overview 6.2 Die Features 6.3 Image Sensor Substrate and Wells 6.4 Image Sensor Substrate Isolation 6.5 Peripheral Transistors and Poly 6.6 Front Dielectrics 6.7 Front Metallization 6.8 Front Vias and Contacts 6.9 Wafer Bonding and Carrier Wafer 6.10 Back of Substrate Features (Dielectrics, Metals, Color Filters, and Microlenses) 6.11 Pixels 7 References 8 Statement of Measurement Uncertainty and Scope Variation About Chipworks

5 Overview Overview 1.1 List of Figures 2 Device Overview Tablet Computer Front Tablet Computer Back Tablet Computer Back Cover Removed Camera Module Top View Camera Module Bottom View Camera Module Side View Camera Module Markings Camera Module X-Ray Image Side A Camera Module X-Ray Image Side B ISX014 Package Top and Bottom Camera Module Substrate with ISX014 Sensor Secondary Die Camera Module Substrate with ISX014 Sensor X-Ray Top View Die Thickness Back Die Photograph Annotated Back Die Photograph Back Die Photograph Organics Removed TSVs at Corner A TSVs at Corner B TSVs at Corner C TSVs at Corner D Analysis Sites Die Corner A Die Corner B Die Corner C Die Corner D Active Pixel Array Corner Top Left Active Pixel Array Corner Bottom Right Bayer Color Filter Array Pixel Pitch Minimum Pitch Bond Pads Bond Pad Die Corner D Tilt View Die Corner D Tilt-View Detail Wire Bonds Tilt View Bond Pad Tilt View Bond Pad Tilt-View Detail Microlenses Plan View Microlenses Plan-View Detail Microlenses Tilt View

6 Overview Die Corner A Die Corner B Die Corner C Die Corner D CMOS at Corner A Alignment Marks Pixel Array Corner Front of Die Patterns 3 Die Utilization Analysis Annotated Poly Level CIS Die Photograph Column Circuit Capacitors Row Control Structures Row Control and TSV Structures 4 Process Analysis Annotated Poly Level ISP Die Photograph ISP Die General Structure ISP Logic Transistors ISP Minimum Contacted Gate Pitch ISP Minimum Metal 1 Pitch General Structure General Structure Pixel Array General Structure TSVs Die Seal Pixel Array Edge Location L Pixe Array Edge Location R Pixel Array Edge Location T Pixel Array Edge Location B Periphery Region SIMS Profiles Periphery Wells SCM Periphery Wells at TSV SCM Row Control Region Shallow N-Well Si Stain Pixel Array SIMS Profiles Pixel Array Photocathodes SCM Pixel Array Edge SCM Pixel Array Photocathodes Si Stain DTI Minimum Width STI Poly Over STI Peripheral Transistors TEM Transistor Gate TEM Transistor Gate Dielectric TEM Gate Poly Over STI Edge TEM

7 Overview PMD Overview Periphery to Pixel Array Transition Pixel Array PMD TEM Peripheral PMD TEM ILD 1 TEM ILD 2 TEM ILD 3 TEM Passivation Layers SEM Passivation Layers TEM Passivation 1 TEM Minimum Pitch Metal Metal 1 TEM Metal 1 Liner TEM Metal 2 TEM Minimum Pitch Metal Metal 3 TEM Metal 4 TEM Metal 4 Liner TEM Minimum Pitch Metal Pixel Array Contacts TEM Pixel Array Transistor S/D Contact Bottom TEM Periphery Transistor S/D Contact Bottom TEM Minimum Pitch Contacts Minimum Pitch Via 1s and Via 2s Minimum Pitch Via 3s Oxide Bonded CIS and ISP Dies Overview Bonding Interface Region TEM Bonding Interface Region Close-Up TEM Voids at Bonding Interface TEM Shallow and Deep TSVs Shallow TSV TSV Sidewall TSV Double Ta-Based Liner TSV Nitride Liner Back Dielectrics Lower Back Dielectrics TSV at CIS Metal 1 Pad TSV at ISP Metal 7 Pad Shallow to Deep TSV Strap ISX014 Bevel Section SEM TSV Straps Plan-View SEM TSV Straps Close-Up TSVs at CIS Metal 1 Bevel SEM

8 Overview Shallow TSV Pad TSV at ISP Metal 7 Bevel SEM Deep TSV Pad Back Feature Overview Blue and Green Filters Green and Red Filters SEM Bond Pad Overview Bond Pad Edge 5 Pixel Analysis Shared Pixel Schematic Pixel Array Row Connections Pixel Array Column Out Connections Pixels at Metal 4 and Via 3s Pixels at Metal Pixels at Via 2 and Metal Pixels at Metal Pixels at Via 1 and Metal Pixels at Metal Pixels at Poly Pixels at Diffusion Tungsten Aperture Grid Plan View Photocathodes Planar SCM Detailed Photocathodes Planar SCM Photocathodes at Back Surface Planar SCM Transfer Gate and FD Contact TEM Transfer Gate SWS TEM Transfer Gate Dielectric Edge Microlens Shift Row Select and Source Follower Transistors Reset Transistor Row Select and Source Follower Transistors Si Stain Reset Transistor Si Stain Floating Diffusion Si Stain Reset Transistor Gate Width Source Follower Transistor Gate Width Row Select Transistor Gate Width 1.2 List of Tables 1 Overview Key Specifications of the Exmor RS Stacked CISs Key Specifications of the Exmor RS Stacked CIS Camera Modules Device Identification ISX014 Device Summary CIS Process Summary

9 Overview Device Overview Camera Module and CMOS Image Sensor Package Summary Die, Pixel Array, and Pad Dimensions 3 Die Utilization Analysis Die Utilization 4 Process Analysis Substrate and Well Vertical Dimensions Substrate Isolation Critical Dimensions Transistor and Poly Horizontal Dimensions Transistor and Poly Vertical Dimensions Measured Dielectric Thicknesses Front Metallization Thicknesses Front Metallization Width and Pitch Front Via and Contact Dimensions ISP Die and Passivation Vertical Dimensions Back Dielectric Layer Thicknesses TSV Dimensions Back Metals, Color Filters, and Microlens Vertical Dimensions 5 Pixel Analysis Pixel Horizontal Dimensions Pixel Vertical Dimensions Pixel Transistor Dimensions 6 Critical Dimensions Camera Module and CMOS Image Sensor Package Summary Die, Pixel Array, and Pad Dimensions Substrate and Well Vertical Dimensions Substrate Isolation Critical Dimensions Transistor and Poly Horizontal Dimensions Transistor and Poly Vertical Dimensions Measured Dielectric Thicknesses Front Metallization Thicknesses Front Metallization Width and Pitch Front Via and Contact Dimensions ISP Die and Passivation Vertical Dimensions Back Metals, Color Filters, and Microlens Vertical Dimensions Pixel Horizontal Dimensions Pixel Vertical Dimensions Pixel Transistor Dimensions

10 About Chipworks About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at Chipworks 1891 Robertson Road, Suite 500 Ottawa, Ontario K2H 5B7 Canada T F Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com

Apple/AuthenTec TMDR92 iphone 5s, 6, and 6 Plus Fingerprint Sensor

Apple/AuthenTec TMDR92 iphone 5s, 6, and 6 Plus Fingerprint Sensor 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613.829.0414 www.chipworks.com Some of the information in this report may