1 Günhan Dündar Department of Electrical and Electronic Engineering Boğaziçi University Bebek 80815, İstanbul Turkey Tel: (212) / ext Fax: (212) Education  Ph.D., Electrical, Computer, and Systems Engineering Rensselaer Polytechnic Institute, USA Thesis: CMOS VLSI Design of Analog Neural Networks.  M.S., Electrical and Electronic Engineering Boğaziçi University, Turkey. Thesis: A Comparative Evaluation of Edge Detectors and Preprocessing Algorithms.  B.S., Electrical and Electronic Engineering Boğaziçi University, Turkey. Awards The Vehbi Koç foundation award for the first 20 in the university entrance exam ( ) Boğaziçi University Research Fund Award (1996) Boğaziçi University Foundation Encouragement Award (2000, 2001,2002,2003) Boğaziçi University Foundation Young Researcher Award (2002) Best Paper Award at the 19th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Leuven, Belgium. (2008)
2 Experience - 5/2002 present: Full Professor, Boğaziçi University - 9/2002 6/2003: Invited Professor, EPFL. - 4/97 5/2002: Associate Professor, Boğaziçi University. Taught VLSI Design, Advanced VLSI Design, Computational VLSI, Electronic Circuits I and II, Electronics Laboratory, and Neural Networks. - 6/96 4/97: Assistant Professor, Boğaziçi University. Taught a graduate course in computational VLSI and a second course in electronic circuits for junior level students. - 1/94-6/96: Instructor, Boğaziçi University, Department of Electrical and Electronic Engineering. Taught graduate courses on microelectronic design, computational aspects of VLSI design, and semiconductor device theory. Taught undergraduate courses on introductory electronics for both electrical engineering and computer engineering students. Conducted electronic circuit labs. - 11/94-12/95: Instructor, Naval Academy, taught Electronics Lab 1, Signals and Systems, Electronics Lab 2, and Digital Electronics. - 8/94-12/95: Military service with the Turkish Navy. - 1/94-6/94: Instructor, Air Force Academy, taught a course in Computer Networks. - 7/90-7/91: Teaching Assistant, Boğaziçi University, Turkey. Held counseling hours for 5 junior/senior level courses on electronic circuits, digital electronic circuits and communication circuits. Instructed three electronics lab classes. - 12/87-1/88: Trainee Engineer, Ekacomp, İstanbul. Worked in the servicing of microcomputers. - 8/87-8/87: Trainee Engineer, Grundig, İstanbul. - 6/87-8/87: Trainee Engineer, Philips, İstanbul. Worked in designing test benches for TV sets. Areas of Research Interest - Analog IC design - Architectural modeling and circuit design of DSP and image processing systems. - Design of analog neural networks - Electronic design automation - Image processing and data compression algorithms
3 Research Projects Conducted to Completion - A Design automation and modeling system for A/D Converters, for TÜBITAK (The Scientific and Technical Research Council of Turkey), Project No:101E039, Implementation of artificial neural networks with analog integrated circuits, for TÜBITAK (The Scientific and Technical Research Council of Turkey), Project No:EEEAG-183, ALG: An Analog Layout Generator, for Boğaziçi University Research Fund, Technical Training - NATO ASI on Computational Intelligence, Turkey, August NATO ASI on System Level Synthesis, Italy, August RF Circuit Design for Wireless Communications, Switzerland, July Administrative and Academic Services - Member of the Curriculum, Faculty Search, PhD administration, and Technical Support Committees, Department of Electrical and Electronic Engineering, Boğaziçi University, 1998-present. - Member of KOSGEB (Small Scale Industry Development Support) Evaluation Committee, Boğaziçi University, 1998-present. - Member of BİM (Computing Facilities) Committee ( ), Boğaziçi University. - Member of Boğaziçi University Press Committee (2004-present). - Vice Chairman of the Electrical and Electronic Engineering Department, Boğaziçi University, ( ). - Chairman of the Electrical and Electronic Engineering Department, Boğaziçi University, (2006-present). - Member of Boğaziçi University ÖYP Committee (2006 present). - Member of Boğaziçi University Foundation Academic Committee ( ).
4 Conferences Organized - Turkish Artificial Intelligence and Neural Networks Symposium, June 1999 (TAINN 1999). - PhD Research in Microelectronics and Electronics, June 2008 (PRIME 2008). Seminars and Invited Talks - G. Dündar: ANNSyS An Analog Neural Network Synthesis System, University of Genoa, Genoa, Italy, August G. Dündar: Non-idealities and component variations in analog neural networks, Georgia Institute of Technology, Atlanta, Georgia, USA, August G. Dündar: Design automation of analog integrated circuits, EPFL, Lausanne, Switzerland, October Courses to the Industry - S. Balkır and G. Dündar: Design Automation of Digital Circuits Using Mentor Graphics Software, Havelsan, İstanbul, 1996.
5 M.S. Theses Conducted to Completion - Top-down Design of CMOS Based Subsystems for DSP. Student: Hakan Binici, Co-advisor: Sina Balkır, Date: Circuit Simulation Based Training Algorithms for Analog Neural Networks. Student: İsmet Bayraktaroğlu, Co-advisor: Sina Balkır, Date: VLSI Implementation of a Neural Network Based Fuzzy Logic Controller. Student: Mustafa Sözer, Date: VLSI Implementation of a New Standard for Lossless Compression of Continuous Tone Still Images. Student: A. Suat Aktürk, Co-advısor: Sina Balkır, Date: Analog VLSI Implementation of Wavelet Transforms Using Switched Capacitor Filters. Student: Gürkan Sönmez, Co-advisor: Sina Balkır, Date: Amendment of Firing Mechanisms of Destructors Based on Development of Software and All Digital Circuitry. Student: İhsan Bakar, Co-advisor: Ömer Cerid, Date: Amendment of Firing Mechanisms of Destructors Based on Development of Hardware Solid State Sensors and All Analog Interfacing Circuitry. Student: Ayhan Bay, Co-advisor: Ömer Cerid, Date: ALG: An Analog Layout Generator. Student: Altuğ Şimşek, Co-advisor: Sina Balkır, Date: A Fast and Accurate Delay Estimation Method for Adders as CMOS Arithmetic Building Blocks in VLSI Design. Student: Gökhan Karakuş, Co-advisor: Sina Balkır, Date: An Optimized Method for the Estimation of Power Dissipation ın Adders as CMOS Arithmetic Building Blocks. Student: Arsal Dikel, Co-advisor: Sina Balkır, Date: Design of a High Resolution ADC. Student: Serhan Eröz, Co-advisor: Sina Balkır, Date: VLSI Implementation of a Secure Communication System Using Current-Mode Chaotic Circuits Student: Sedat Nişancı, Co-advisor: Sina Balkır, Date: Design of a Microcontroller Board and Development of Software for Ultrasonic Radar Student: Nilüfen Çotuk, Co-advisor: Ömer Cerid, Date: Hardware Implementation of Ultrasonic Radar System and Microcontroller Interfacing Student: Levent Bektaş, Co-advisor: Ömer Cerid, Date: Feedforward Neural Network Optimization Suitable for Hardware Implementation Student: Devrim Albuz, Date: Traffic Modeling in ATM Switches Using Neurofuzzy Methods Student: Amer Çatoviç, Co-advisor: Sema Oktuğ, Date: High-Level Synthesis of Analog Circuits Student: İ. Gökhan Erten, Co-advisor: Sina Balkır, Date: Performance Comparison of Viterbi Decoders
6 Student: Levent Çetrez, Date: Performance Estimation in Analog CAD Student: İ. Faik Başkaya, Date: Theoretical Prediction of Parameter Quantization Effects in Gaussian Potential Function Neural Networks Student: Erkan Karakuş, Date: Architectures and Implementations for Speech Enhancement Student: Gökhan Coşgül, Date: Weight Quantization for Multilayer Perceptrons Student: Fatih Köksal, Co-advisor: Ethem Alpaydın, Date: Logic Level Power Estimation in CMOS VLSI Circuits Student: Mustafa Aktan, Date: High Level Modeling and Optimization of A/D Converters Student: Selçuk Talay, Date: Design and Implementation of 3.2 Gbps LVDS Receiver Student: Erdem Karaadam, Date: An Optimization-based Hierarchical Design Automation System Student: Öszun Serkan Sönmez, Date: An Analog Performance Estimation System Based on BSIM Models Student: Balkır Kayaaltı, Date: A Layout advisor for Analog Layouts Student: Mehmet Selçuk Ataç, Date: A Single-chip solution for text-to-speech synthesis Student: Ozan Aktan, Date: Development of a library for CMOS analog neural networks Student: Mustafa Taşkaldıran, Date: Analog Design automation System Performance Estimation Student: Engin Deniz, Date: A Study of phase noise in differential CMOS LC Voltage Controlled Oscillators Student: Oktay Güryay, Date: An Analytical modeling approach to the design of PLL s Student: Şeref Ersin Ak, Date: Analog Layout Generation Student: Ender Yılmaz, Date: Analog Design and Optimization of PWL circuits used in fuzzy logic solutions Student: Yankı Yalçın, Date: Power Analysis and Low Power Realization of Digital Filter Structures. Student: Okan Zafer Batur, Date: 2006.
7 PhD Theses Conducted to Completion - A Silicon Compiler for Multirate DSP Systems Student: Arda Yurdakul, Co-advisor: Sabih Tansal, Date: Multilayer Perceptron Neural Networks in Analog VLSI A System Level Study Student: A. Selçuk Öğrenci, Co-advisor: Sina Balkır, Date: A New Approach to Analog Integrated Circuit Optimization Student: Güner Alpaydın, Co-advisor: Sina Balkır, Date: Analysis and Modeling of Multi-gate MOSFET Structures Student: Koray Karahaliloğlu, Date: Hardware/Software Partitioning for Custom Instruction Processors Student: Kubilay Atasu, Co-Advisor: Can Özturan, Date: High Level Power Efficient Synthesis of FIR Based Digital Systems Student: Mustafa Aktan, Date High Level Modeling of Sigma-Delta Analog to Digital Converters Student: Selçuk Talay, Date:2008 Personal Information Birth Place and Date: Istanbul, 1969 Marital Status: Married Children: Two Foreign Languages: English (fluent), German (medium), Italian (beginner), French (beginner). Nationality: Turkish
8 Journal Publications 1. E. Yılmaz and G. Dündar, Analog layout generator for CMOS circuits, IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, Vol.28, No. 1, pp , January S. Talay, E. Deniz, G. Dündar, A Sigma-Delta ADC design automation tool with embedded performance estimator, Integration the VLSI Journal, Vol. 42, No. 1, pp , January B.M. Wilamowski, N.J. Cotton, O. Kaynak, and G. Dündar, Computing gradient vector and Jacobian matrix in arbitrarily connected neural networks, IEEE Transactions on Industrial Electronics, Vol. 55, No. 10, pp , October J.D. Hewlett, B.M. Wilamowski, and G. Dündar, Optimization using a modified second-order approach with evolutionary enhancement, IEEE Transactions on Industrial Electronics, Vol. 55, No. 9, pp , Sept M. Aktan, A. Yurdakul, and G. Dündar, An algorithm for the design of low-power hardware efficient FIR filters, IEEE Transactions on Circuits and Systems I, Vol. 55, No. 6, pp , K. Atasu, C. Özturan, G. Dündar, O. Mencer, and W. Luk, CHIPS: Custom Hardware Instruction Processor Synthesis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 3, pp , K. Karahaliloğlu and G. Dündar, An explicit current model for dual gate MOSFET, Solid State Electronics, Vol. 47, No. 11, pp , G. Alpaydın, S. Balkır, and G. Dündar, An evolutionary approach to automatic synthesis of high performance analog integrated circuits, IEEE Transactions on Evolutionary Computing, Vol. 7, No. 3, pp , S. Minaei, O. Cicekoglu, H. Kuntman, G. Dündar, and O. Cerid, New realizations of current-mode and voltage-mode multifunction filters without external passive elements, AEU-International Journal Of Electronics And Communications, Vol. 57, No. 1, pp , January A. Yurdakul and G. Dündar, Fast and efficient algorithm for the multiplierless realization of linear DSP transforms, IEE Proceedings Circuits, Devices, and Systems, Vol. 149, No. 4, pp , August G. Alpaydın, G. Dündar, and S. Balkır, Evolution based design of neural fuzzy networks using self-adapting genetic parameters, IEEE Transactions on Fuzzy Systems, Vol. 10, No. 2, pp , April A. Chatovich, S. Oktuğ, and G. Dündar, Hierarchical neuro-fuzzy call admission controller for ATM networks, Computer Communications, Vol. 24, No. 11, pp , June A. S. Öğrenci, G. Dündar, and S. Balkır, Fault tolerant training of neural networks in the presence of MOS transistor mismatches, IEEE Transactions on Circuits and Systems, Vol. 48, No.3, pp , March G. Alpaydın, G. Erten, S. Balkır, and G. Dündar, Multi-level optimization approach to switched capacitor filter synthesis, IEE Proceedings Circuits, Devices, and Systems, Vol. 147, No. 4, pp , August B. E. Sağlam, G. Coşgül, and G. Dündar, Comments on a systematic approach for design of digit-serial signal processing architectures, IEEE Transactions on Circuits and Systems -II, Vol. 47, No. 4, pp , April E. Yazıcıoğlu, S. Balkır, G. Dündar, and H. Çağlar, Implementation of a new orthogonal shuffled block transform for image coding applications, Journal of Real Time Imaging, Vol. 6, No. 1, pp , February 2000.
9 17. A. Yurdakul and G. Dündar, Multiplierless realization of linear DSP transforms by using common two-term expressions, Journal of VLSI Signal Processing, Vol. 22, No. 3, pp , September A. Yurdakul and G. Dündar, Statistical methods for the estimation of quantization effects and determination of optimal quantization stepsize in FIR-based multirate systems, IEEE Transactions on Signal Processing, Vol. 47, No. 6, pp , June İ. Bayraktaroğlu, A.S. Öğrenci, G. Dündar, S. Balkır, and E. Alpaydın, ANNSyS: An Analogue Neural Network Synthesis System, Neural Networks, Vol. 12, No. 2, pp , March A. Şimşek and G. Dündar, An application of self organizing neural networks to circuit partitioning, ELEKTRİK, Turkish Journal of Electrical Engineering and Computer Sciences, Vol. 4, Supplement, pp , G. Dündar, F-C. Hsu, and K. Rose, Effects of nonlinear synapses on multilayer neural networks, Neural Computation, Vol. 8, No. 5, pp , July G. Dündar and K. Rose, Comparing models for the growth of silicon-rich-oxides (SRO), IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 1, pp , Feb G. Dündar and K. Rose, The effects of quantization on multilayer neural networks, IEEE Transactions on Neural Networks, Vol. 6, No. 11, pp , Nov Ö. Cerid, S. Balkır, and G. Dündar, Novel CMOS reference current generator, International Journal of Electronics, Vol. 78, No. 6, pp , June Ö. Cerid, S. Balkır, and G. Dündar, Design automation of digital integrated circuits, Hava Harp Okulu Bülteni, Vol. 13, No. 36, pp , July 1994 (in Turkish). 26. Ö. Cerid, S. Balkır, and G. Dündar, Structural modeling and simulation of pipelined radix-2 n multipliers, Hava Harp Okulu Bülteni, Vol. 13, No. 35, pp , April 1994 (in Turkish).
10 Conference Publications 1. A. Çelebi, O. Urhan, S. Ertürk, İ. Hamzaoğlu, and G. Dündar, MVBLA based design of Constrained 1-bit Transform based motion estimation algorithm, Proceedings of SIU 2008, April 2008, Ankara, Turkey (in Turkish). 2. Y. Yalçın, G. Dündar, and B.M. Wilamowski, Design and optimization of PWL circuits used in fuzzy logic hardware, Proceedings of PRIME 08, pp , June 2008, Istanbul, Turkey. 3. E. Deniz and G. Dündar, Hybrid approach for performance estimation; embedded tool for analog design automation systems, Proceedings of PRIME 08, pp. 5-8, June 2008, Istanbul, Turkey. 4. B. Kayaaltı, Ö. Cerid, and G. Dündar, A design methodology for asynchronous sigma-delta converters, Proceedings of PRIME 08, pp , June 2008, Istanbul, Turkey. 5. O.Z. Batur, M. Koca, and G. Dündar, Measurements of impulsive noise in broad-band wireless communication channels, Proceedings of PRIME 08, pp , June 2008, Istanbul, Turkey. 6. K. Atasu, O. Mencer, W. Luk, C. Özturan, and G. Dündar, Fast custom instruction identification by convex subgraph enumeration, Proceedings of ASAP 2008, 2-4 July 2008, Leuven Belgium. 7. M. Aktan, G. Dündar, and M. Koca, Low-Power hardware efficient MMSE equalizer design, Proceedings of ICCSC 08, pp , May 2008, Shanghai, China. 8. N.J. Cotton, B.M. Wilamowski, and G. Dündar, A Neural network implementation on an inexpensive eight bit microcontroller, Proceedings of INES 2008, pp , February 2008, Miami, FL. 9. O. Aytar, A. Tangel, and G. Dündar, A 9-bit 1GS/S CMOS folding ADC implementation using TIQ based flash ADC cores, Proceedings of MIXDES 2008, pp , June 2008, Poznań, Poland. 10. U, Yapar and G. Dündar, Current-mode circuits for sigma-delta converters, Proceedings of ECCTD 07, pp , August , Sevilla, Spain. 11. E. Yılmaz and G. Dündar, New layout generator for analog CMOS circuits, Proceedings of ECCTD 07, pp , August , Sevilla, Spain. 12. W.M. Anderson, B.M. Wilamowski, and G. Dündar, Wide Band tunable filter design implemented in CMOS, Proceedings of INES 07, pp , June 29-July , Budapest, Hungary. 13. A. Çelebi, O. Urhan, S, Ertürk, and G. Dündar, Implementation of constrained 1-bit transform based motion estimation algorithm with an FPGA based architecture, Proceedings of SIU 2007, June , Eskişehir, Turkey (in Turkish). 14. J. Hewlett, B. Wilamowski, and G. Dündar, Merge of evolutionary computation with gradient based method for optimization problems, Proceedings of ISIE 07, pp , June , Vigo, Spain. 15. B.M Wilamowski, N.J. Cotton, O. Kaynak, and G. Dündar, Method of computing gradient vector and Jacobean matrix in arbitrarily connected neural networks, Proceedings of ISIE 07, pp , June , Vigo, Spain 16. Y. D. Gökdel, S. Talay, and G. Dündar, Adaptive high performance Σ modulator designs, Proceedings of PRIME 07, pp , July , Bordeaux, France.
11 17. K. Atasu, R. Dimond, O. Mencer, W. Luk, C. Özturan, and G. Dündar, Optimizing instruction-set extensible processors under data-bandwidth constraints, Proceedings of DATE 07, April 2007, Nice, France. 18. Ö. Yetik, M. O. Sağlamdemir, S. Talay, and G. Dündar, A coefficient optimization and architecture selection tool for Σ modulators in MATLAB, Proceedings of DATE 07, April 2007, Nice, France. 19. M. O. Sağlamdemir, Ö. Yetik, S. Talay, and G. Dündar, A coefficient optimization and architecture selection tool for SD modulators considering component nonidealities, Proceedings of GLSVLSI 07, pp , March 11-13, 2007, Stresa, Italy. 20. U. Yazkurt, G. Dündar, S. Talay, N. Beilleau, H. Aboushady, and L. de Lamarre, Scaling input signal swings of overloaded integrators in resonator-based sigma-delta modulators, Proceedings of ICECS 06, pp , Dec , 2006, Nice, France. 21. Y.D. Gökdel, S. Talay, G.Dündar and A. Meriç, High Performance Sigma-Delta ADC with adaptive gain controller Proceedings of ELECO 06, 6-10 December 2006, Bursa, Turkey. 22. S. Talay, E. Deniz, and G. Dündar, A Sigma-Delta ADC design automation tool with embedded performance estimator, Proceedings of MIXDES 06, pp , June , Gdynia, Poland. 23. E. Yılmaz and G. Dündar, A New performance oriented module generator, Proceedings of MIXDES 06, pp , June , Gdynia, Poland. 24. B. Koç, A. Koukab, and G. Dündar, Phase noise in bipolar and CMOS VCO s an analytical comparison, Proceedings of ISCAS 06, pp , May , KOS, Greece. 25. B.M. Wilamowski, M.E. Sinangil, and G. Dündar, A Gray-Code current mode ADC structure, Proceedings of IEEE MELECON, May , Benalmadena, Spain. 26. O. Aktan, İ.F. Başkaya, and G. Dündar, A single chip solution for text-to-speech synthesis, Proceedings of ECCTD 05, pp. III/449 III/452, August 29-September 2, 2005, Cork City, Ireland. 27. E. Deniz and G. Dündar, MOSFET modeling with EKV 2.6 and analog circuit design strategy for performance estimation tool, Proceedings of ELECO 05, pp , 7-11 December 2005, Bursa, Turkey. 28. Ö. Gürsoy, O. Sağlamdemir, M. Aktan, S. Talay, and G. Dündar, Low power decimation filter architectures for sigma-delta ADC s, Proceedings of ELECO 05, pp , 7-11 December 2005, Bursa, Turkey. 29. E. Deniz and G. Dündar, Peformance estimator for an analog design automation system using EKV modeled analog circuits, Proceedings of ECCTD 05, pp. II/119 II/122, August 29-September 2, 2005, Cork City, Ireland. 30. K. Atasu, G. Dündar, and C. Özturan, An integer linear programming approach for identifying instruction set extensions, Proceedings of CODES+ISSS 05, Sept , 2005, Jersey City, New Jersey. 31. M. Aktan and G. Dündar, Design of digital filters for low power applications using integer quadratic programming, Proceedings of PATMOS 05, pp , Sept 21-23, S. Talay and G. Dündar, A Sigma-Delta ADC design automation tool, Proceedings of PRIME 2005, pp , July , Lausanne, Switzerland. 33. S. Talay and G. Dündar, A Pipeline ADC Design with an ADC design automation system, Proceedings of ELECO 2004, pp , Dec. 8-12, 2004, Bursa, Turkey (in Turkish). 34. M. Taşkaldıran and G. Dündar, Development of a library for CMOS analog neural networks, Proceedings of TAINN 2004, pp , June , İzmir, Turkey. 35. S. Talay and G. Dündar, Slew rate effects in first order sigma-delta ADC s, Proceedings of MELECON 2004, pp , May , Dubrovnik, Croatia.
12 36. İ.F. Başkaya, O. Aktan, and G. Dündar, Text-to-speech integrated circuit, Proceedings of SIU 2004, pp , April , Kuşadası, Turkey (in Turkish). 37. M. Aktan, U. Çini, and G. Dündar, Design of digital filters for low-power applications by reducing the Hamming distance of the filter coefficients using mean fied annelaing algorithm, Proceedings of SIU 2004, pp , April , Kuşadası, Turkey (in Turkish). 38. S. Talay and G. Dündar, Jitter model of sigma-delta converters, Proceedings of SIU 2004, pp , April , Kuşadası, Turkey (in Turkish). 39. S. Talay and G. Dündar, High speed design tool for flash and pipeline ADC s, Proceedings of ECCTD 03, pp. II-213 II-216, Sept , Cracow, Poland. 40. S. Talay and G. Dündar, Modeling of Sigma-Delta converters in MATLAB, Proceedings of SIU 2003, pp , June 18-20, 2003, İstanbul, Turkey (in Turkish). 41. H. Sunar, G. Dündar, and E. Anarım, IC Realization of multiwavelet filters, Proceedings of SIU 2002, pp , June 12-14, 2002, Pamukkale, Turkey. (in Turkish) 42. G. Tulunay, G. Dündar, and A. Ataman, A new approach to modeling statistical variations in MOS transistors, Proceedings of ISCAS 2002, pp. I-757 I-760, May 26-29, 2002, Phoenix, Arizona. 43. G. Alpaydın, S. Balkır, and G. Dündar, Evolution based automatic synthesis of analog integrated circuits, Proceedings of ISCAS 2002, pp. II-65 II-68, May 26-29, 2002, Phoenix, Arizona. 44. K. Karahaliloğlu and G. Dündar, Analytical current model for dual gate MOSFET, Proceedings of ICECS 2001, pp , September 2-5, 2001, Malta. 45. İ. F. Başkaya and G. Dündar, Performance estimation in analog computer aided design, Proceedings of ECCTD 2001, pp.ii-117 II-120, August 28-31, 2001, Espoo, Finland. 46. F. Köksal, E. Alpaydın, and G. Dündar, Weight quantization for multilayer perceptrons using soft weight sharing, Proceedings of ICANN 2001, pp , August 21-25, 2001, Vienna, Austria. 47. E. Karakuş, A. S. Öğrenci, and G. Dündar, Parameter quantization effects in Gaussian potential function neural networks, Advances in Neural Networks and Applications, pp , February 11 15, 2001, Puerto de la Cruz, Spain. 48. D. Albuz, A.S. Öğrenci, and G. Dündar, Using sensitivity analysis for weight quzntization, Proceedings of TAINN 2000, pp , June 21-23, 2000, İzmir, Turkey. 49. F. Köksal, E. Alpaydın, and G. Dündar, Weight quantization for multilayer perceptrons, Proceedings of TAINN 2000, pp , June 21 23, 2000, İzmir, Turkey. 50. İ.C. Çevikbaş, A.S. Öğrenci, G. Dündar, and S. Balkır, VLSI implementation of GRBF (Gaussian Radial Basis Function) networks, Proceedings of ISCAS 00, pp. III-646 III-649, May 28 31, 2000, Geneva, Switzerland. 51. G. Alpaydın, G. Coşgül, G. Dündar, and S. Balkır, Fuzzy performance model of mismatch for analog integrated circuit optimization, Proceedings of ECCTD 99, pp , Aug. 30 Sept. 2, 1999, Stresa, Italy. 52. S. Nişancı, G. Dündar, S. Balkır, and Y. Denizhan, IC design for secure communication using current-mode chaotic circuits, Proceedings of ECCTD 99, pp , Aug. 30 Sept. 2, 1999, Stresa, Italy. 53. G. Alpaydın, G. Erten, S. Balkır, and G. Dündar, Synthesis of switched capacitor filters in a multi-level optimization environment, Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, pp , July 26-28, 1999, Puerta Vallarta, Mexico.
13 54. G. Erten, G. Dündar, and, S. Balkır, Optimization and synthesis of switched current filters with non-ideal MOS transistors, Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, pp , July 26-28, 1999, Puerta Vallarta, Mexico. 55. A. Çatoviç, S. Oktuğ, and G. Dündar, Hierarchical neuro-fuzzy call admıssıon controller for ATM networks, Proceedings of IFIP 99, June 28-30, Antwerp, Belgium. 56. G. Alpaydın, G. Dündar, and S. Balkır, Optimization of neural fuzzy networks, Proceedings of TAINN 99, pp , June 23-25, 1999, Istanbul, Turkey. 57. G. Coşgül, A. S. Öğrenci, and G. Dündar, Neural network based CAD tool for modeling manufacturing variations in MOS devices, Proceedings of TAINN 99, pp , June , Istanbul, Turkey. 58. A. S. Öğrenci, M. Becer, G. Dündar, and S. Balkır, Incorporating MOS transistor mismatches into training of analog neural networks, Proceedings of NC 98, pp , Sept. 1998, Vienna, Austria. 59. İ. F. Başkaya and G. Dündar, Test pattern generation for VLSI neural networks, Proceedings of TAINN 98, pp , June 24-26, 1998, Ankara, Turkey. 60. A. Yurdakul and G. Dündar, Multiplierless realization of FIR-based multirate systems by using common twoterm expressions, Proceedings of SIU 98, Vol. 2, pp , May 28-30, 1998, Kızılcahamam, Turkey. (in Turkish). 61. G. Hafız, G. Dündar, S. Balkır, and L. Akın, Optimization of analog integrated circuits via simulated annealing and evolutionary strategies, Proceedings of ECCTD 97, pp , Sept. 1-4, 1997, Budapest, Hungary. 62. İ. Bayraktaroğlu, A. S. Öğrenci, G. Dündar, S. Balkır, and E. Alpaydın, ANNSyS: An Analog Neural Network Synthesis System, Proceedings of ICNN 97, Vol 2, pp , June 9-13, 1997, Houston, Texas. 63. İ. G. Erten, A. S. Öğrenci, and G. Dündar, A compaction algorithm for SAFANN, Proceedings of TAINN 97 (New Trends in Artificial Intelligence and Neural Networks), pp , May 22-23, 1997, Kızılcahamam, Turkey. 64. E. Yazıcıoğlu, G. Dündar, S. Balkır, and H. Ça lar, VLSI Design of shuffled block transform and inverse transform architectures, Proceedings of SIU 97, Vol. 2, pp , May 1-3, 1997, Kuşadası, Turkey. (in Turkish) 65. A. Yurdakul and G. Dündar, The effects of finite wordlength on FIR filters and the reflection on multiresolution systems, Proceedings of SIU 97, Vol. 2, pp , May 1-3, 1997, Kuşadası, Turkey. (in Turkish). 66. A. S. Öğrenci, G. Dündar, S. Balkır, and E. Alpaydın, Training of multilayer neural networks with non-linear multipliers from analog integrated circuits, Proceedings of SIU 97, Vol. 2, pp , May 1-3, 1997, Kuşadası, Turkey. (in Turkish). 67. İ. Bayraktaroğlu, A. S. Öğrenci, G. Dündar, and S. Balkır, On-chip training by software for analog neural networks using ANNSyS, Proceedings of the 6th NASA Symposium on VLSI Design, pp , March 5-6, İ. Bayraktaroğlu, S. Balkır, and G. Dündar, A circuit level simulator for analog neural networks, Proceedings of the 5th Turkish Symposium on Artificial Intelligence and Neural Networks, pp , June 27-28, A. Şimşek and G. Dündar, An application of self organizing neural networks to circuit partitioning, Proceedings of the 5th Turkish Symposium on Artificial Intelligence and Neural Networks, pp , June 27-28, A. S. Öğrenci and G. Dündar, SAFANN: Silicon Assembler for Analog Neural Networks, Proceedings of the 5th Turkish Symposium on Artificial Intelligence and Neural Networks, pp , June 27-28, 1996.
14 71. A. Yurdakul and G. Dündar, A new hybrid algorithm for over the cell routing, Proceedings of Melecon 96, Vol. III, pp , May 13-16, 1996, Bari. 72. Ş. Özev, A. Altınordu, and G. Dündar, Implementation of a radix-2n multiplier using high performance logic, Proceedings of Melecon 96, Vol. III, pp , May 13-16, 1996, Bari. 73. A. Şimşek, M. Civelek, and G. Dündar, Study of the effects of nonidealities in multilayer analog neural networks with circuit level simulation, Proceedings of Melecon 96, Vol. I, pp , May 13-16, 1996, Bari. 74. Y. Atabek, G. Dündar, S. Balkır, H. Çağlar, and E. Anarım, Design of M-band wavelet filter with perfect reconstruction architecture, Proceedings of the International Conference on Telecommunications, pp , April 14-17, G. Elbek, S. Balkır, and G. Dündar, Design and simulation of a two band three level wavelet decomposition architecture using folding algorithm, Proceedings of the International Conference on Telecommunications, pp , April 14-17, Y. Atabek, G. Dündar, S. Balkır, H. Çağlar, and E. Anarım, Design of M-band analysis and perfect reconstruction filters, Proceedings of SIU 96, Kemer, Türkiye, pp , April 5-6, 1996 (in Turkish). 77. G. Elbek, S. Balkır, and G. Dündar, Design and VLSI realization of a two band three level wavelet decomposition architecture, Proceedings of SIU 96, Kemer, Türkiye, pp , April 5-6, 1996 (in Turkish). 78. H. Binici, G. Dündar, and S. Balkır, A new multiplier based on radix-2 conversion scheme, Proceedings of the European Conference on Circuit Theory and Design, pp , August S. Gören, S. Balkır, G. Dündar, and E. Anarım, Novel VLSI architectures for morphological filtering Proceedings of the IEEE Workshop on Morphological Signal Processing, pp , June 22, S. Gören, S. Balkır, G. Dündar, and E. Anarım, Novel VLSI architectures for morphological filtering, Proceedings of SIU 95, Nevşehir, Türkiye, Book A. Image Processing, pp , April 26-28, 1995 (in Turkish). 81. Y. Atabek, G. Dündar, S. Balkır, H. Çağlar, and E. Anarım, A novel architecture for M-band wavelet transforms, Proceedings of SIU 95, Nevşehir, Türkiye, Book B, Signal Processing, pp , April 26-28, 1995 (in Turkish). 82. G. Dündar and S. Balkır, Design and simulation of a wavelet decomposition architecture, Proceedings of the 6th International Conference on Microelectronics, pp , Sept. 5-7, S. Balkır, G. Dündar, and Ö. Cerid, Hardware modeling of wavelet architectures with VHDL, Proceedings of SIU 94, Gökova, Türkiye, April 8-9, 1994, pp (in Turkish). 84. G. Dündar and K. Rose, Analog neural network circuits suitable for ASIC fabrication, Proceedings of the IEEE ASIC Conference, Rochester, NY, 1992, pp T. Aydın, G. Dündar, E. Anarım, and Ö. Cerid, A comparative evaluation of edge detectors and improvement of edge detectors via preprocessing in the presence of noise, Trezième Colloque Gretsi, Juan-les-Pins, France, 1991, pp
15 Other Publications 1. A. Yurdakul and G. Dündar, Statistical methods for the estimation of quantization effects in FIR-based multirate systems, Technical Report FBE-EE-01/97-09, Boğaziçi University, G. Dündar and K. Rose, Neural Chips, Encyclopedia of Electrical Engineering, Vol. 14, pp , John Wiley, G. Dündar, Implementation of artificial neural networks with analog integrated circuits, Project report for TÜBİTAK (The Scientific and Technical Research Council of Turkey), Project Report No: EEEAG-183, 1998.
16 Books - S. Balkır, G. Dündar, and A. S. Öğrenci, Analog VLSI Design Automation, CRC Press, 2003.
17 Papers in Review 1. O. Sağlamdemir, Ö. Yetik, S. Talay, G. Dündar, System Level Synthesis of SD ADC's with Architecture Generation, Analog Integrated Circuits, in review. 2. Ö. Sönmez, G. Dündar, Simulation-based Analog and RF Circuit Synthesis Using a Modified Evolutionary Strategies Algorithm, IEEE Transactions on Evolutionary Computation, in review. 3. B. Sarıoğlu, G. Dündar, B. Wilamowski, A nuerofuzzy chip design, IEEE Transactions on Fuzzy Systems, in review.
Curriculum Vitae Full Name: Date & Place of Birth: Office Contact: Dr. Recai KILIÇ 01 August 1973, Gümüşhane, TURKEY. Dept. of Electrical&Electronics Eng., Faculty of Engineering, Erciyes University, Kayseri,
NATIONAL SUN YAT-SEN UNIVERSITY Department of Electrical Engineering (Master s Degree, Doctoral Program Course, International Master's Program in Electric Power Engineering) Course Structure Course Structures
MASTER OF SCIENCE IN ELECTRICAL ENGINEERING (MS EE) FIRST YEAR Elective 3 Elective 3 Elective 3 Seminar Course (EE 296) 1 TOTAL 12 TOTAL 10 SECOND YEAR Major Subject 3 Thesis (EE 300) 3 Thesis (EE 300)
A -GSPS CMOS Flash A/D Converter for System-on-Chip Applications Jincheol Yoo, Kyusun Choi, and Ali Tangel Department of Computer Science & Department of Computer & Engineering Communications Engineering
Bright and dark sides of computational intelligence Bogdan M. Wilamowski Auburn University Electrical and Computer Engineering, Auburn University, 420 Broun Hall, Auburn, Alabama, USA Abstract: The paper
CURRICULUM VITAE PERSONAL DATA Name: Dimokritos Panagiotopoulos Date of birth: March 21, 1960 Family Status: Married, has two children Current Posistion: Work Address: Tel. No. (Work): Mobile No.: E-mail:
BSEE Degree Plan Bachelor of Science in Electrical Engineering: 2015-16 Freshman Year ENG 1003 Composition I 3 ENG 1013 Composition II 3 ENGR 1402 Concepts of Engineering 2 PHYS 2034 University Physics
Implementation of emulated digital CNN-UM architecture on programmable logic devices and its applications Theses of the Ph.D. dissertation Zoltán Nagy Scientific adviser: Dr. Péter Szolgay Doctoral School
The Master s Degree Program in Electrical and Computer Engineering M. Lee Edwards and Dexter G. Smith The Master s of Science in Electrical and Computer Engineering, the first Johns Hopkins degree to be
ISTANBUL UNIVERSITY JOURNAL OF ELECTRICAL & ELECTRONICS ENGINEERING YEAR VOLUME NUMBER : 2009 : 9 : 1 (921-927) A DESIGN OF DSPIC BASED SIGNAL MONITORING AND PROCESSING SYSTEM Salih ARSLAN 1 Koray KÖSE
Guru Ghasidas Vishwavidyalaya, Bilaspur (C.G.) Institute of Technology Electronics & Communication Engineering B.Tech III Semester 1. Electronic Devices Laboratory 2. Digital Logic Circuit Laboratory 3.
3 Year ECE Course Rollout for 2015 2017 (updated April 2015) All parts of the rollout are subject to updates. For course descriptions, please refer to http://www.ece.cmu.edu/courses/course homepages.html
Introduction Graduate Option in Electronics Department of Electrical and Computer Engineering University of Puerto Rico at Mayagüez This document defines the Electronics Option in the Electrical Engineering
FACULTY OF POSTGRADUATESTUDIES Master of Science in Computer Engineering The Future University 2 Table of Contents: Page I. Introduction 1 II. Philosophy of the Program 2 III. Aims of the Program 2 IV.
INTRODUCTION TO DIGITAL SYSTEMS 1 DESCRIPTION AND DESIGN OF DIGITAL SYSTEMS FORMAL BASIS: SWITCHING ALGEBRA IMPLEMENTATION: MODULES (ICs) AND NETWORKS IMPLEMENTATION OF ALGORITHMS IN HARDWARE COURSE EMPHASIS:
Curriculum for a Master s Degree in ECE with focus on Mixed Signal SOC Design Department of Electrical and Computer Engineering Overview The VLSI Design program is part of two tracks in the department:
Continuous-Time Converter Architectures for Integrated Audio Processors: By Brian Trotter, Cirrus Logic, Inc. September 2008 As consumer electronics devices continue to both decrease in size and increase
Session ENG 206-6 Design and Development of Virtual Instrument (VI) Modules for an Introductory Digital Logic Course Nikunja Swain, Ph.D., PE South Carolina State University firstname.lastname@example.org Raghu Korrapati,
STUDENT PROFILES 2014-15 M.TECH IN RADIO FREQUENCY DESIGN AND TECHNOLOGY CENTRE FOR APPLIED RESEARCH IN ELECTRONICS INDIAN INSTITUTE OF TECHNOLOGY, DELHI http://care.iitd.ac.in Page 2 of 8 Dhritiman Kashyap
Dr. YILDIRAY YALMAN Associate Professor CONTACT INFORMATION Turgut Ozal University Computer Engineering Department TR-06010 Ankara, Turkey Phone: +90 (0)312-5515437 E-mail: email@example.com RESEARCH
118 Master of Science in Computer Science Department of Computer Science College of Arts and Sciences James T. Wilkes, Chair and Professor Ph.D., Duke University WilkesJT@appstate.edu http://www.cs.appstate.edu/
work for MS leading to PhD in Electrical Engineering 1 s for Digital Systems and Signal Processing EE 801 Analysis of Stochastic Systems EE 802 Advanced Digital Signal Processing EE 80 Advanced Digital
Architectural Level Power Consumption of Network Presenter: YUAN Zheng Why Architectural Low Power Design? High-speed and large volume communication among different parts on a chip Problem: Power consumption
Lesson 7: SYSTEM-ON ON-CHIP (SoC( SoC) AND USE OF VLSI CIRCUIT DESIGN TECHNOLOGY 1 VLSI chip Integration of high-level components Possess gate-level sophistication in circuits above that of the counter,
CURRICULUM VITAE A. GENERAL Name Address : Izzet Cem GÖKNAR : I.T.U. Elektrik-Elektronik Fakültesi Maslak 80626 Istanbul TURKEY Phone :+90-212-2853613, Fax : +90-212-2853679 e-mail Position Place of birth
MS GRADUATE PROGRAM IN COMPUTER ENGINEERING INTRODUCTION The increased interaction between computing and communication in recent years is changing the landscape of computer engineering. There is now an
Agenda Introduzione Il mercato Dal circuito integrato al System on a Chip (SoC) La progettazione di un SoC La tecnologia Una fabbrica di circuiti integrati 28 How to handle complexity G The engineering
Wide Band Tunable Filter Design Implemented in CMOS W. Matthew Anderson and Bogdan M. Wilamowski Electrical & Computer Engineering Dept. Auburn University, AL 36849 firstname.lastname@example.org, email@example.com
Mixed-Signal Test Emphasis in Engineering Technology Rainer J. Fink, Jay Porter, Yong-Kyu Jung, B. Ben Zoghi Department of Engineering Technology and Industrial Distribution Texas A&M University College
Recommended Courses by ECE Topic Area Undergraduate Students: Verify a course is an approved Science/Math/Engineering Elective or Technical Elective for your major. Graduate Students: A maximum of 6 credits
International Journal of Electronics and Computer Science Engineering 1482 Available Online at www.ijecse.org ISSN- 2277-1956 Behavioral Analysis of Different ALU Architectures G.V.V.S.R.Krishna Assistant
Introduction to Digital System Design Chapter 1 1 Outline 1. Why Digital? 2. Device Technologies 3. System Representation 4. Abstraction 5. Development Tasks 6. Development Flow Chapter 1 2 1. Why Digital
An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis Oliver Schrape 1, Frank Winkler 2, Steffen Zeidler 1, Markus Petri 1, Eckhard Grass 1, Ulrich Jagdhold 1 International
Master of Science in Electrical Engineering Graduate Program: A student may pursue a Master of Science in Electrical Engineering (M.Sc. EE) via one of the following three options: (i) M.Sc. with thesis,
University of California, Irvine 2015-2016 1 Undergraduate Major in Computer Science and Engineering On This Page: Overview Admissions Requirements for the B.S. in Computer Science and Engineering Sample
Victoria Kostina Curriculum Vitae - September 6, 2015 Page 1 of 5 Victoria Kostina Department of Electrical Engineering www.caltech.edu/~vkostina California Institute of Technology, CA 91125 firstname.lastname@example.org
Master of Science (Electrical Engineering) MS(EE) 1. Mission Statement: The mission of the Electrical Engineering Department is to provide quality education to prepare students who will play a significant
Session: 2220 Technical Aspects of Creating and Assessing a Learning Environment in Digital Electronics for High School Students Adam S. El-Mansouri, Herbert L. Hess, Kevin M. Buck, Timothy Ewers Microelectronics
Table of Contents Preface Acknowledgements Chapter 1: Overview 1.1 Silicon on Insulator a brief Introduction 1.2 Circuits and SOI 1.3 Technology and SOI Chapter 2: SOI Materials 2.1 Silicon on Heteroepitaxial
Mike Perkins, Ph.D. email@example.com Summary More than 28 years of experience in research, algorithm development, system design, engineering management, executive management, and Board of Directors
Victoria University of Wellington (VUW) course offering for NZ-EU Joint Mobility Project Novel Sensing Technologies and Instrumentation in Environmental Climate Change Monitoring 1. General The Victoria
IEE5049 - Spring 2012 數 位 積 體 電 路 Digital Integrated Circuits Course Overview Professor Wei Hwang 黃 威 教 授 Department of Electronics Engineering National Chiao Tung University firstname.lastname@example.org Wei
Second Year B.Tech. Program in Electronics Semester I 1MA 203 201 202 203 204 252 253 Applied Mathematics III Circuits Theory L T P Credits Scheme Theory Marks Practical Marks -- Data Structures and Algorithms
Core Curriculum to the Course: Environmental Science Law Economy for Engineering Accounting for Engineering Production System Planning and Analysis Electric Circuits Logic Circuits Methods for Electric
INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR CIRCUITS AND SYSTEMS, VOL. 1, NO. 1, JUNE 2011 27 A Charge Pump Circuit by using Voltage-Doubler as Clock Scheme Wen Chang Huang, Jin Chang Cheng,
Master of Science in Computer Engineering College of Engineering - Department of Electrical and Computer Engineering 1. Introduction \ Program Mission Computer engineers provide the key building blocks
Digital Signal Controller Based Automatic Transfer Switch by Venkat Anant Senior Staff Applications Engineer Freescale Semiconductor, Inc. Abstract: An automatic transfer switch (ATS) enables backup generators,
Christos Kyrkou, PhD KIOS Research Center for Intelligent Systems and Networks, Department of Electrical and Computer Engineering, University of Cyprus, Tel:(+357)99569478, email: email@example.com Education
COMPUTER ENGINEERING PROGRAM The master s degree in Computer Engineering focus on three main areas of research: computer architecture, data communication, and information processing. Active research interests
Assoc. Prof. Dr. Serdar KÜÇÜK Biography. Education: 2004: Ph.D. in Technical Educational Faculty, Electrical Department, Kocaeli University, Kocaeli, TURKEY. Thesis Title: Modeling and off-line programming
Huseyin Polat s Curriculum Vitae Department of Computer Engineering, Anadolu University, Eskisehir 26555, TURKEY +90 222 321 3550-6554 firstname.lastname@example.org http://home.anadolu.edu.tr/~polath/ Research
BTBU Master of Control Theory Control Discipline class: Primary discipline:control Science Sub-discipline: Control Theory Control Sub-discipline code:081101 一 Program Overview The program aims to educate
VON BRAUN LABS WE PROVIDE COMPLETE SOLUTIONS WWW.VONBRAUNLABS.COM Issue #1 VON BRAUN LABS WE PROVIDE COMPLETE SOLUTIONS ULTRA LOW POWER STATE MACHINE SOLUTIONS State Machine Technology IoT Solutions Learn
ROCIO ALBA-FLORES, Ph.D Work Address Home Address Electrical Engineering Technology Department 32 High St. State University of New York, Alfred Alfred, NY 14802 10 Upper College Drive, Alfred, NY 14802
Automatic Floating-Point to Fixed-Point Transformations Kyungtae Han, Alex G. Olson, and Brian L. Evans Dept. of Electrical and Computer Engineering The University of Texas at Austin Austin, TX 78712 1084
EE ELECTRICAL ENGINEERING See beginning of Section H for abbreviations, course numbers and coding. The * denotes labs which are held on alternate weeks. A minimum grade of C is required for all prerequisite
Master of Science in Computer Science Background/Rationale The MSCS program aims to provide both breadth and depth of knowledge in the concepts and techniques related to the theory, design, implementation,
35'th Annual Precise Time and Time Interval (PTTI) Systems and Applications Meeting San Diego, December 2-4, 2003 A PC-BASED TIME INTERVAL COUNTER WITH 200 PS RESOLUTION Józef Kalisz and Ryszard Szplet
Vol. 6, o., April, 011 A ew Programmable RF System for System-on-Chip Applications Jee-Youl Ryu 1, Sung-Woo Kim 1, Jung-Hun Lee 1, Seung-Hun Park 1, and Deock-Ho Ha 1 1 Dept. of Information and Communications
DEVELOPING TRENDS OF SYSTEM ON A CHIP AND EMBEDDED SYSTEM * Monire Norouzi Young Researchers and Elite Club, Shabestar Branch, Islamic Azad University, Shabestar, Iran *Author for Correspondence ABSTRACT
DEGREE PLAN INSTRUCTIONS FOR COMPUTER ENGINEERING Fall 2000 The instructions contained in this packet are to be used as a guide in preparing the Departmental Computer Science Degree Plan Form for the Bachelor's
Serial port interface for microcontroller embedded into integrated power meter Mr. Borisav Jovanović, Prof. dr. Predrag Petković, Prof. dr. Milunka Damnjanović, Faculty of Electronic Engineering Nis, Serbia
Circuit and System Representation IC Designers must juggle several different problems Multiple levels of abstraction IC designs requires refining an idea through many levels of detail, specification ->
Downloaded from orbit.dtu.dk on: Jan 04, 2016 Clock and datarecovery IC with demultiplexer for a 2.5 Gb/s ATM physical layer controller Hansen, Flemming; Salama, C.A.T. Published in: Proceedings of the
Georges EL-HOWAYEK Valparaiso University Electrical and Computer Engineering Building, Room 223 Valparaiso, IN 46383, USA email@example.com http://www.unm.edu/~ghowayek/ RESEARCH INTERESTS Communication
COURSE CATALOGUE 201-201 Field: COMPUTER SCIENCE Programme: Bachelor s Degree Programme in Computer Science (Informatics) Length of studies: years (6 semesters) Number of ECTS Credits: 180 +0 for the B.Sc.
Implementing a Digital Answering Machine with a High-Speed 8-Bit Microcontroller Zafar Ullah Senior Application Engineer Scenix Semiconductor Inc. Leo Petropoulos Application Manager Invox TEchnology 1.0
PROPOSAL FOR A MASTER OF SCIENCE DEGREE PROGRAM IN ELECTRICAL ENGINEERING UNIVERSITY OF THE DISTRICT OF COLUMBIA SCHOOL OF ENGINEERING AND APPLIED SCIENCES DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
INF4420 Analog to Digital Converters Jørgen Andreas Michaelsen Spring 2013 1 / 34 Outline Overview of architectures for implementing analog to digital conversion Spring 2013 Analog to Digital Converters
1 M.S. in Electrical Engineering Degree Requirements Bridge Program Students who have earned a Bachelor of Science in Engineering Technology (B.S.E.T.) degree, or who lack an appropriate background may
C8051F020 Utilization in an Embedded Digital Design Project Course Daren R. Wilcox Southern Polytechnic State University Marietta, Georgia Abstract In this paper, the utilization of the C8051F020 in an
(662) 325-1530 firstname.lastname@example.org EDUCATION University of Nevada Las Vegas Las Vegas, Nevada Ph.D., Electrical Engineering 5/00 Course Emphases: Computer Engineering and Digital Signal Processing Dissertation:
CURRICULUM VITAE 1. Name of the Faculty : Dr. Satish Kumar Peddapelli 2. Father s Name : P. Shankar 3. Date of Birth : 28-10-1974 4. Designation : Assistant Professor 5. Department : Electrical Engineering
Note that these pages are extracted from the full Graduate Catalog, please refer to it for complete details. College of 1 ELECTRICAL AND COMPUTER ENGINEERING www.ece.neu.edu SHEILA S. HEMAMI, PHD Professor
216 ON SUITABILITY OF FPGA BASED EVOLVABLE HARDWARE SYSTEMS TO INTEGRATE RECONFIGURABLE CIRCUITS WITH HOST PROCESSING UNIT *P.Nirmalkumar, **J.Raja Paul Perinbam, @S.Ravi and #B.Rajan *Research Scholar,
PROGRAMMABLE ANALOG INTEGRATED CIRCUIT FOR USE IN REMOTELY OPERATED LABORATORIES Carsten Wulff (email@example.com) Prof. Trond Ytterdal (firstname.lastname@example.org) Norwegian University of Science and Technology,
imtech Curriculum Presentation Effective from Batch 2015 Onwards April, 2015 Course Structure Every course has a fixed number of credits associated with it (e.g., 4 credits) One has to earn 200 credits
Digital Logic Design: An Embedded Systems Approach Using VHDL Chapter 1 Introduction and Methodology Portions of this work are from the book, Digital Logic Design: An Embedded Systems Approach Using VHDL,
SoC Curricula at Tallinn Technical University Margus Kruus, Kalle Tammemäe, Peeter Ellervee Tallinn Technical University Phone: +372-6202250, Fax: +372-6202246 email@example.com firstname.lastname@example.org email@example.com
Curriculum Vitae Michael M. Zavlanos Home Address Work Address 2114 Pine Street 3330 Walnut Street Apartment 1 Front GRASP Laboratory, Levine Hall 465 Philadelphia, PA 19103 Dept. of Electrical and Systems
An Efficient Architecture for Image Compression and Lightweight Encryption using Parameterized DWT Babu M., Mukuntharaj C., Saranya S. Abstract Discrete Wavelet Transform (DWT) based architecture serves
ECE 410: VLSI Design Course Introduction Professor Andrew Mason Michigan State University Spring 2008 ECE 410, Prof. A. Mason Lecture Notes Page i.1 Age of electronics microcontrollers, DSPs, and other
Spike-Based Sensing and Processing: What are spikes good for? John G. Harris Electrical and Computer Engineering Dept ONR NEURO-SILICON WORKSHOP, AUG 1-2, 2006 Take Home Messages Introduce integrate-and-fire
May 2010 Issue: Tutorial Phase Locked Loop Systems Design for Wireless Infrastructure Applications Use of linear models of phase noise analysis in a closed loop to predict the baseline performance of various
MsC in Advanced Electronics Systems Engineering 1 2 General overview Location: Dijon, University of Burgundy, France Tuition Fees : 475 / year Course Language: English Course duration: 1 year Level: Second