Traditional Software Development. Model Requirements and JAVA Programs. Formal Verification & Validation. What is a state?
|
|
- Agnes Lang
- 8 years ago
- Views:
Transcription
1 Mel Requirements and JAVA Programs MVP The Waterfall Mel Problem Area Traditional Software Develoment Analysis REVIEWS Design Costly wrt time and money. Errors are found too late (or maybe never). SPIN/PROMELA JAVA Imlementation Testing REVIEWS MVP Running System Intrucing, detecting and reairing errors Liggesmeyer 98 Formal Verification & Validation? Design Mel Secification Verification & Validation MVP 3 MVP 4 Objective What is a state? Design= behaviour + Requirement= desired or forbidden behaviour X=5 Y=7 Z=3 a Xsin Yes/No! Simulation Deadlock? Livelock? Requirement violation? MVP 5 A state is characterized by: Values of local/global variables Channel(s) contents State of each rocess (=rogram location) MVP 6
2 What is a state (continued)? A state is the cross-ruct between the state of all rocesses (+ variable values + channel contents): A B A A A3 MVP 7 B B (A,B) (A,B) (A,B) (A3,B) Interleaving examle from MVP byte s = roctye A(){s== -> s++ roctye B() {s== -> s-- init {run A(); run B() Transition systems: A <s=> s== s++ <s=> <s=> MVP 8 B <s=> s== <s=> s-- <s=> Combined (interleaved) transition system (state grah) of (A B) state++ state== MVP 9 state== state== state== state-- state++ state-- state++ state-- state-- state++ state-- state++ Each trace = a rogram execution (behaviour) SPIN checks all traces Correctness Requirements to Promela mels Behaviour: The set of all execution sequences in the state grah Sequences may be finite or infinite Two kinds of requirements: State requirements: Boolean conditions on some (or all) system states Temoral requirements: Requirements to a certain ordering of boolean conditions on states MVP Correctness Analysis: Analysis of the State Grah Promela Program Each state is described by: Values of all variables Contents of all channels Location counters for all rocesses State Grah MVP roctye A() {.. assert(condition).. Result of analysis Assertions When this location is art of the system state, the condition must be true! Note: assert(...) is always executable No error: condition is true for all ossible executions Error: there exists at least one execution, where the condition is false MVP Assert examle
3 byte state=; 3 roctye A() 4 { state== -> state++; 5 assert (state==) roctye B() 9 { state== -> state--; assert (state==) 3 init {run A(); run B() Simle counter examle rearing trail, lease wait...ne : roc (:init:) line 3 "an_in" (state ) [(run A())] : roc (:init:) line 3 "an_in" (state ) [(run B())] 3: roc (B) line 9 "an_in" (state ) [((state==))] 4: roc (A) line 4 "an_in" (state ) [((state==))] 5: roc (B) line 9 "an_in" (state ) [state = (state-)] 6: roc (B) line "an_in" (state 3) [assert((state==))] 7: roc terminates 8: roc (A) line 4 "an_in" (state ) [state = (state+)] sin: line 5 "an_in", Error: assertion violated sin: text of failed assertion: assert((state==)) MVP 3 Combined (interleaved) transition system of (A B) state== state++ state== state== state-- state++ state-- state++ state-- state-- state++ state-- state++ Each trace = a rogram execution SPIN checks all traces MVP 4 state== Invariant roerties is always true is an invariant assert(p) must be evaluated for all system states One way of exressing an invariant: Define a dedicated rocess: roctye monitor(){assert() Invariant: Simle counter revisited int int x; x; roctye roctye P(){ P(){ x< x< x=x+ x=x+ roctye roctye Q(){ Q(){ x> x> x=x- x=x- roctye roctye R(){ R(){ x== x== x= x= roctye roctye invariant(){ invariant(){ assert(x>=- assert(x>=- && && x<=) x<=) Which values may x take? count-inv MVP 5 MVP 6 Linear Temoral Logic (LTL) LTL examle LTL can exress requirements on the ordering of state conditions (redicates): <> Eventually [] Always/invariantly U q until q #define (state==) #define q (state==3) byte state=; roctye A(){ state= roctye B(){ state=3 <>q? Uq? []( -> <>q)? Ltl/ltl examle MVP A formula must hold for ALL traces 7 MVP 8 3
4 Imlementing rocesses Meling rocesses as finite state machines using Promela Imlementing threads in Java. Note: to avoid confusion, we use the term rocess when referring to the mels, and thread when referring to the imlementation in Java. MVP 9 Two basic object invokation meths call-return (caller waits for callee) Efficient Callee is rotected from caller Callee is a assive object start-sto (caller and callee continues) Exensive calling sequence Callee is not rotected from caller Callee becomes an object (a thread) call-return one thread start-sto two threads MVP Fundamental roblems: Scheduling, Protection, Synchronization JVM with threads JVM State State State 3 State 4 Four Thread States each consisting of Program Counter & Object addresses MVP Threads in Java A Thread class manages a single sequential thread of control. Threads may be created and deleted dynamically. Thread MyThread The Thread class executes instructions from its meth. The actual ce executed deends on the imlementation rovided for in a derived class. class MyThread extends Thread { ublic void { //... Thread x = new MyThread(); MVP Threads in Java Since Java es not ermit multile inheritance, we often imlement the meth in a class not derived from Thread but from the interface Runnable. Runnable target Thread ublic interface Runnable { ublic abstract void ; MyRun class MyRun imlements Runnable{ ublic void { //... Thread x = new Thread(new MyRun()); MVP 3 An overview of the life-cycle of a thread as state transitions: thread life-cycle in Java new Thread() Created The redicate isalive() can be used to test if a thread has been started but not terminated. Once terminated, it cannot be restarted (cf. mortals). start() causes the thread to call its meth. start() Alive failure, or returns Terminated MVP 4 4
5 Thread alive states in Java Once started, an alive thread has a number of substates : Summary of thread meths start() yield() Running Runnable disatch slee() wait() notify() timeout Non-Runnable failure, or returns Dummy: yield Blocking: wait, wait(msec), slee, slee(msec), join, join(msec) Unblocking: notify, notifyall, interrut State inquiry: isalive, isinterruted Priority: getpriority, setpriority MVP 5 MVP 6 CountDown timer examle Develo a JAVA alet which can: Count wn once er second from some constant number Dislay the current count value Sto after count wn to zero or when requested by system (e.g. winw change) Mel in Promela? CountDown timer - Promela #define dummy #define N 5 chan bee = [] of {bit; chan tick = [] of {bit; chan sto = [] of {bit; chan start = [] of {bit; byte count=; roctye counter() { byte i; if start?dummy -> i=n; i> -> tick!dummy; i-- i== -> bee!dummy; break sto?dummy -> break fi roctye system() { start!dummy; sto!dummy roctye dislay() { tick?dummy -> count++ bee?dummy -> break timeout -> break Proerties? MVP 7 MVP 8 CountDown timer - roerties Count wn to zero should be ossible The system should be able to terminate before count wn to zero (at system sto) CountDown timer - Promela #define dummy #define N 5 chan bee = [] of {bit; chan tick = [] of {bit; chan sto = [] of {bit; chan start = [] of {bit; byte count=; roctye counter() { byte i; if start?dummy -> i=n; i> -> tick!dummy; i-- i== -> bee!dummy; break sto?dummy -> break fi roctye system() { start!dummy; sto!dummy roctye dislay() { tick?dummy -> count++ bee?dummy -> break timeout -> break Imlementation in Java? MVP 9 MVP 3 5
6 CountDown timer - class diagram Alet CountDown init() start() sto() tick() bee() counter dislay Runnable target The class NumberCanvas rovides the dislay canvas. Thread NumberCanvas setvalue() The class CountDown derives from Alet and contains the imlementation of the meth which is required by Thread. MVP 3 CountDown class ublic class CountDown extends Alet imlements Runnable { Thread counter; int i; final static int N = ; AudioCli beesound, ticksound; NumberCanvas dislay; ublic void init() {... ublic void start() {... ublic void sto() {... ublic void {... rivate void tick() {... rivate void bee() {... MVP 3 CountDown class - start(), sto() and ublic void start() { counter = new Thread(this); i = N; counter.start(); ublic void sto() { counter = null; ublic void { while(true) { if (counter == null) return; if (i>) { tick(); --i; if (i==) { bee(); return; COUNTDOWN Mel roctye counter() { byte i; if start?dummy -> i=n; i> -> tick!dummy; i-- i== -> bee!dummy;break sto?dummy -> break fi MVP 33 CountDown class tick() and bee() rivate void tick(){ dislay.setvalue(i); ticksound.lay(); try{ Thread.slee(); catch (InterrutedExcetion e){ rivate void bee(){ dislay.setvalue(i); beesound.lay(); MVP 34 Summary Concets rocess - unit of concurrency, execution of a rogram Mels Promela to mel rocesses as state machines - sequences of atomic actions Practice Java threads to imlement rocesses Thread lifecycle - created, running, runnable, nonrunnable, terminated MVP 35 6
Overview of Lecture 3. Model Checking with SPIN. First attempt (revisited) Linear Temporal Logic (LTL) CDP #3
Concurrent and Distributed Programming htt://fmt.cs.utwente.nl/courses/cd/ Mel Checking with SPIN CDP #3 Overview of Lecture 3 Ch. 4 - Verification of Concurrent Programs linear temoral logic (LTL) deductive
More informationSoftware Model Checking: Theory and Practice
Software Model Checking: Theory and Practice Lecture: Secification Checking - Temoral Logic Coyright 2004, Matt Dwyer, John Hatcliff, and Robby. The syllabus and all lectures for this course are coyrighted
More informationConcurrent programming in Java
Concurrent programming in Java INF4140 04.10.12 Lecture 5 0 Book: Andrews - ch.05 (5.4) Book: Magee & Kramer ch.04 - ch.07 INF4140 (04.10.12) Concurrent programming in Java Lecture 5 1 / 33 Outline 1 Monitors:
More informationENFORCING SAFETY PROPERTIES IN WEB APPLICATIONS USING PETRI NETS
ENFORCING SAFETY PROPERTIES IN WEB APPLICATIONS USING PETRI NETS Liviu Grigore Comuter Science Deartment University of Illinois at Chicago Chicago, IL, 60607 lgrigore@cs.uic.edu Ugo Buy Comuter Science
More informationIntroduction to SPIN. Acknowledgments. Parts of the slides are based on an earlier lecture by Radu Iosif, Verimag. Ralf Huuck. Features PROMELA/SPIN
Acknowledgments Introduction to SPIN Parts of the slides are based on an earlier lecture by Radu Iosif, Verimag. Ralf Huuck Ralf Huuck COMP 4152 1 Ralf Huuck COMP 4152 2 PROMELA/SPIN PROMELA (PROcess MEta
More informationToday s Agenda. Automata and Logic. Quiz 4 Temporal Logic. Introduction Buchi Automata Linear Time Logic Summary
Today s Agenda Quiz 4 Temporal Logic Formal Methods in Software Engineering 1 Automata and Logic Introduction Buchi Automata Linear Time Logic Summary Formal Methods in Software Engineering 2 1 Buchi Automata
More informationFundamentals of Software Engineering
Fundamentals of Software Engineering Model Checking with Temporal Logic Ina Schaefer Institute for Software Systems Engineering TU Braunschweig, Germany Slides by Wolfgang Ahrendt, Richard Bubel, Reiner
More informationOverview Motivating Examples Interleaving Model Semantics of Correctness Testing, Debugging, and Verification
Introduction Overview Motivating Examples Interleaving Model Semantics of Correctness Testing, Debugging, and Verification Advanced Topics in Software Engineering 1 Concurrent Programs Characterized by
More informationSoftware Engineering using Formal Methods
Software Engineering using Formal Methods Model Checking with Temporal Logic Wolfgang Ahrendt 24th September 2013 SEFM: Model Checking with Temporal Logic /GU 130924 1 / 33 Model Checking with Spin model
More informationLecture 9 verifying temporal logic
Basics of advanced software systems Lecture 9 verifying temporal logic formulae with SPIN 21/01/2013 1 Outline for today 1. Introduction: motivations for formal methods, use in industry 2. Developing models
More informationIntroduction to Promela and SPIN. LACL, Université Paris 12
Introduction to Promela and SPIN LACL, Université Paris 12 Promela = Process Meta Language A specification language! No programming language! Used for system description : Specify an abstraction of the
More informationFormal Verification by Model Checking
Formal Verification by Model Checking Natasha Sharygina Carnegie Mellon University Guest Lectures at the Analysis of Software Artifacts Class, Spring 2005 1 Outline Lecture 1: Overview of Model Checking
More informationConcurrent Program Synthesis Based on Supervisory Control
010 American Control Conference Marriott Waterfront, Baltimore, MD, USA June 30-July 0, 010 ThB07.5 Concurrent Program Synthesis Based on Suervisory Control Marian V. Iordache and Panos J. Antsaklis Abstract
More informationThe Model Checker SPIN
The Model Checker SPIN Author: Gerard J. Holzmann Presented By: Maulik Patel Outline Introduction Structure Foundation Algorithms Memory management Example/Demo SPIN-Introduction Introduction SPIN (Simple(
More informationMutual Exclusion using Monitors
Mutual Exclusion using Monitors Some programming languages, such as Concurrent Pascal, Modula-2 and Java provide mutual exclusion facilities called monitors. They are similar to modules in languages that
More informationExtending your Qt Android application using JNI
Extending your Qt Android alication using JNI Dev Days, 2014 Presented by BogDan Vatra Material based on Qt 5.3, created on November 13, 2014 Extending your alication using JNI Extending your alication
More information1 Gambler s Ruin Problem
Coyright c 2009 by Karl Sigman 1 Gambler s Ruin Problem Let N 2 be an integer and let 1 i N 1. Consider a gambler who starts with an initial fortune of $i and then on each successive gamble either wins
More informationINF5140: Specification and Verification of Parallel Systems
INF5140: Specification and Verification of Parallel Systems Lecture 7 LTL into Automata and Introduction to Promela Gerardo Schneider Department of Informatics University of Oslo INF5140, Spring 2007 Gerardo
More informationLecture 8: Safety and Liveness Properties
Concurrent Programming 19530-V (WS01) 1 Lecture 8: Safety and Liveness Properties Dr. Richard S. Hall rickhall@inf.fu-berlin.de Concurrent programming December 11, 2001 Safety Properties 2 A safety property
More informationQuick Start Guide. June 3, 2012
The ERIGONE Model Checker Quick Start Guide Mordechai (Moti) Ben-Ari Department of Science Teaching Weizmann Institute of Science Rehovot 76100 Israel http://stwww.weizmann.ac.il/g-cs/benari/ June 3, 2012
More informationCS11 Java. Fall 2014-2015 Lecture 7
CS11 Java Fall 2014-2015 Lecture 7 Today s Topics! All about Java Threads! Some Lab 7 tips Java Threading Recap! A program can use multiple threads to do several things at once " A thread can have local
More informationJava Virtual Machine Locks
Java Virtual Machine Locks SS 2008 Synchronized Gerald SCHARITZER (e0127228) 2008-05-27 Synchronized 1 / 13 Table of Contents 1 Scope...3 1.1 Constraints...3 1.2 In Scope...3 1.3 Out of Scope...3 2 Logical
More informationintroduction to program monitoring
introduction to program monitoring CS 119 part II beyond assert and print course website http://www.runtime-verification.org/course09 action standing order: sell when price drops more than 2% within 1
More informationChapter 8 Implementing FSP Models in Java
Chapter 8 Implementing FSP Models in Java 1 8.1.1: The Carpark Model A controller is required for a carpark, which only permits cars to enter when the carpark is not full and does not permit cars to leave
More informationThreads & Tasks: Executor Framework
Threads & Tasks: Executor Framework Introduction & Motivation WebServer Executor Framework Callable and Future 12 April 2012 1 Threads & Tasks Motivations for using threads Actor-based Goal: Create an
More informationOutline of this lecture G52CON: Concepts of Concurrency
Outline of this lecture G52CON: Concepts of Concurrency Lecture 10 Synchronisation in Java Natasha Alechina School of Computer Science nza@cs.nott.ac.uk mutual exclusion in Java condition synchronisation
More informationVerification of Agent Behavioral Models
The 2000 International Conference on Artificial Intelligence (IC-AI'2000) June 26-29, 2000 Monte Carlo Resort, Las Vegas, Nevada Verification of Agent Behavioral Models Timothy H. Lacey and Scott A. DeLoach
More informationStylianos Basagiannis
Interlocking control by Distributed Signal Boxes Technical Report (TR) 4 Stylianos Basagiannis Supervisors: Dr Andrew Pombortsis, Dr Panagiotis Katsaros Aristotle University of Thessaloniki Department
More informationThreads 1. When writing games you need to do more than one thing at once.
Threads 1 Threads Slide 1 When writing games you need to do more than one thing at once. Threads offer a way of automatically allowing more than one thing to happen at the same time. Java has threads as
More informationJAVA - MULTITHREADING
JAVA - MULTITHREADING http://www.tutorialspoint.com/java/java_multithreading.htm Copyright tutorialspoint.com Java is amulti threaded programming language which means we can develop multi threaded program
More informationLast Class: OS and Computer Architecture. Last Class: OS and Computer Architecture
Last Class: OS and Computer Architecture System bus Network card CPU, memory, I/O devices, network card, system bus Lecture 3, page 1 Last Class: OS and Computer Architecture OS Service Protection Interrupts
More informationTopics. Producing Production Quality Software. Concurrent Environments. Why Use Concurrency? Models of concurrency Concurrency in Java
Topics Producing Production Quality Software Models of concurrency Concurrency in Java Lecture 12: Concurrent and Distributed Programming Prof. Arthur P. Goldberg Fall, 2005 2 Why Use Concurrency? Concurrent
More informationLecture 6: Introduction to Monitors and Semaphores
Concurrent Programming 19530-V (WS01) Lecture 6: Introduction to Monitors and Semaphores Dr. Richard S. Hall rickhall@inf.fu-berlin.de Concurrent programming November 27, 2001 Abstracting Locking Details
More informationrace conditions Image courtesy of photostock / FreeDigitalPhotos.net Flavia Rainone - Principal Software Engineer
Boston race conditions? Image courtesy of photostock / FreeDigitalPhotos.net 2 race conditions Race conditions arise in software when separate computer processes or threads of execution depend on some
More informationUniversity of Twente. A simulation of the Java Virtual Machine using graph grammars
University of Twente Department of Computer Science A simulation of the Java Virtual Machine using graph grammars Master of Science thesis M. R. Arends, November 2003 A simulation of the Java Virtual Machine
More informationCISC422/853: Formal Methods
Outline CISC422/853: Formal Methods in Software Engineering: Computer-Aided Verification Topic 7: Specifying, or How to Describe How the System Should (or Should Not) Behave Juergen Dingel Feb, 2009 Readings:
More informationTemporal Logics. Computation Tree Logic
Temporal Logics CTL: definition, relationship between operators, adequate sets, specifying properties, safety/liveness/fairness Modeling: sequential, concurrent systems; maximum parallelism/interleaving
More information3C03 Concurrency: Condition Synchronisation
3C03 Concurrency: Condition Synchronisation Mark Handley 1 Goals n Introduce concepts of Condition synchronisation Fairness Starvation n Modelling: Relationship between guarded actions and condition synchronisation?
More informationSoftware safety - DEF-STAN 00-55
Software safety - DEF-STAN 00-55 Where safety is dependent on the safety related software (SRS) fully meeting its requirements, demonstrating safety is equivalent to demonstrating correctness with respect
More informationSoftware Cognitive Complexity Measure Based on Scope of Variables
Software Cognitive Comlexity Measure Based on Scoe of Variables Kwangmyong Rim and Yonghua Choe Faculty of Mathematics, Kim Il Sung University, D.P.R.K mathchoeyh@yahoo.com Abstract In this aer, we define
More informationJava Memory Model: Content
Java Memory Model: Content Memory Models Double Checked Locking Problem Java Memory Model: Happens Before Relation Volatile: in depth 16 March 2012 1 Java Memory Model JMM specifies guarantees given by
More informationA Classification of Model Checking-based Verification Approaches for Software Models
A Classification of Model Checking-based Verification Approaches for Software Models Petra Brosch, Sebastian Gabmeyer, Martina Seidl Sebastian Gabmeyer Business Informatics Group Institute of Software
More informationPRIME NUMBERS AND THE RIEMANN HYPOTHESIS
PRIME NUMBERS AND THE RIEMANN HYPOTHESIS CARL ERICKSON This minicourse has two main goals. The first is to carefully define the Riemann zeta function and exlain how it is connected with the rime numbers.
More informationFormal Verification of Software
Formal Verification of Software Sabine Broda Department of Computer Science/FCUP 12 de Novembro de 2014 Sabine Broda (DCC-FCUP) Formal Verification of Software 12 de Novembro de 2014 1 / 26 Formal Verification
More informationSystem modeling. Budapest University of Technology and Economics Department of Measurement and Information Systems
System modeling Business process modeling how to do it right Partially based on Process Anti-Patterns: How to Avoid the Common Traps of Business Process Modeling, J Koehler, J Vanhatalo, IBM Zürich, 2007.
More informationOBJECT ORIENTED PROGRAMMING LANGUAGE
UNIT-6 (MULTI THREADING) Multi Threading: Java Language Classes The java.lang package contains the collection of base types (language types) that are always imported into any given compilation unit. This
More informationMonitors & Condition Synchronization
Chapter 5 Monitors & Condition Synchronization 1 monitors & condition synchronization Concepts: monitors: encapsulated data + access procedures mutual exclusion + condition synchronization nested monitors
More informationContext-Bounded Model Checking of LTL Properties for ANSI-C Software. Jeremy Morse, Lucas Cordeiro, Bernd Fischer, Denis Nicole
Context-Bounded Model Checking of LTL Properties for ANSI-C Software Jeremy Morse, Lucas Cordeiro, Bernd Fischer, Denis Nicole Model Checking C Model checking: normally applied to formal state transition
More informationDesign of A Knowledge Based Trouble Call System with Colored Petri Net Models
2005 IEEE/PES Transmission and Distribution Conference & Exhibition: Asia and Pacific Dalian, China Design of A Knowledge Based Trouble Call System with Colored Petri Net Models Hui-Jen Chuang, Chia-Hung
More informationMODEL CHECKING OF SERVICES WORKFLOW RECONFIGURATION: A PERSPECTIVE ON DEPENDABILITY
MODEL CHECKING OF SERVICES WORKFLOW RECONFIGURATION: A PERSPECTIVE ON DEPENDABILITY 1 Juan Carlos Polanco Aguilar 1 Koji Hasebe 1 Manuel Mazzara 2 Kazuhiko Kato 1 1 University of Tsukuba Department of
More informationModel Checking based Software Verification
Model Checking based Software Verification 18.5-2006 Keijo Heljanko Keijo.Heljanko@tkk.fi Department of Computer Science and Engineering Helsinki University of Technology http://www.tcs.tkk.fi/~kepa/ 1/24
More informationNAVAL POSTGRADUATE SCHOOL THESIS
NAVAL POSTGRADUATE SCHOOL MONTEREY CALIFORNIA THESIS SYMMETRICAL RESIDUE-TO-BINARY CONVERSION ALGORITHM PIPELINED FPGA IMPLEMENTATION AND TESTING LOGIC FOR USE IN HIGH-SPEED FOLDING DIGITIZERS by Ross
More informationApplying Model Checking to Destructive Testing and Analysis of Software System
1254 JOURNAL OF SOFTWARE, VOL. 8, NO. 5, MAY 2013 Applying Mel Checking to Destructive Testing and Analysis of Software System Hiroki Kumamoto, Takahisa Mizuno, Kensuke Narita, Shin-ya Nishizaki Department
More informationWeb Application Scalability: A Model-Based Approach
Coyright 24, Software Engineering Research and Performance Engineering Services. All rights reserved. Web Alication Scalability: A Model-Based Aroach Lloyd G. Williams, Ph.D. Software Engineering Research
More informationIntroducing the Dezyne Modelling Language
Introducing the Dezyne Modelling Language Bits & Chips Smart Systems, 20 November 2014 Paul Hoogendijk. paul.hoogendijk@verum.com Software Controlled Systems Software Controlled Systems Event driven Concurrent,
More informationlogic language, static/dynamic models SAT solvers Verified Software Systems 1 How can we model check of a program or system?
5. LTL, CTL Last part: Alloy logic language, static/dynamic models SAT solvers Today: Temporal Logic (LTL, CTL) Verified Software Systems 1 Overview How can we model check of a program or system? Modeling
More informationProgramming by Contract. Programming by Contract: Motivation. Programming by Contract: Preconditions and Postconditions
COMP209 Object Oriented Programming Designing Classes 2 Mark Hall Programming by Contract (adapted from slides by Mark Utting) Preconditions Postconditions Class invariants Programming by Contract An agreement
More informationDeadlock Victim. dimanche 6 mai 12
Deadlock Victim by Dr Heinz Kabutz && Olivier Croisier The Java Specialists Newsletter && The Coder's Breakfast heinz@javaspecialists.eu && olivier.croisier@zenika.com 1 You discover a race condition 2
More informationModel Checking LTL Properties over C Programs with Bounded Traces
Noname manuscript No. (will be inserted by the editor) Model Checking LTL Properties over C Programs with Bounded Traces Jeremy Morse 1, Lucas Cordeiro 2, Denis Nicole 1, Bernd Fischer 1,3 1 Electronics
More informationMultithreaded Programming
Java Multithreaded Programming This chapter presents multithreading, which is one of the core features supported by Java. The chapter introduces the need for expressing concurrency to support simultaneous
More informationSafety evaluation of digital post-release environment sensor data interface for distributed fuzing systems
Safety evaluation of digital ost-release environment sensor data interface for distributed fuzing systems 57 th Fuze Conference, Newark, NJ Wednesday, July 30 th, 2014 Oen Session IIIA, 3:20 PM S. Ebenhöch,
More informationFDA CFR PART 11 ELECTRONIC RECORDS, ELECTRONIC SIGNATURES
Document: MRM-1004-GAPCFR11 (0005) Page: 1 / 18 FDA CFR PART 11 ELECTRONIC RECORDS, ELECTRONIC SIGNATURES AUDIT TRAIL ECO # Version Change Descrition MATRIX- 449 A Ga Analysis after adding controlled documents
More informationFailure Behavior Analysis for Reliable Distributed Embedded Systems
Failure Behavior Analysis for Reliable Distributed Embedded Systems Mario Tra, Bernd Schürmann, Torsten Tetteroo {tra schuerma tetteroo}@informatik.uni-kl.de Deartment of Comuter Science, University of
More informationMonitors, Java, Threads and Processes
Monitors, Java, Threads and Processes 185 An object-oriented view of shared memory A semaphore can be seen as a shared object accessible through two methods: wait and signal. The idea behind the concept
More informationMassachusetts Institute of Technology 6.005: Elements of Software Construction Fall 2011 Quiz 2 November 21, 2011 SOLUTIONS.
Massachusetts Institute of Technology 6.005: Elements of Software Construction Fall 2011 Quiz 2 November 21, 2011 Name: SOLUTIONS Athena* User Name: Instructions This quiz is 50 minutes long. It contains
More informationTest Case Generation for Ultimately Periodic Paths Joint work with Saddek Bensalem Hongyang Qu Stavros Tripakis Lenore Zuck Accepted to HVC 2007 How to find the condition to execute a path? (weakest precondition
More informationA Hoare Logic for Monitors in Java
INSTITUT FÜR INFORMATIK UND PRAKTISCHE MATHEMATIK EHRSTUH FÜR SOFTWARETECHNOOIE A Hoare ogic for Monitors in Java Erika Ábrahám Frank S. de Boer Willem-Paul de Roever Martin Steffen Bericht Nr. TR-ST-03-1
More informationPoint Location. Preprocess a planar, polygonal subdivision for point location queries. p = (18, 11)
Point Location Prerocess a lanar, olygonal subdivision for oint location ueries. = (18, 11) Inut is a subdivision S of comlexity n, say, number of edges. uild a data structure on S so that for a uery oint
More informationModel-Checking Verification for Reliable Web Service
Model-Checking Verification for Reliable Web Service Shin NAKAJIMA Hosei University and PRESTO, JST nkjm@i.hosei.ac.jp Abstract Model-checking is a promising technique for the verification and validation
More informationC-Bus Voltage Calculation
D E S I G N E R N O T E S C-Bus Voltage Calculation Designer note number: 3-12-1256 Designer: Darren Snodgrass Contact Person: Darren Snodgrass Aroved: Date: Synosis: The guidelines used by installers
More informationComparing Dissimilarity Measures for Symbolic Data Analysis
Comaring Dissimilarity Measures for Symbolic Data Analysis Donato MALERBA, Floriana ESPOSITO, Vincenzo GIOVIALE and Valentina TAMMA Diartimento di Informatica, University of Bari Via Orabona 4 76 Bari,
More informationInternational Journal of Software Engineering and Knowledge Engineering Vol. 11, No. 3 (2001) 231-258 World Scientific Publishing Company
International Journal of Software Engineering and Knowledge Engineering Vol. 11, No. 3 (2001) 231-258 World Scientific Publishing Company MULTIAGENT SYSTEMS ENGINEERING SCOTT A. DELOACH, MARK F. WOOD AND
More informationMemory management. Chapter 4: Memory Management. Memory hierarchy. In an ideal world. Basic memory management. Fixed partitions: multiple programs
Memory management Chater : Memory Management Part : Mechanisms for Managing Memory asic management Swaing Virtual Page relacement algorithms Modeling age relacement algorithms Design issues for aging systems
More informationJava Concurrency Framework. Sidartha Gracias
Java Concurrency Framework Sidartha Gracias Executive Summary This is a beginners introduction to the java concurrency framework Some familiarity with concurrent programs is assumed However the presentation
More informationChapter 6, The Operating System Machine Level
Chapter 6, The Operating System Machine Level 6.1 Virtual Memory 6.2 Virtual I/O Instructions 6.3 Virtual Instructions For Parallel Processing 6.4 Example Operating Systems 6.5 Summary Virtual Memory General
More informationtutorial: hardware and software model checking
tutorial: hardware and software model checking gerard holzmann and anuj puri { gerard anuj } @research.bell-labs.com Bell Labs, USA outline introduction (15 mins) theory and algorithms system modeling
More informationFormal Verification and Linear-time Model Checking
Formal Verification and Linear-time Model Checking Paul Jackson University of Edinburgh Automated Reasoning 21st and 24th October 2013 Why Automated Reasoning? Intellectually stimulating and challenging
More informationAlgorithmic Software Verification
Algorithmic Software Verification (LTL Model Checking) Azadeh Farzan What is Verification Anyway? Proving (in a formal way) that program satisfies a specification written in a logical language. Formal
More informationSoftware Quality Exercise 1
Software Quality Exercise Model Checking Information. Dates Release: 7.0.0.5pm Deadline: 07.0.0.5pm Discussion:.0.0. Formalities While this exercise can be solved and handed in in groups of three, every
More informationSoftware Verification and Testing. Lecture Notes: Temporal Logics
Software Verification and Testing Lecture Notes: Temporal Logics Motivation traditional programs (whether terminating or non-terminating) can be modelled as relations are analysed wrt their input/output
More information6.042/18.062J Mathematics for Computer Science December 12, 2006 Tom Leighton and Ronitt Rubinfeld. Random Walks
6.042/8.062J Mathematics for Comuter Science December 2, 2006 Tom Leighton and Ronitt Rubinfeld Lecture Notes Random Walks Gambler s Ruin Today we re going to talk about one-dimensional random walks. In
More informationHoare-Style Monitors for Java
Hoare-Style Monitors for Java Theodore S Norvell Electrical and Computer Engineering Memorial University February 17, 2006 1 Hoare-Style Monitors Coordinating the interactions of two or more threads can
More informationBusiness Process Verification: The Application of Model Checking and Timed Automata
Business Process Verification: The Application of Model Checking and Timed Automata Luis E. Mendoza Morales Processes and Systems Department, Simón Bolívar University, P.O. box 89000, Baruta, Venezuela,
More informationBuilt-in Concurrency Primitives in Java Programming Language. by Yourii Martiak and Mahir Atmis
Built-in Concurrency Primitives in Java Programming Language by Yourii Martiak and Mahir Atmis Overview One of the many strengths of Java is the built into the programming language support for concurrency
More informationValidated Templates for Specification of Complex LTL Formulas
Validated Templates for Specification of Complex LTL Formulas Salamah Salamah Department of Electrical, computer, Software, and Systems Engineering Embry Riddle Aeronautical University 600 S. Clyde Morris
More informationData Link Layer(1) Principal service: Transferring data from the network layer of the source machine to the one of the destination machine
Data Link Layer(1) Principal service: Transferring data from the network layer of the source machine to the one of the destination machine Virtual communication versus actual communication: Specific functions
More informationAutomata-based Verification - I
CS3172: Advanced Algorithms Automata-based Verification - I Howard Barringer Room KB2.20: email: howard.barringer@manchester.ac.uk March 2006 Supporting and Background Material Copies of key slides (already
More informationRuntime Verification - Monitor-oriented Programming - Monitor-based Runtime Reflection
Runtime Verification - Monitor-oriented Programming - Monitor-based Runtime Reflection Martin Leucker Technische Universität München (joint work with Andreas Bauer, Christian Schallhart et. al) FLACOS
More informationSHARED HASH TABLES IN PARALLEL MODEL CHECKING
SHARED HASH TABLES IN PARALLEL MODEL CHECKING IPA LENTEDAGEN 2010 ALFONS LAARMAN JOINT WORK WITH MICHAEL WEBER AND JACO VAN DE POL 23/4/2010 AGENDA Introduction Goal and motivation What is model checking?
More informationIntegrated Error-Detection Techniques: Find More Bugs in Java Applications
Integrated Error-Detection Techniques: Find More Bugs in Java Applications Software verification techniques such as pattern-based static code analysis, runtime error detection, unit testing, and flow analysis
More informationSimple Cooperative Scheduler for Arduino ARM & AVR. Aka «SCoop»
Simple Cooperative Scheduler for Arduino ARM & AVR Aka «SCoop» Introduction Yet another library This library aims to provide a light and simple environment for creating powerful multi-threaded programs
More informationAUTOMATED TEST GENERATION FOR SOFTWARE COMPONENTS
TKK Reports in Information and Computer Science Espoo 2009 TKK-ICS-R26 AUTOMATED TEST GENERATION FOR SOFTWARE COMPONENTS Kari Kähkönen ABTEKNILLINEN KORKEAKOULU TEKNISKA HÖGSKOLAN HELSINKI UNIVERSITY OF
More informationUsing Patterns and Composite Propositions to Automate the Generation of Complex LTL
University of Texas at El Paso DigitalCommons@UTEP Departmental Technical Reports (CS) Department of Computer Science 8-1-2007 Using Patterns and Composite Propositions to Automate the Generation of Complex
More informationIt is the thinnest layer in the OSI model. At the time the model was formulated, it was not clear that a session layer was needed.
Session Layer The session layer resides above the transport layer, and provides value added services to the underlying transport layer services. The session layer (along with the presentation layer) add
More informationThe Darwin Game 2.0 Programming Guide
The Darwin Game 2.0 Programming Guide In The Darwin Game creatures compete to control maps and race through mazes. You play by programming your own species of creature in Java, which then acts autonomously
More informationCABRS CELLULAR AUTOMATON BASED MRI BRAIN SEGMENTATION
XI Conference "Medical Informatics & Technologies" - 2006 Rafał Henryk KARTASZYŃSKI *, Paweł MIKOŁAJCZAK ** MRI brain segmentation, CT tissue segmentation, Cellular Automaton, image rocessing, medical
More informationStatic and Dynamic Properties of Small-world Connection Topologies Based on Transit-stub Networks
Static and Dynamic Proerties of Small-world Connection Toologies Based on Transit-stub Networks Carlos Aguirre Fernando Corbacho Ramón Huerta Comuter Engineering Deartment, Universidad Autónoma de Madrid,
More informationMonitoring Frequency of Change By Li Qin
Monitoring Frequency of Change By Li Qin Abstract Control charts are widely used in rocess monitoring roblems. This aer gives a brief review of control charts for monitoring a roortion and some initial
More informationLecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
More informationBuilding a Multi-Threaded Web Server
Building a Multi-Threaded Web Server In this lab we will develop a Web server in two steps. In the end, you will have built a multi-threaded Web server that is capable of processing multiple simultaneous
More information