The search engine you can see. Connects people to information and services

Transcription

1 The search engine you can see Connects people to information and services

2 The search engine you cannot see Total data: ~1EB Processing data : ~100PB/day Total web pages: ~1000 Billion Web pages updated: ~10Billion/day requests: ~10Billion/day Total logs : ~100PB Logs updated: ~1PB/day

3 The search engine you don t see Speech Image Rec. sys Intelligent HCI Other cutting edge tech. Large scale distributed computing Large scale distributed storage

4 The history of Moore s law PERFORMANCE OF PROCESSOR The Moore s law is going to the end

5 The history of data center PERFORMANCE OF PROCESSOR Mainframe PC cluster SDDC

6 History of data center PC cluster SDDC 2000~now Scalability 2013~ Efficiency

7 Outline What is the PC cluster What is the SDDC Baidu s practice Conclusion

8 PC cluster Background Web scale applications The performance and cost limitations of mainframe Scale PC server by Ethernet Up to 10K servers per cluster Typical configurations Commodity hardware: X86 CPU, INSPUR, HUAWEI Software: MR/HDFS/Spark

9 PC cluster Typical stack Each layer are independent The interfaces are highly abstract Follows the technology paradigms of PC Limitations Multiple highly abstract layers block to exploit the performance potential Commodity hardware cannot support emerging applications, such as AI and big data The end of Moore s law Applications Distributed software Commodity hardware

10 Software-Defined Data Center - SDDC What is SDDC How Applications driven hardware and software Whole-stack co-design Algorithm Customized for new hardware and architecture System and software separate data path and control path Hardware Expose low level API, fully controlled by software Customized for applications Applications Applications Distributed software software Commodity hardware hardware

11 Software-Defined Data Center - SDDC Why SDDC Exploit performance potential cross multiple layer Customized hardware to extend Moore s law for emerging applications AI and big data Achieve extreme efficiency The FPGA in SDDC Enable the possibility of whole-stack co-design

12 SDDC Baidu s visions and practice Vision Shift PC cluster to SDDC in next 3 years Define and design the SDDC, collaborating with partners Practice SDF: software-defined flash SDA: software-defined accelerator 2011: SDF 2013: SDA 2015: design the distributed SD system

13 Software-defined flash background Traditional SSD limitations Low bandwidth utilization 40% or less in real workload Limited capacity utilization Only 50%~70% for applications Less predictable performance Large-scale 10,000+ SSD deployment per year (10PB+ capacity) Challenges Acquisition of extra devices Higher cost

14 Software-defined flash designs Software defined Expose low level hardware interface to software Software can control hardware completely New hardware architecture Expose hardware channels to software Individual FTL controller for each channel New HW/SW interface Write in the unit of erase block size Leverage global resource for data persistency Removes across-channel parity coding CH_0 ch_0 /dev/sda SSD Controller CH_1 ch_0... Conventional SSD CH_N ch_0 /dev/sda0 ~/dev/sdan SSD Ctrl CH_0 ch_0 SSD Ctrl CH_1 ch_0 SDF... SSD Ctrl CH_N ch_0

15 Software-defined flash designs Removing unnecessary software layers To reduce latency and CPU cycles To remove complexity of kernel configurations User-defined scheduler Data layout Erase scheduling File System User Space VFS Generic Block Layer IO Scheduler Block Device Page Cache 1 1 User Space Kernel Space IOCTRL PCIE SCSI Mid-layer SATA and SAS Translation 1 Low Level Device Driver PCIE Driver Direct IO IO Conventional SSD Buffered IO IO SDF (a) (b)

16 Software-defined flash designs Hardware 25nm MLC NAND, 44 channels, ONFI 1.x asynchronous 40Mhz 5 FPGA, 4 Spartan-6 for FTL, Virtex-5 for PCIE PCIEx8 Virtex-5 Spartan-6 Spartan-6 Spartan-6 Spartan-6 11 channels 11 channels 11 channels 11 channels

17 Software-defined flash conclusions Key ideas Exposes flash channels to software SW/HW co-design Results 95% write and 99% read bandwidth utilization 99% capacity utilization 50% cost reduction per GB compared with SSD for workload on the production systems deployment in Baidu Webpage storage system 3x performance better than commodity SSD 50% cost reduction

18 Software-defined accelerator background AI is the core technology speech, image, page ranking and Ads. Extremely computing density GPU CPU FPGA High cost High power and high space consumption Higher demand on data center cooling, power supply, and space utilization Medium cost and power consumption Low speed Most potential Need faster iteration of development

19 Software-defined accelerator design Xilinx K7 FPGA Best performance/cost/power consumption Evaluations x 4.1 x CPU GPU FPGA Batch size=8, layer=8 Workload1 Weight matrix size=512 FPGA is 4.1x than GPU FPGA is 3x than CPU Workload2 Weight matrix size=2048 FPGA is 2.5x than GPU FPGA is 3.5x than CPU Req/s Fig a:workload1 2.5 x Thread # 3.5 x CPU GPU FPGA Conclusions FPGA can merge the small requests to improve performance Throughput in Req/s of FPGA scales better Fig b: workload2 Thread #

20 Conclusion Paradigm shift From PC cluster to SDDC What is SDDC Applications driven Whole-stack co-deign and tuning The FPGA in SDDC Enable SDDC Baidu s vision and practice Shift PC cluster to SDDC SDF,SDA and more