Flexible I/O Using FMC Standard FPGA and CPU Track B&C HWCONF 2013
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1 Flexible I/O Using FMC Standard FPGA and CPU Track B&C HWCONF 2013 THALES NEDERLAND B.V. AND/OR ITS SUPPLIERS THIS INFORMATION CARRIER CONTAINS PROPRIETARY INFORMATION WHICH SHALL NOT BE USED, REPRODUCED OR DISCLOSED TO THIRD PARTIES WITHOUT PRIOR WRITTEN AUTHORIZATION BY THALES NEDERLAND B.V. AND/OR ITS SUPPLIERS, AS APPLICABLE. 1 THALES NEDERLAND B.V.
2 Connecting PC Technology to Thales Sensors PC Technology Connection Sensors Embedded-PC (6U) Integrated Multi-Sensor Suite Rack-PC (19 ) Desktop-PC (Test Equipment) Compact Single Sensor Use international standards to interface between the PC-Backbone and Thales Specific I/O 2 THALES NEDERLAND B.V.
3 Specific I/O Evolutions with respect to specific I/O Physically combined I/O and Processing Physically decoupled I/O from Processing FPGA-based I/O, FPGA on mezzanine Adopt international mezzanine standards CMC (=mechanical formfactor only) PMC (=CMC + conventional PCI bus) 3 THALES NEDERLAND B.V.
4 Specific I/O (2) Further evolutions (last decade) Parallel busses replaced by high-speed serial Logical step in terms of mezzanine: XMC (=CMC + high-speed serial) XMC standard (VITA 42) suffers from: Limited market adoption Solder-joint issues with XMC connector (reliability) Use of (Industrial) PC technology for Compact Sensor Systems PCIe is backbone, Ethernet and USB have their own limitations 4 THALES NEDERLAND B.V.
5 Specific I/O (3) Potential threat: Increased design effort due to design-in of FPGAs with multi-gigabit serial links Selected solution: Migrate FPGA from mezzanine towards carrier card, and develop: Generic carrier: design-once, use-many Simple application-specific mezzanines Adoption of FMC (VITA 57) standard 5 THALES NEDERLAND B.V.
6 Examples I/O FMC Mezzanine Cards (MC) 1-ch 8.0 GSPS DAC 1/2/4-ch 1.25/2.5/5.0 GSPS ADC 40 Gbps QSFP Optical Transceiver GHz RF Transceiver 6 THALES NEDERLAND B.V.
7 Examples Processing Mezzanine Cards (MC) Single 4-core Fixed-Point DSP Single 8-core Floating-Point DSP Quad 16-core Floating-Point (Co)Processor 7 THALES NEDERLAND B.V.
8 And for DIY fanatics.. FMC Breadboard Mezzanine (COTS) 8 THALES NEDERLAND B.V.
9 Examples COTS FMC Carrier Cards (CC) cpci 3U (single-site) VPX 6U (dual-site) MC MC1 MC2 AMC (single-site) VPX 6U RTM (dual-site) MC 9 THALES NEDERLAND B.V.
10 Examples of Evaluation Carrier/Mezzanine Cards Not compliant to mechanical standard! Hopefully compliant to electrical standard.. 10 THALES NEDERLAND B.V.
11 FMC Connector Physical characteristics Samtec SeaArray SEAM/SEAF connector (2 nd supplier: Molex) 400-balls BGA, 10 columns/40 rows, 1.0 mm pitch, solder-charged Low Pin Count (LPC, 4 col.) / High Pin Count (HPC, 10 col.) Designed for high-density, high-speed interconnect Electrical characteristics Differential signalling (LVDS/CML pairs) Up to 80 inputs/outputs Up to 4 dedicated clocks Up to 10 full-duplex gigabit transceivers Up to 2 transceiver reference clocks Single-ended signalling (LVTTL/LVCMOS/.) Up to 160 inputs/outputs/bidirs Adjustable voltage supply (VADJ), based on IPMI EEPROM FMC carrier cards reads EEPROM and sets VADJ Fixed 12V/3.3V power supplies JTAG 11 THALES NEDERLAND B.V.
12 TNL: PCIe- and FMC Standards Combined PCIe (PCI Express): International Standard PCI-SIG FMC (FPGA Mezzanine Card) : International Standard ANSI/VITA THALES NEDERLAND B.V.
13 PCIe FMC Carrier (PFC) / FMC Mezzanines PFC (Generic) FMC_DTIO FMC_CTIO FMC_DIO FMC_TRX6A 13 THALES NEDERLAND B.V.
14 Carrier Assembly Testing/Programming FMC Loopback Mezzanine (COTS, ApisSys) PFC (=DUT) SFP+ Loopback Module (COTS, Molex) Carrier Assembly Testing: - Mandatory: Optical Inspection - Optionally: Flying-Probe Testing - Mandatory: IEEE (JTAG/Boundary Scan) - Optionally: Functional Testing (SFP+ Loopback) Carrier Programming (=Configuration Flash): - Mandatory: IEEE 1532 (ISC) 14 THALES NEDERLAND B.V.
15 Mezzanine Assembly Testing/Programming FMC (=DUT) PFC + Goepel JTAG PCIe Adapter (=Test Adapter) Mezzanine Assembly Testing: - Mandatory: Optical Inspection - Optionally: Flying-Probe Testing - Optionally: IEEE (through Carrier FPGA) Mezzanine Programming (=IPMI EEPROM): - Mandatory: IEEE (JTAG/Boundary Scan, through Carrier FPGA) 15 THALES NEDERLAND B.V.
16 So far, the physical part.. But what about the application? 16 THALES NEDERLAND B.V.
17 PCIe FMC Carrier Block-diagram / FPGA 17 THALES NEDERLAND B.V.
18 FMC Mezzanine Signal Mapping (Excel/VBA) All user I/O names, -types and -electrical levels defined in Excel: generated VHDL and UCF 18 THALES NEDERLAND B.V.
19 FMC Mezzanine User I/O VHDL Wrapper 19 THALES NEDERLAND B.V.
20 FMC Mezzanine User I/O UCF Constraints 20 THALES NEDERLAND B.V.
21 FMC Mezzanine IPMI XML Description XML converted to Motorola SREC (hex) file (JTAG) Command-line tool prior to assembly for: Board Manufacturing Date/Time Board Serial Number 21 THALES NEDERLAND B.V.
22 Decoupling of Design Disciplines Design of FMC mezzanine cards: Intended for physical layer (only) of specific interface(s) Electrical/optical/RF/etc. Design templates available under CM Board/PCB design activity/skills Design of FMC carrier card FPGAs: Provides datalink/transport layer(s) of interface protocol(s) (De)Serializing/error checking/framing, etc. Applicative functions For instance (pre-)processing/formatting of data Bridging to/from PCI-Express Generic PFC Shell available under CM FPGA design activity/skills Design of driver- and application software: Linux driver has generic part Linux driver application part and application Embedded (real-time) software design activity/skills 22 THALES NEDERLAND B.V.
23 Mezzanine / Carrier Combination FMC (Specific) PFC (Generic) 23 THALES NEDERLAND B.V.
24 Sensor / Processing Combination Rack PC: - Linux (RT) - GPP (Intel) - GP-GPU (Nvidia) Radar Antenna System Radar Transceiver (FPGAs, RF, PSU) DIO Multiple Discrete I/Os (MC) (RS422/RS485/Solid State Relais) Transceiver Data/Parameters (CC) (Optical Link, SFP) 24 THALES NEDERLAND B.V.
25 Summary/Conclusions Flexible I/O solution/product for PC technology At acceptable RC costs and long(er) life-cycle Mezzanines either COTS or developed at minimal lead-time/cost FPGA design effort minimized by re-use and code-generation SW programming model is (more) standard and open Envisioned future applications Legacy systems / upgrades Analog Radar Video output/input RF/IF Generation Specific I/O Discretes New systems Phased-array Front-End Processing (FPGA/GPP/GPU) Small Systems Segment products (GPP/GPU) Thanks for your attention and feedback! 25 THALES NEDERLAND B.V.
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