Virtualisation in NOCs for enhanced MPSOC robustness and performance verification. overview 1

Transcription

1 Virtualisation in NOCs for enhanced POC robustness and performance verification Electronic ystems Group Electrical Engineering Faculty overview 1 context embedded systems applications OC design goal & approach reduce OC design effort independent design & verification of applications techniques composability / ualisation predictability CompOC platform conclusions Electronic ystems

2 embedded systems 2 smart phones, game consoles, cars, refrigerators, buildings,... interaction with physical world safety critical real time phone, TV? cochlear implant x-by-wire Electronic ystems converging application domains 3 audio, video, graphics, games, internet apps,... diverse requirements: hard/soft real-time, best effort many combinations of applications (use cases) run-time switching upgrades, run-time downloads independent software vendors (IV) Electronic ystems

3 OC platform-based design many hardware blocks (IP) multi-processor distributed shared memory PEG IP DC VIP P B CU TDC QVCP5L Triedia #1 Triedia #2 QVCP2L 4 many IP providers many IP interface standards re-use is common DC-EC DC-CT -GIC -IPC CLOCK GLOBAL IP P4450 PA-ON PA-EC PA-AB PCI/XIO PA emory Controller T32 DC-EC VPG DVDD EDA VLD T32 T1-IPC T1-GIC DC-CT T2-IPC T2-GIC DENC integration at structural level e.g. protocol checkers functional verification?... EET T1-DBG T2-DBG UAT1 UAT2 UAT3 EJTAG BOOT DE IIC1 IIC2 IIC3 UB C1 C2 -Gate QVCP2 B1 B2 QTN QVCP1 VIP1 VIP2 VPK TDA PDIO AIO1 AIO2 AIO3 GPIO TUNNEL P1 P2 C-Bridge -DC T-DC Electronic ystems OC design 5 complex logically (complex function & architecture) physically (lay-out, package) logistically (hundreds of people, concurrent development, IV) getting worse every year (oore s law, reduced TT) takes too long software development verification & debug monolithic verification after integration hardware plus software IV / IP providers do not release source code circular verification who s to blame for errors? + money - 3 start design start selling 2 first profit 1 time end of life Electronic ystems

4 overview 6 context embedded systems applications OC design goal & approach reduce OC design effort independent design & verification of applications techniques composability / ualisation predictability CompOC platform conclusions Electronic ystems goal & approach 7 goal: reduce OC design effort and cost approach: design & verification per application Electronic ystems

5 requirements 8 independent development of applications require specification of applications, both functionally (values) and non-functionally (temporal behaviour) stability of prior applications the validated service of an application must not be affected by the integration of the component into a larger system linear integration effort already integrated applications must not disturbed by the integration of another application replica determinism if fault tolerance is achieved by replication, a set of replicated components must be replica determinate based on Kopetz [but services & components are replaced by applications; more later] Electronic ystems overview 9 context embedded systems applications OC design goal & approach reduce OC design effort independent design & verification of applications techniques composability / ualisation predictability CompOC platform conclusions Electronic ystems

6 goal & approach 10 goal: reduce OC design effort and cost approach: design & verification per application two-level solution 1.composability: ual platform per application no interference between applications 2.predictability: real-time ual platform for T application bounded interference within T application FT radio application T video application BE GUI application Electronic ystems composability 11 the behaviour of an application is not affected by the presence or absence of other applications the functional and non-functional (timing) behaviour also when switching other applications on/off (transition behaviour) (ideally) no restrictions on application (programming model) no interference between applications: 1. monolithic verification after integration independent verification before integration inter-dependent 2 N x 2 N x 2 N x 2 N independent 2 N + 2 N + 2 N + 2 N 2.reduced state space speeds up design, simulation, verification, debug Electronic ystems

7 composability 12 intuitively, every application has its own ual platform and time-division multiplex ual platforms on real platform FT radio ual platform T video ual system proc interc mem proc interc mem processor interconnect memory application operating system, scheduler, arbiter,... hypervisor, ual machine monitor, real-time operating system Electronic ystems composability 13 intuitively, every application has its own ual platform and time-division multiplex ual platforms on real platform... many app combinations... few ual platforms Electronic ystems

8 composability 14 1.develop new video application independently in its own ual platform add new application to existing system (e.g. comprising audio & GUI applications) 2.without causing problems for existing applications (audio & GUI) 3.without causing problems for newly added application (video) hence avoids circular dependencies in development & verification and, the integration effort is linear in the number of applications FT radio application BE GUI application T video application Electronic ystems composability vs. ualisation 15 normal ualisation time: operating system space: ual memory ualise addresses ualise memory capacity instruction set 1961, time-sharing IB 7090/94 here, additionally, ualise the performance when you are served Electronic ystems

9 goal & approach 16 goal: reduce OC design effort and cost approach: design & verification per application two-level solution 1.composability: ual platform per application no interference between applications 2.predictability: real-time ual platform for T application bounded interference within T application FT radio application T video application BE GUI application Electronic ystems predictability 17 within a ual platform only for real-time applications that need it 1.bounded interference per ual resource minimum bandwidth, maximum latency, etc. FT radio ual platform T video ual system proc interc processor interconnect memory Electronic ystems mem proc interc mem application operating system, scheduler, arbiter,... hypervisor, ual machine monitor, real-time operating system

10 predictability 18 within a ual platform only for applications that need it 1.bounded interference per ual resource minimum bandwidth, maximum latency, etc. T video application 2.end-to-end performance guarantee taking into account all the ual resources that the application uses various formalisms data flow, latency-rate, network calculus restrictions on resources & application (programming model) Electronic ystems overview 19 context embedded systems applications OC design goal & approach reduce OC design effort independent design & verification of applications techniques composability / ualisation predictability CompOC platform conclusions Electronic ystems

11 CompOC 20 composable & predictable multi-processor OC platform network on chip, processors, memories predictable resources appropriate arbiters (composable, predictable) intuitively, two-level arbitration on each resource pre-emptive TD between applications (not) predictable between tasks of same application FT radio ual platform T video ual system proc interc mem proc interc mem processor interconnect memory Electronic ystems CompOC 21 actually, we use budget schedulers that guarantee a budget within a replenishment interval pre-emptive or guarantee finite requests composable and/or predictable static / dynamic schedules not / work conserving TD static schedule composable not work conserving replenishment interval budget (2/6) time CCP dynamic schedule static priorities, but with budget predictable optionally work conserving Electronic ystems

12 CompOC: network on chip 22 connections are ual wires with budgeted throughput & latency pipelined TD switch composable contention-free routing inter & intra application issues: multiple clock domains (GAL, mesochronous / asynchronous) pre-emption / ual channels K K K K K K K K K K T P T shell (): transaction message network interface (K): message packet routers (): move packets around Electronic ystems CompOC: processor tile one master per tile may have local memories scratch pad, cache os P os P 23 os CompOe TO composable pre-emptive TD between applications predictable TD/ within applications optionally work conserving issues: predictable processor (A, ihive VLI, icroblaze) interrupts (hard to budget; only for TO, not for applications) caches (pollution: flush between applications, software coherency) Electronic ystems

13 CompOC: processor tile communicate with other tiles using NOC connections master local bus implements distributed memory map D memory consistency D os P D os P 24 issues: blocking reads / IO (use DA, communication assist CA) synchronisation (avoid locks & semaphores) Electronic ystems CompOC: shared memory tile 25 A resource shared by multiple masters A, DA / DD various arbitration schemes composable (TD) predictable (TD, CCP) optionally work-conserving issues: no ual memory (static partitioning of address space over applications) infinitely long transactions (chop them up vs. pre-emption) DA, refresh (predictable memory patterns) A A C Electronic ystems

14 CompOC: performance methodology 26 for real-time applications use variable-rate data flow to model applications task - resource binding resource sharing & budgets can compute end-to-end throughput & latency, buffer sizes restrictions on programming model (explicit communication) resources & arbiters (predictable) N-1 task-resource dependencies no resource-resource dependencies A A C Electronic ystems CompOC: FPGA prototype 27 jpeg, ring-tone player, audio filtering, video processing, etc. run-time loading, starting, stopping of applications TTTL mixer filter JPEG em PE T em PE T em PE T em PE TTT em PE TT host NoC Audio em Video app Electronic ystems T task

15 related approaches 28 CompOC resource sharing between & within apps with two-level arbitration dynamic schedules can use slack within applications physical separation of applications essentially, independent systems no resource sharing time-triggered architectures [Kopetz] only share interconnect resource no distinction between arbitration between and within applications TD everywhere (static schedules only, may be expensive) cannot use slack within applications addresses faults (static schedulecan observe absence of event) in use in automotive, aerospace, railway industries eterg: only performance-monotonic applications Electronic ystems conclusions 29 OC design cost explodes due to software development & verification aim for independent application development & verification composability also support real-time applications predictability CompOC platform clean concept, but with many restrictions hardware, embedded software, design flow FPGA prototype Electronic ystems

16 CompOC references 30 CompOC template Hansson, TODAE 09 Bekooij, LNC 3199/2004 composable & predictable network on chip Goossens, Design & Test 05 Hansson, IET CDT 09 predictable DD memory controller Akesson, CODE 07 composable slave arbitration Akesson, DD 09 data flow modelling oreira, EOFT 07 iggers, COPE 07 Electronic ystems end 31 for further information Electronic ystems Group Electrical Engineering Faculty Electronic ystems