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1 LENAHCP MICROPROCESOR Paralel CPU With 6 CPU Directly Compatible oitcurti With MC5 ROMs and Instruction Set Includes RAMs lanoitidnoc Branching, Easy Expansion One CPU pmuj to Subroutine and can Directly Drie up to tceridni Fetching 3,68 Bits of ROM and up Binary and Decimal to 5 Bits of RAM citemhtira Modes Standard Operating 8 Microsecond Tmperture Range of noitcurti Cycle to C Also Aailable With ot +85 C Operating Range eht Intel is a complete blt paralel central procesing unit (CPU) The easily Interfaces with keyboards,sehctiws displays, AO conerters printers and other peripheral equipment eht CPU can directly adre K 8bit instruction words of progrwn memory and 5 bits of data storage RAM Sixten xedni registers are proided for temporary data storage Up to 6 bit input ports af'd 6 bit output ports may also be yltcerid adr88d { W I ow INTIRNAl I'ITI DATA" ATAD " I T TIlT Sy CLsI r'f ' ',' ' TOT s ', AIT N era InformatIOn t8ln8d Ier t'8ci specifications on DIeM from _rel 8 CorpOr8lon 98 Order Number: 38 f acats INTI \PI I I R ''TI II O''CTIoAI ft DATA DATA [!I r! I HCTARK DAP "I 8n+ _I I SINGLE CHIP BIT Bit The is fabricated with Pch8nnel silicon pie MOS technology i: IT 'GISTI PROGR C_TIR & " i LIVtLNO' "" J ;;;;;;,, LIVI"J "" _I STACK ' '8' M T"'NG r In CorpOrallOn a r8spcwisi for DIe use 8IY CRUIry o«ner tn8n ;)OOI8G, an Intel product No arcuii paiint licenses

2 TSET noit8cinum betwmn the prr and the RAM dna ROM chips ocurs on t lin A logic "'" lewf It this input cl8t's I flglnd Ntus regilt'" Ind forces the prowm 'l8tnu to Z8'O To completely clear I adres TSET input The togal 8 of this sipl may be mtlt with the JCN instruction MORMC m out by the pr when d8ta is rir MARMC outputs Tte re the Iection sigsln for the RAM ;ps ;n the System owt pm clodt inputs tlom po8tie t8g8 V 5 t5% m8in,ply wit8gl Pin Description, BIDIRECTIONAL DATA BUS Alladdrnd dau CMROM output This is the ROM selection signal RESET RESET input from prm memory CMAAMQ CMAAM3, Ind index regilt'", clock cycles (8 mkhine cyclesl RESET must be Ipplied for 6, Va SYNC SYNC OUtput SyndoniUtion lignel WIt8d by the ijfr and to the ROM Ind RAM chips It indic8t8 the beginning of an instruction cycle Voo

3 B eht uper bits (OPRI wil always be fetched before the lower bits (OPAl during M and M ENO WORD INSTRUCTIONS w I DA'A I tuptuo/tupni and RAM Instructions and OWT WORD INSTRUCTIONS,AI!I' A, A, A,I I At A, A, A, I A, A, A, A, I L at at A, at I A, a, a, a, I I OA'A I M'A I I t Dt D O I,,,, I ni these instructions (which are al single word) the CPR contains a bit code which identifies either "'"TuOIflWI I, I, I, I I I I I I Instruction Set Format AMaine Instructions word instruction 8bits requiring 8 clod< periods (instruction cycle) word instruction 6bits requiring 6 clock periods ( instruction cycles) hcae instruction is diided into two fourbit fields The uper bits is the OPR field containing the operation code The lower bits is the OPA containing the modifier For two word instructions, the second word contains address information or data times respectiely DJ DJ D DJ DJ D I I 8 I 8 I I ::5:::J IGISTI I 8 I 8 I I : ':':8 _I IGIST' A' I, I I 8,88 ' I, cnll,,,,,, '''j I I I I IS I CYCLI OJ,, De, OJ, De '''''] I _I_I I _ I, CC*OI'I I I I I c c c c OR I I I I :O:;:"I;'I 'GIS" I "\ A_I I I I I I I Ar: A;I A' 'GII' AI Table I i, IMtnlCtion Form8t Accumulator Group Instructions eht I/O instruction or the acumulator group instruction and the CPA contains a bit code which identifies the operation to be performed Table II illustrates the contents of each bit field o,"dto,d, \) TI'I'I'IItII II_'_I,I,I,I,IfAl_fTI'I'I'I'IIII _ IITMI A""' A, T'" II and A,Ia Group Itructen Fnwu 3

4 BASIC NO R OUCRlrTDI OF PIMT8 c, C ROM I COItIS this JCN "SfInlf t*' C C c, c AM R R R FtIdI m (rkt) from ROM Dati,,,, O O O O D O D D _ reg, catal R 3 A A A catn out u an ad, Oatl8Cld IS placid!ria r 3 JIM A A A Ju '"'eci SInd coni"' 'ea MA out 8 5 JMS As AAAAs A A, AA AAAA"SIWldms(,"tIX*) I A, 8Id A, I, WI u I"" ' A A A A S'*rKt CO of, MAR m, WI" borow A La t A A A A con of rtoti8f MA I D A A A A EICI\InGI cu,*","* II8IW AR 8Id KCr C OD D D IrnI bkk (8Mt leel WI stkid d*i DO F CLC a cry F I ",'r 3F C* 5F ML o o left (Acaimw 8Id ry) AM O, AOI8 rlqlt (Accu"" F TC '" o " TrtoCUftU8fIndc OAC '" o " IF TCS o o T, *at Md c af OM 'O" *'muck I nstruction Set INSTRUCTIONS 8( = Word Instructions) It It, De It D, De NOP NoOO8fltn Jump to ROM address A, I, A, A, A, A, A, A (WIIfIII tile JCN a a a c, c A, A A A A At A A IS tr otiww go to till nul,str*' c pp klcaal MR fttcii mrki from N)M sid contl fo Indli reo, cycle J ' A, As As A Jump uncofdlgiiilo N)M As At As A A A A A A A, A A As A, A, A, A, A, A A As A A, Jump SutMIe N)M A A, A, A, A, A, A, A, IW SlQI*a SUI,Nt A A A A ICrrllln conlin of reo, MRA A A A A IIICr"'t CO"''ls,,, MAR Go ROM Iddrns A, A, A, A, SZ As As A As AA ' A,A AAAA,(uS8'N)MNcont_sISZ,"S'OrI d mull O lilt nut WlstrD" ADO ' A A A A Add nii of riilsw MAA KCII8r If! 'Y D lam D D D D LOadati DODO ccu" Fa ClI CIt8' DotII (Accwnr and cry) aiid Clrry) FC,, rsuott_ciin"i out Of *' to I y ca8 Fa oa

5 TUPTUOITUPNI ANO RAM INSTRUCTIONS IH IEMOMC " ON DESCRIPTIO DF OPE emc,, D D, D, D D Instructn OE WAM Wrd, t, contms tile acumulator Into tilt prhtous se E WMP WrMt Ifte caim,"ts MAR mam mlftofy ctlaractlr E WR Write Ifte cantlims tilt Icumuilor "' Ifte pred dld cycle MOR Outul POIt (I/O lsl WAG Wr_t I" COftIftS Ifte ICUmor I'" pltylou$ly st 5E 9E AW ORM MAR stilus Cftafldtr ae ADM I Ad " "egusly sectld RAM mlwi memory cqrlcer ronrl\ci wltl Clry //8/9/89 Send 'OIS,r control Send the Iddress (contents ot tn SAC R R R ',gist" pal' RRR) to ROM and RAM at x, and X,lmt In 'lie I" ICwmulitOf O I'" preiously ctld RAM Ouput POfI (Output llftlsi Wrltt Ifte contents I" accumuillor Into I" pltwousiy ctld EJ WPM IIaW Dytl Of rudlwrlti program memory tultd wltll 8/9 or ", Write till ","'I of IlIIlCcumUlator Into preiously SI RAM aitul ctllrlctl' E3 a t t, Write 'III contents ', Iccumuiltor Into 'III preiously ndld RAM slltus clrldef J Reid llie PfUSIy sa_clld RAM ma, memory C""actl' Into llie accumator EA ADA Ae tile contents Iftl previously Sl8Cd AOM,nout fllto lilt lccumtor (/ lfals), EC RDO I Aud tile "IVGUSIy selected RAM 5lluS cllirlcler Inlo Kcurnuillor EF AD3 t t t Reid tfte "I tousty SIed RAM stilus cftlrldlr JccumlllOf 3 Into 5

6 M 8 AO CO EO FO JCN JCN JCN 3 JCN JCN 5 JCN 8 JCN JCN 8 JCN 9 JCN A JCN 8 JCN C JCN JCN E JCN F JCN FlY SAC FIM 3 SAC FlY 5 SAC 8 FlY SftC 8 FlY SAC A FlY 8 SftC C FlY D SAC Fl f SAC FIN 3 JIN 3 FIN 3 JIN, FIN JIN FIN 3 JIN FIN JIN M FIN JIN X FIN m JIN 3 FIN J'I NC I JZ JUN JUN JUN 3 JUN JUN 5 JUN 6 JUN JUN 8 JUN 9 JUN A JUN 8 JUN t JUN JUN E JUN f JUN 5 JMS 5 JMS 5 JMS 35 JMS 5 JMS 5 JMS 65 JUS 5 JMS 85 JMS 95 JMS A5 JMS 5 JMS t5 JMS 5 JMS E5 JMS F5 JMS M 6 INt & INt I 6 INt 3 INt 3 INt SI INt 5 I INt & 8 INC 9 AS INC I INC ti INC INC 3 EI INC INt 5 A ISZ ISZ C I I 3 I F I 5 ah Mic EI AD F8 AD 5 SUB SUB SUB 3 SUB 3 5 SUB 5 SUB 5 69 SUB & 9 SUB 9 SUB I 9 SUB I AI SUB SUB C9 SUB SUI 3 E9 SUB FI SUB 5 OA LD A LD A LD 3A LD 3 A LD 5A LO 5 IA LD I A LD 8A LO I IA ld I A LD IA LD CA ld DA LD 3 EA LD FA LD 5 XCH IB XCH B XCH 3 XCH 3 XCH 5B XCH 5 I XCH 8 XCH I XCH 8 'I XCH AI XCH I XCH CI XCH 8 XCH 3 EI XCH fi XC" 'I OC BL OC IlL LOM LOM D ldm 5D LOM D lom AO CD LOM FD LOM OE WRM E WMP E WR 3 WPM E WHO 5E WR IE WR WR3 9E RDM AE RDR CE RDO OE A FE RD3 OF CLa 3F CMC SF RAL IF RAR IF OAC AF STC IF OM CF KIP OF OCL EF f 3 5 & 9 MM888ic 3 CHaO CNlllroJNT CN II JC CN3 CNS CN CN] CN, CN' m JT CNIOlsoJNC tn CN II JNZ tn3 tn CNIS Instruction Code Second he die;' is p' of jump Iddr 8 ADD 8 ADD 8 ADD 83 ADD 3 8 ADD 85 ADD 5 86 ADD 6 ADD 88 ADD 8 8 ADD I SA ADD 8B ADD IC ADD 8 ADD 3 Ha C BBL C BIL C3 BIL C BIL C5 IlL C6 BIL C BIL C8 III Ct IlL CA BIL CI III CC IlL CE IlL CF BIL 3 D6 DI D9 DI DE , İ,, 6 INt III III n III 3 III III 3 5 III 5 8 III n III J ISZ III t 6 EI sam EI ADM EE A F CLC F lac F CMA F TCC FI TCI

7 T O'C to QC; V VO 5V t 5%; ; logic "" is defind as the mor8x)sitiw8 oluge,hiv( VOH); logic "" is defined as tn" nigitie VOh8g (VIL, VOL); Unl Ouwt Specified aliv CHtV C\IV NIC \IV LO' NoR NoR MIV Lb NoR tupni Low Vot (E CIockst I Low Volt I High Vol a UID Bul Output Lukge Curent atad U, Sinkl, crt tuptuo Low Om Bus CM SYNC MORMC Ouqa,t R 8t8 Li V L8WI taw V 5, Db\ Db\ Db\ TNWlAOC : m 8 : m Am Am Am ot n n V LIV VO )X( TEST Inpu_t,, Absolute Maximum Ratings Ambient Temperature Under Bi Stor98 TemperCure Input Volt nd Supply Vgge PowerOlaaiption SVotcepserhtiw OC to DC SSC to + SC +O5V to SI,_ Ilol8 I, u, "A8ouf AIe,mum R8't98 ",, u P8'_, " WwC TII" 'ei"" on" nd Inel" pe''on ' " _c, Iu or " or,, coftdil 88 IndIC, In '" "8f_8/ IKIIOftI ' " PK",cal II not ""pi'" DC and Operating Characteristics L Y CURRENT INPUT CHARACTERISTICS ILl tupni U Q"rent IAA Input H9' Vol (ExC8P( Clocks) \\5 Input Low Vol Clock, OUTPUT CHARACTERISTICS Ita CAPACITANCE c Cae Out H9t Volt8g8 CMROM Sinki arent CMRAM Sinti, crem Va5V "s "' 5 5 o R 8t8 u T Le 5 CMRAM OutPUt Rni Data Lirw "" l8 8I 8cit8'8 D8t8 Ius ccn 3a "+3! "3 I pf UoCTOu'PItClP8Cl'Ufa IIA UTV Cll*iunm pf pf I pf "',, "' o5ma,,5v Va5V,,5V,, Lot

8 C O=AT to YCt A kcoc Fal Ti nlud CM SYNC Write Ti nl8t8d CM SYNC Hold Ti ltlo Bus tuotad A Tinw CNYS MORMC MARMC t th Mdt!fA! w c C J 5 t u i I w, t tw,8f,d the of me _t to tak me data bit 8t X 8M X3 t nw8for8 the th ii I"at ;;; jq,tn of _ka"8ft8td F of _di emt_tfwt tfwbitf,v/ F if end or 8 ido YOS' 53 timil m 5, I S" S" N, M M Typical DC Characteristics EWO' SUPL Y CUENT VS TE_ATUE Voo II'IV, il=,a '"" AIINT TI_IATI ra AC Characteristics C VssVoD = 5V 5%, Prame', _mys Min Typ Max Unit Tilt Coition Clock Per iod Clock Ai Time 'os! toh Clock Width Clock DeI8Y, to Clock Del8Y to, Hokj TifM Owing X Ind Ind XX3 Transitk»n Set Tinw (Refll') ns ou Dlta LiNt Lirws Datout Hold Tinw 38) ) 93) 93) 93J nl ns CoUT8 SKJpF D8t8 L8n8I CIJpF D8u u SKJpFSYNC, arom CMRAM CQUTOpF T ACC is D8t8 Iu SYNC 8td Cift8 OUtput tw, to nil wftdl dock II_ tos i 3 All MCsO «,,;;;t_dlln8 It_" ioft or data tit OOt 8t M end X 8 f IIfttW CoATA BUS 8

9 ATAD 8 F Timinl " F T ol to, 8Y*H, 9

1.- L a m e j o r o p c ió n e s c l o na r e l d i s co ( s e e x p li c a r á d es p u é s ).

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