1 Electronics Design Challenges in Sensor Systems THALES NEDERLAND B.V. AND/OR ITS SUPPLIERS THIS INFORMATION CARRIER CONTAINS PROPRIETARY INFORMATION WHICH SHALL NOT BE USED, REPRODUCED OR DISCLOSED TO THIRD PARTIES WITHOUT PRIOR WRITTEN AUTHORIZATION BY THALES NEDERLAND B.V. AND/OR ITS SUPPLIERS, AS APPLICABLE. 1 THALES NEDERLAND B.V.
2 Thales Nederland (TNL) at a glance Established in 1922 ~ employees in 6 locations (4 product development oriented) The largest defence company in the Netherlands Hengelo - Head Office -Naval Systems Integration -Sensors Huizen -Communications & Security Houten -Transportation Systems Delft -D-CIS Lab -Sensors R&D Main centres of excellence: Naval Systems Integration Sensors Vehicle Communication Systems Transportation Systems Eindhoven -Cryogenics Enschede -Technology-Xchange 2 THALES NEDERLAND B.V.
3 Zooming into radar development Locations: Hengelo and Delft 750 employees Ca. 500 research and development 30% MSc, 40% BSc level Ca. 250 production, integration and test 20% MSc and BSc level 40 M total R&D value Customer and self funded 10% (applied) research and knowledge building Worldwide number 2 in Naval Radars First in Integrated Mast Cooperation with approx. 10 universities, 8 institutes and 50 industrial partners (core) Sponsoring of professorships, postacademic education, trainee posts Patent portfolio Approx. 500 patents Thales Nederland University Internal employee training Master classes System Engineering 3 THALES NEDERLAND B.V.
4 Radar tasks in todays missions Radar development challenges Multiple stealthy threats at high speed Complex radar environment in coastal areas 4 THALES NEDERLAND B.V.
5 Integrated mast: a suite of sensors 5 THALES NEDERLAND B.V.
6 D&E Event Themes TNL activities from Antenna to Software (and back) : Wireless: Differences/communalities with wireless (comms) products Pulsed/CW, Modulation/Demodulation, Beamforming, etc. PCB Technology: High Speed Design (Power Integrity/Signal Integrity) HDI (High Density Interconnect) FPGA: Multi-channel Digital Signal Processing Hardware/Software boundaries Agile working Embedded: Open HW Evolution Example of opening systems 6 THALES NEDERLAND B.V.
7 Challenges of AESA Active Electronically Scanned Array (AESA) radar antenna systems require today: Up to 1000 active transmit/receive channels per antenna face Reduced Size, Weight, Power and Cost (SWAP-C) per channel Scalable, open (COTS-aware) system architectures Building-block approach: Lego And in future: Reconfigurable sensor suites Multiple tasks/missions More complex waveforms.. 7 THALES NEDERLAND B.V.
8 Consequences of AESA AESA radar architecture lead to: Increased level of miniaturization and integration Multiple (sometimes all!) electronic domains on same PCA/PCB Further integration of RF functions on chip (GaAs/SiGe/GaN) Tight cooperation with parties like TNO and NXP Further integration digital functions in FPGA devices Massively parallel digital signal processing close to data source, e.g. inside antenna systems/receiver channels Many multi-gigabit transceivers (1000+/system) Deterministic system-level timing & control (in ns region) Small footprint embedded solutions (including on-chip CPUs) Tight integration with mechanical- and thermal design Ensuring reliability at increased power densities (W/cm 2 ) Larger volumes of PCA/PCBs per system: increased BOM cost awareness and industrialisation effort, yield optimization, etc. 8 THALES NEDERLAND B.V.
9 Wireless Challenges Typical RF/microwave design flow Functional chain (RX or TX) is fragmented into multiple small sections Circulator/Isolator, Limiter, LNA, Mixer, Filter, Amplifier, etc. Each section separate stamp PCB with single-function circuit(s) Each section is designed, manufactured and measured in a representative setup (build-up, material, etc.) Measured sections are linked together in simulation (ADS/HFSS) and optimized if needed Form-Fit Function proto board is designed, manufactured, tested Multiple RX/TX channels, mechanical/thermal Topics for possible improvement Earlier attention for manufacturablity (DFM/DFA) Reduce number of stamps PCBs, reduce measurement time Reduce overall leadtime and (NRE) costs, rely (more) on simulation 9 THALES NEDERLAND B.V.
10 Wireless Challenges (2) Micro-packaging of RF chips is non-trivial High junction temperatures, thermal stress (e.g. HPA) Mismatches in thermal expansion coefficients (CTE): Die material (SiGe, GaAs, GaN) Die attach (left, wired bonded) / solder bumps (right, CSP) Package substrate material Package solder joint PCB material (with mounted QFN) Filling method of (thermal) via s in exposed pad Manufacturability/reliability of QFN packages remains concern Thales Group has corporate-level guidelines w.r.t. QFN usage 10 THALES NEDERLAND B.V.
11 PCB Challenges High-Speed Design: Power Integrity (PI) IR-drop analysis VDD=0.9V +/- 3% Impedance profiles: power plane behavior (freq domain, resonance) Analysis/optimization of Power Distribution Network (PDN) 11 THALES NEDERLAND B.V.
12 PCB Challenges (2) High-Speed Design: Signal Integrity (SI) Multi-Gigabit Transceiver: Eye, Jitter, BER, etc. Transmission line: S-parameters models Measured (by VNA/TDR) or extracted (from CAD) Driver/Receiver: IBIS-AMI model XCVR Preemphasis / Equalization optimization 12 THALES NEDERLAND B.V.
13 PCB Challenges (3) New technologies of interest High-Speed Basematerials (compliant to RoHS process!) Nelco, Hitachi, Panasonic, Isola, etc. DDR4 (=evolution) and Hybrid Memory Cube (=revolution) HMC: 3D DRAM stacking, multi-gigabit multi-lane interface Gigabit transceivers technology will reach 56 Gbps soon Fiberoptical modules up to 120 Gbps/400 Gbps (CXP/CDFP) DDR4 HMC CDFP CXP 13 THALES NEDERLAND B.V.
14 PCB Challenges (4) High Density Interconnect (HDI) Micro-via s Copper filling Stacking / staggering. 14 THALES NEDERLAND B.V.
15 FPGA Challenges FPGA capabilities blur the HW/SW boundaries Current high-density FPGA devices require: Team-based design approach with multiple roles Skill sets Accurate, communicative, SW-like but HW-thinking, etc. Common methodology w.r.t. design re-use and -verification Extend FPGA flow with tools in common with SW community FPGA design flow migrated to Linux and multi-core platforms FPGA design flow supported by generic batch scripting: FPGA Back-End : Constraint-driven Synthesis, Place & Route, Timing Analysis, Bitstream Generation Version/Change Management, Collaboration (SVN/Jira, Confluence) Repository/Build/Continuous Integration (Nexus/Maven/Jenkins) CI: Regression-tested Nightly-Builds 15 THALES NEDERLAND B.V.
16 Agile Working Reprogrammable nature of FPGA: Enables incremental/iterative adding of new functionality Perception shifted from Programmable ASIC to Programmable SoC, or Firmware or even Software? What happened to Right-First-Time? For ASIC design increasingly more a must For PCA/PCB design a (very) strong objective One proto needed on average For FPGA design a weakening objective/credo For SW design a non-understood topic Introduction of Agile/Scrum process for FPGA: Currently in progress, promising results, but requiring: New process and terminology: Product Owner, Backlog, Standup, Sprint, Scrum Master, Impediment, Backlog Grooming, Epic, User Story, Story Point, Burn-down Chart, Retrospective, Slacklist, etc. New project management tool: Greenhopper (planning, metrics, etc.) 16 THALES NEDERLAND B.V.
17 Embedded: Open Hardware Evolution OHWR 17 THALES NEDERLAND B.V. Generation BB/X: EE = Electronics Engineer (!) Generation Y/Z: EE = Embedded Engineer (?)
18 Opening up legacy (=closed) systems PCIe FMC Carrier (Generic) Several FMC Mezzanines (Product Specific) 18 THALES NEDERLAND B.V.
19 Summary/Conclusions Technology keeps on moving fast There are plenty of future challenges to tackle Don t try to tackle them alone in this global world Engineering is the art of making what you want from things you can buy Enjoy the tracks and exhibition of the D&E event! Thanks for your attention and feedback! 19 THALES NEDERLAND B.V.
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