Curriculum Vitae. Vladimír Guzma. Flat 16, Moore Court, 2 Dodd Road, WD24 5DA, Watford, United Kingdom Telephone(s) +44 (0)

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1 Curriculum Vitae Personal information Surname(s) / First name(s) Address(es) Flat 16, Moore Court, 2 Dodd Road, WD24 5DA, Watford, United Kingdom Telephone(s) +44 (0) (s) Nationality(-ies) vladimir.guzma@icloud.com Slovak Date of birth 8th of April 1977 Work experience Dates Position Employer June present Leading Software Design Engineer Imagination Technologies Group Dates January May 2013 Department of Pervasive Computing Dates July December 2012 Department of Computer Systems Dates Jan. - June 2008 Position Visiting Researcher at University of Maryland, College Park MD, USA 1

2 Department of Computer Systems Dates Aug Dec Institute of Digital and Computer Systems Dates Jan June 2007 Dates Oct Dec Position Visiting Researcher at Technical University of Eindhoven The Netherlands Dates May Sept Dates July Apr Position Teacher, researcher Dates July Sept Position Internship Institute of Production Engineering Education Dates Name of institution September present Post-graduate studies Tampere Graduate School in Information Science and Engineering (TISE) Tampere University of Technology, Finland Date September June 2000 Title awarded Dipl. Ing. (M.Sc. equivalent), with honors Page 2 - Curriculum vitæ of

3 Institution Technical University of Košice, Faculty of Electrical Engineering and Informatics Slovak Republic Publications Monographs International Journal V. Guzma, Pojem a vlastnosti algoritmov (Algorithms and recursive functions) Master of Science thesis in Slovak, Technical University of Košice, Slovakia, 2000 V. Guzma, T. Pitkänen and J. Takala Use of compiler optimization of software bypassing as a method to improve energy efficiency of exposed data path architectures EURASIP Journal on Embedded Systems (2013) P. Jääskeläinen, V. Guzma and J. Takala Resource conflict detection in simulation of function unit pipelines Journal of System Architectures (2008) P. Kellomäki, V. Guzma, J. Takala Safe Pre-pass Software Bypassing for Transport Triggered Processors Acta Technica Napocensis. Electronica-Telecomunicatii Volume 49, Number 3/2008 International Conference Jiao Xianjun, Chen Canfeng, Pekka Jääskeläinen,, Heikki Berg "A 122Mb/s Turbo Decoder using a Mid-range GPU" accepted for International Wireless Communications & Mobile Computing Conference (IWCMC 2013) Heikki Kultala, Otto Esko, Pekka Jääskeläinen,, Jarmo Takala, Jiao Xianjun, Tommi Zetterman, Heikki Berg "Turbo Decoding on Tailored OpenCL Processor" accepted for International Wireless Communications & Mobile Computing Conference (IWCMC 2013) V. Guzma, T. Pitkänen, J. Takala Effects of Loop Unrolling and Use of Instruction Buffer on Processor Energy Consumption" Int. Symp. System-on-Chip, Tampere, Finland, Nov Page 3 - Curriculum vitæ of

4 V. Guzma, T. Pitkänen, J. Takala "Instruction Buffer with Limited Control Flow and Loop Nest Support" SAMOS XI: Int. Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, Samos, Greece, July V. Guzma, T. Pitkänen, J. Takala Reducing Instruction Memory Energy Consumption by Using Instruction Buffer and After Scheduling Analysis" Int. Symp. System-on-Chip, Tampere, Finland, Sep V. Guzma, T. Pitkänen, P. Kellomäki, J. Takala Reducing Processor Energy Consumption by Compiler Optimization IEEE Workshop on Signal Processing Systems, SiPS 2009, October , Tampere, Finland V. Guzma, Shuvra S. Bhattacharyya, P. Kellomäki, and J. Takala Trade-offs in mapping high-level dataflow graphs onto ASIPs Int. Symp. System-on-Chip, Tampere, Finland, Nov V. Guzma, Shuvra S. Bhattacharyya, P. Kellomäki, and J. Takala An Integrated ASIP Design Flow for Digital Signal Processing Applications (Invited Paper) Int. Symp. Applied Sciences in Biomedical and Communication Technologies, Aalborg, Denmark, Oct V. Guzma, P. Jääskeläinen, P. Kellomäki and J. Takala Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic Embedded Computer Systems: Architectures, Modeling, and Simulation: Proc. 8th Int. Workshop SAMOS VIII(2008) P. Jääskeläinen, V. Guzma, and J. Takala Resource Conflict Detection in Simulation of Function Unit Pipelines Embedded Computer Systems: Architectures, Modeling, and Simulation: Proc. 7th Int. Workshop SAMOS 2007 S. Vassiliadis, M. Bereković, T. D. Hämäläinen, Eds. Lecture Notes in Computer Science, vol. LNCS 4599, pp Springer- Verlag, Berlin, Germany, Page 4 - Curriculum vitæ of

5 P. Jääskeläinen, V. Guzma, A. Cilio and J. Takala Codesign Toolset for Application-Specific Instruction-Set Processors Multimedia on Mobile Devices, Jan 2007, Proc. SPIE Vol. 6507, 65070X Other International V. Guzma, J. Takala Energy Efficient Code Generation for Embedded Processors Poster abstract in "ACACES 2010 Poster Abstracts" Academia Press, Ghent (Belgium), ISBN , pp V. Guzma, P. Kellomäki, and J. Takala Reprogramming Embedded TTAs Poster abstract in "ACACES 2007 Poster Abstracts" Academia Press, Ghent (Belgium), ISBN , pp V. Guzma, P. Jääskeläinen, P. Kellomäki, and J. Takala Instruction Scheduling in TTA Co-Design Environment Poster abstract in "ACACES 2006 Poster Abstracts" Academia Press, Ghent (Belgium), ISBN , pp V. Guzma, J. Heikkinen, A. Cilio, J. Takala, and P. Kellomäki Scheduler Framework for TTA Processors Poster abstract in "ACACES 2005 Poster Abstracts" Academia Press, Ghent (Belgium), ISBN , pp V. Guzma Possibilities for code reorganization in TTAs Workshop On Transport Triggered Architectures November at Nokia Research Center, Visiokatu 1, Tampere, Finland Teaching Name of Institution Name of Course Department of Software Systems Tampere University of Technology Operating Systems (Fall 2000), lectures Object Oriented Programming (Fall 2000), lectures Embedded Systems (Spring 2001), lectures Utilization of Data Structures (several years), lectures Page 5 - Curriculum vitæ of

6 Name of Institution Name of Course Programming I & II (several years), exercises Department of Computer Systems Tampere University of Technology Signal Processors (fall 2011), exercise works,exams (course given as self study) Signal Processors (fall 2010), exercises, lectures, exams Processor Design (spring 2011), exercises Digital Design III (2008/2009), exercises Technical Skills Programming languages General Compilation related Project work Mother tongue(s) Other language(s) C, C++, OpenCL data structures & algorithms, programming for Unix/Linux, compiler backend optimizations dependence analysis, instruction level parallelism extraction, processor resource modeling, instruction scheduling TTA-Codesign Environment, tce.cs.tut.fi, launchpad.net/tce Portable OpenCL, launchpad.net/pocl Slovak English Page 6 - Curriculum vitæ of