AN880. Converting from 8051 to Microchip Assembler: A Quick Reference INTRODUCTION

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1 Converting from 805 to Assembler: A Quick Reference Author: INTRODUCTION Gaurang Kavaiya Technology Inc. When migrating assembly language programs from one family of microcontrollers to another, the first question is almost always: What s the equivalent opcode? Some operations, like addition and subtraction, are self-evident and practically universal. Other instructions may have some subtle differences in syntax or spelling that make direct conversions a bit trickier. Occasionally, some instructions simply don t have a direct equivalent in the target set, or an equivalent exists but is explained in different terms. Another question that arises is that of addressing modes. Typically, Direct and Indirect Addressing modes are standard in all architectures. However, they tend to be different in limitations and feature set. To help simplify the conversion process, this application note provides a table of the instruction set of the bit microcontroller family and their equivalents in the PICmicro instruction sets (Table ). It is organized alphabetically by the 805 instruction mnemonic in the first column, followed by the common description of the operation and the closest equivalent opcode or opcode sequence in the PIC6 and PIC8 instruction sets. In addition, the size of the instructions (in words or bytes, as appropriate) and the number of machine or instruction cycles required for execution are listed for each entry. There are some instructions in the PICmicro architecture that do not have exact equivalents in the 805 architecture. For the convenience of users more familiar with 805 instructions, these are listed separately in Table. They are organized by the PIC8 mnemonic in the first column, followed by the PIC6 equivalent, the closest 805 equivalent or equivalent sequence and the common description. Again, information on the instruction size and execution time is provided. It is important to remember that this reference list is only a starting point for code conversion. There are several considerations to keep in mind when moving code from 8-bit 805 devices to PICmicro devices:. The basic processor architecture is significantly different. The 805 processor core is a von Neumann machine which places data and program memory in the same flat memory space and accesses all information through a single bus. In contrast, all PICmicro processor cores are Harvard machines which use separate data and program memory spaces and two separate busses.. Both the 805 and PICmicro devices use a data memory that is 8 bits wide. With their core architecture, 805 devices are also limited to 8-bit wide program memories as well. PICmicro devices, on the other hand, have program memories that are either 4 bits or 6 bits wide (PIC6 and PIC8 families, respectively). 3. The 805 devices result in greater variance in the size of instructions, from one to three bytes (depending on the operand requirements of the instruction). In contrast, PICmicro instructions are mostly single-word (two bytes) with a small amount of two-word instructions. In general, the first byte of the opcode represents the instruction, while the second byte represents the data or address payload. 003 Technology Inc. DS00880A-page

2 4. Addressing modes in 805 and their equivalents in PIC microcontrollers: a) Direct Addressing: Both the PIC and the 805 architecture support the Direct Addressing mode, where an 8-bit address is specified in the operand. On the 805, only the lower 8 bytes of RAM and SFRs can be accessed in this mode. On the PIC architecture, the entire data memory is accessible in this mode. b) Indirect Addressing: Both the PIC MCUs and the 805 support this mode, where a register contains the address of the operand. The 805 cannot access SFRs in this mode. It can access both internal and external memory in this mode. PIC devices can access whole data memory and SFRs in this mode. PIC devices cannot access external memory data in this mode (some devices on the PIC8 architecture offer external data memory; however, it is accessed in Indexed Addressing mode). The 805 uses R0, R and DPTR for indirect access. PIC devices use File Select Registers (FSR) for Indirect Addressing. The FSRs also provide the options for preincrement, post-increment, post-decrement and the use of 8-bit offsets on PIC8 devices. c) Register Instructions: The register banks on the 805 can be accessed by certain instructions that carry 3-bit information. This mode is available only on the 805. d) Register Specific Instructions: On the 805, some instructions are specific to certain registers (e.g., CPL A). On the PIC MCUs, most of the instructions can work on any register (e.g., same instruction as COMF M, F). e) Immediate Constants: The value of constant (literal) is in opcode. On the 805, the Immediate Constants is one addressing mode and it can be used with many instructions. In PIC architecture, different equivalent instructions handle Immediate Constants. These are documented under literal-based operations. f) Indexed Addressing: Only program memory is accessed in this mode on the 805. It is used to read the program memory content. On the PIC6, this is implemented through program memory access SFRs. On the PIC8, TBLRD instructions provide the read access to program memory. This instruction also provides options to pre-increment, postincrement and post-decrement the access pointers. The PIC architecture provides a way to write to program memory. The PIC8 implements various options for TBLWT (table write, similar to table read). The 805 architecture does not provide instructions to write to program memory. The external data memory on some of the PIC8 devices can be accessed in this mode. 5. The 805 implements 8 bits of bit addressable memory. Some of the instructions can directly operate on these bit variables. Some of the SFRs are accessible in bit addressing modes. In PIC architecture, any bit in data memory is accessible through bit access instructions. Some of the instructions with bit addressing modes in the 805 do not have equivalent instructions in PIC architecture. 6. The classic 805 architecture supports only 384 bytes of internal RAM. However, the variant of the architecture with expanded RAM exists. This provides additional internal RAM. This RAM is mapped as external RAM and one needs to access it in a way similar to external RAM (e.g., MOVX instruction). On the PIC devices, the entire internal RAM (up to 4K on the PIC8) is accessed in the same way through direct and indirect addressing. 7. The equivalent register and FSR name 4-bit location/function are different in both architectures (e.g., PSW in the 805 is equivalent to the Status register in PICmicro devices). Users are encouraged to review the documentation for both architectures. All of these differences can significantly change the way that both data and logical program structures are implemented. This is particularly true when indexed and indirect addressing methods are used to direct code execution. Users are encouraged to review existing application notes for the appropriate family to get an idea of how different applications are implemented. DS00880A-page 003 Technology Inc.

3 TABLE : 805 INSTRUCTIONS AND THEIR MICROCHIP EQUIVALENTS 805 PIC6 PIC8 Instruction Bytes Cycles Instruction(s) Words Cycles Instruction(s) Bytes Cycles ACALL Absolute Call CALL RCALL rel ADD ADD A #data - Add without Carry () ADDWF M, F Add Literal and WREG (Accumulator) () ADDLW ADDC - Add with Carry () BTFSC STATUS, C INCF M, F ADDWF M, F ADDWF M, F ADDLW 3 3 ADDWFC M, F AJMP Absolute Jump GOTO Addr BRA rel ANL ANL A #data Logical AND () Logical AND Literal with WREG (Accumulator) () ANDWF M, F ANDLW ANDWF M, F ANDLW ANL Bit Logical AND for bit variables No equivalent instruction CJNE 3 Compare and Jump if Not Equal () SUBWF M, W BTFSS STATUS, Z GOTO Addr CLR A Clear Accumulator (5) Clear Memory CLRW CLRF M, F 3 4 CPFSEQ M BRA Addr CLRF WREG CLRF M, F 4 4 CLR bit - Clear bit BCF M, F BCF M, F CPL A Complement Accumulator (/Memory) (5) COMF M, F COMF M, F CPL bit - Complement bit MOVLW # XORWF M, F BTG M, F Legend: For PICmicro mnemonics: M = memory location, n = specific bit location, F = file register, addr = full 3-bit or 0-bit address, rel = 8-bit or -bit offset, WREG = W register (equivalent to accumulator in 805 architecture). Note : Direct or indirect addressing version of instruction depending on the registers selected by M and F; equivalent to Direct, Indirect or Indexed Addressing modes in 805 architecture. : Immediate addressing version of instruction; equivalent to Immediate Addressing mode in 805 architecture. 3: Reference routines are the 8-bit fixed-point Multiply and Divide routines specified in the application note, AN67, Fixed Point Routines (DS0067). 4: Reference routine for PIC8 devices is the 8-bit fixed-point Divide routine provided with the MPLAB C8 C compiler. 5: Register specific instruction on 805 architecture. On PICmicro devices, it works on all memory locations. 003 Technology Inc. DS00880A-page 3

4 TABLE : 805 INSTRUCTIONS AND THEIR MICROCHIP EQUIVALENTS (CONTINUED) 805 Instruction Bytes Cycles DAA Decimal Adjust Accumulator ADDLW 0x06 BTFSS STATUS, DC GOTO $+3 ADDLW 0x0 GOTO $+ ADDLW 0xFA ADDLW 0x60 BTFSS STATUS, DC ADDLW 0xA0 9 0 DAW DEC - Decrement () DECF M, F DECF M, F DIV 4 Divide Divide Routine 4 69 Divide Routine DJNZ -3 Decrement and Jump if Not Zero DECF M, F BTFSS STATUS, Z 3 4 DCFSNZ M, F BRA rel 4 3 INC - Increment () INCF M, F INCF M, F INC DPTR Increment Data Pointer INCF FSR, F INFSNZ FSR0L, F INCF FSR0H, F JB Bit, rel 3 Jump if bit set BTFSC M, n JBC Bit, rel 3 Jump if bit set and Clear bit No equivalent instruction JC rel Jump if Carry is set BTFSC STATUS, C 3 BTFSC M, n BRA rel BC rel + DPTR Jump Indirect MOVWF PCL MOVWF PCL JNB bit, rel 3 Jump if bit is not set BTFSS M, n PIC6 PIC8 Instruction(s) Words Cycles Instruction(s) Bytes Cycles 3 BTFSS M, n BRA rel 4 3 Legend: For PICmicro mnemonics: M = memory location, n = specific bit location, F = file register, addr = full 3-bit or 0-bit address, rel = 8-bit or -bit offset, WREG = W register (equivalent to accumulator in 805 architecture). Note : Direct or indirect addressing version of instruction depending on the registers selected by M and F; equivalent to Direct, Indirect or Indexed Addressing modes in 805 architecture. : Immediate addressing version of instruction; equivalent to Immediate Addressing mode in 805 architecture. 3: Reference routines are the 8-bit fixed-point Multiply and Divide routines specified in the application note, AN67, Fixed Point Routines (DS0067). 4: Reference routine for PIC8 devices is the 8-bit fixed-point Divide routine provided with the MPLAB C8 C compiler. 5: Register specific instruction on 805 architecture. On PICmicro devices, it works on all memory locations. DS00880A-page Technology Inc.

5 TABLE : 805 INSTRUCTIONS AND THEIR MICROCHIP EQUIVALENTS (CONTINUED) 805 Instruction Bytes Cycles JNC rel Jump if Carry not set BTFSS STATUS, C JNZ rel Jump if Accumulator Not Zero BTFSS STATUS, Z JZ rel Jump if Accumulator Zero BTFSC STATUS, Z 3 BNC rel 3 BNZ rel 3 BZ rel LCALL addr6 3 Long Call CALL Addr CALL Addr 4 3 LJMP addr6 3 Long Jump GOTO Addr GOTO Addr 4 3 MOV N, M -3 - Move byte variable MOVF M, W MOVFF N, M 4 MOV A, #data Move Literal to WREG (Accumulator) MOVWF N MOVLW # MOVLW # MOV Db Sb - Move bit Data No equivalent instruction MOV DPTR, #data6 3 Load Data Pointer with a 6-bit constant MOVLW data MOVWF FSR PIC6 PIC8 Instruction(s) Words Cycles Instruction(s) Bytes Cycles LFSR data MOVC Move Code byte No equivalent PIC6 instruction TBLRD* MOVX Move External No equivalent PIC6 instruction TBLRD* MUL AB 4 Multiply (5) Multiply Routine 74 MULWF M, F NOP No NOP NOP ORL -3 - Logical OR for byte variables () IORWF M, F IORWF M, F ORL Bit Logical OR for bit variables No equivalent instruction POP Pop from Stack No equivalent PIC6 instruction POP PUSH Push from Stack No equivalent PIC6 instruction PUSH RET Return from Subroutine RETURN RETURN RETI Return from Interrupt RETFIE RETFIE Legend: For PICmicro mnemonics: M = memory location, n = specific bit location, F = file register, addr = full 3-bit or 0-bit address, rel = 8-bit or -bit offset, WREG = W register (equivalent to accumulator in 805 architecture). Note : Direct or indirect addressing version of instruction depending on the registers selected by M and F; equivalent to Direct, Indirect or Indexed Addressing modes in 805 architecture. : Immediate addressing version of instruction; equivalent to Immediate Addressing mode in 805 architecture. 3: Reference routines are the 8-bit fixed-point Multiply and Divide routines specified in the application note, AN67, Fixed Point Routines (DS0067). 4: Reference routine for PIC8 devices is the 8-bit fixed-point Divide routine provided with the MPLAB C8 C compiler. 5: Register specific instruction on 805 architecture. On PICmicro devices, it works on all memory locations. 003 Technology Inc. DS00880A-page 5

6 TABLE : 805 INSTRUCTIONS AND THEIR MICROCHIP EQUIVALENTS (CONTINUED) 805 RL Rotate Accumulator Left No equivalent PIC6 instruction RLNCF M, F RLC Rotate Accumulator Left through Carry () RLF M, F RLCF M, F RRC Rotate Accumulator Right () No equivalent PIC6 instruction RRNCF M, F RRC Rotate Accumulator Right through Carry () RRF M, F RRCF M, F SETB - Set bit BSF M, F BSF M, F SJMP rel Short Jump BRA rel SUBB - Subtract with Borrow () BTFSS STATUS, C INCF M, F SUBWF M, F SUBWFB M, F SWAP A Swap nibbles within the Accumulator (5) SWAPF M, F SWAPF M, F XCH XCHD Instruction Bytes Cycles XRL XRL A #data Exchange Accumulator with byte variable Exchange Digit Logical Exclusive OR for byte variables () Exclusive OR Literal with WREG (Accumulator) PIC6 PIC8 Instruction(s) Words Cycles Instruction(s) Bytes Cycles No equivalent instruction XORWF M, F XORLW XORWF M, F XORLW Legend: For PICmicro mnemonics: M = memory location, n = specific bit location, F = file register, addr = full 3-bit or 0-bit address, rel = 8-bit or -bit offset, WREG = W register (equivalent to accumulator in 805 architecture). Note : Direct or indirect addressing version of instruction depending on the registers selected by M and F; equivalent to Direct, Indirect or Indexed Addressing modes in 805 architecture. : Immediate addressing version of instruction; equivalent to Immediate Addressing mode in 805 architecture. 3: Reference routines are the 8-bit fixed-point Multiply and Divide routines specified in the application note, AN67, Fixed Point Routines (DS0067). 4: Reference routine for PIC8 devices is the 8-bit fixed-point Divide routine provided with the MPLAB C8 C compiler. 5: Register specific instruction on 805 architecture. On PICmicro devices, it works on all memory locations. DS00880A-page Technology Inc.

7 TABLE : MICROCHIP PIC8 INSTRUCTIONS WITHOUT EXACT EQUIVALENTS IN THE 805 FAMILY 805 Equivalent to PIC8 #Bytes #Cycles Equivalent to PIC6 #Words #Cycles Name #Bytes #Cycles BN rel BTFSC M, 7 GOTO Addr BNN rel BTFSS M, 7 GOTO Addr BNOV rel BTFSS STATUS, OV GOTO Addr BOV rel BTFSC STATUS, OV GOTO Addr 3 Branch if Negative No equivalent instruction 3 Branch if Not Negative No equivalent instruction 3 Branch if Not Overflow JNB PSW. rel 3 3 Branch if Overflow JB PSW. rel 3 CLRWDT CLRWDT Clear Watchdog Timer No equivalent instruction CPFSGT M No equivalent PIC6 instruction Compare M with W, skip if M > W CPFSLT M No equivalent PIC6 instruction Compare M with W, skip if M < W DECFSZ M, F DECFSZ M, F Decrement M, skip if 0 () DEC JNZ INCFSZ M, F INCFSZ M, F Increment M, skip if 0 () INC JNZ INFSNZ M, F No equivalent PIC6 instruction Increment M, skip if not 0 () INC JZ MOVLB # BSF/BCF STATUS, RP0 BSF/BCF STATUS, RP NEGF M, F COMF M, F INCF M, F No equivalent instruction No equivalent instruction Move Literal to BSR CLR/SETB PSW.3 CLR/SETB PSW.4 Negate (Two s Complement) XCH A, M CPL A INC A XCH A, M RESET No equivalent PIC6 instruction Reset No equivalent instruction RETLW RETLW Return Literal to W MOV A # RET Legend: For PICmicro mnemonics: M = memory location, n = specific bit location, F = file register, addr = full 3-bit or 0-bit address, rel = 8-bit or -bit offset, WREG = W register (equivalent to accumulator in 805 architecture). Note : Direct or indirect addressing version of instruction depending on the registers selected by M and F; equivalent to Direct, Indirect or Indexed Addressing modes in 805 architecture. 003 Technology Inc. DS00880A-page 7

8 TABLE : MICROCHIP PIC8 INSTRUCTIONS WITHOUT EXACT EQUIVALENTS IN THE 805 FAMILY 805 Equivalent to PIC8 #Bytes #Cycles Equivalent to PIC6 #Words #Cycles Name #Bytes #Cycles SETF MOVLW 0xFF MOVWF M SLEEP SLEEP Enter Sleep (Power-down) mode Set File to all s MOV M, # 3 MOV A, #0x ORL PCON, A SUBWF M, F SUBWF M, F Subtract W from M () No equivalent instruction TBLRD (*+; *-; +*) No equivalent PIC6 instruction Table Read with pointer manipulation TBLWT (*; *+; *-; +*) No equivalent PIC6 instruction Table Write with pointer manipulation No equivalent instruction No equivalent instruction 4 TSTFSZ M No equivalent PIC6 instruction Test M, skip if 0 CJNE M, #0, rel 3 Legend: For PICmicro mnemonics: M = memory location, n = specific bit location, F = file register, addr = full 3-bit or 0-bit address, rel = 8-bit or -bit offset, WREG = W register (equivalent to accumulator in 805 architecture). Note : Direct or indirect addressing version of instruction depending on the registers selected by M and F; equivalent to Direct, Indirect or Indexed Addressing modes in 805 architecture. DS00880A-page Technology Inc.

9 Note the following details of the code protection feature on devices: products meet the specification contained in their particular Data Sheet. believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the products in a manner outside the operating specifications contained in 's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. is willing to work with the customer who is concerned about the integrity of their code. Neither nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at are committed to continuously improving the code protection features of our products. Attempts to break microchip s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of s products as critical components in life support systems is not authorized except with express written approval by. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The name and logo, the logo, Accuron, dspic, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microid, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Technology Incorporated in the U.S.A. Application Maestro, dspicdem, dspicdem.net, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzylab, In-Circuit Serial Programming, ICSP, ICEPIC, microport, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rflab, rfpic, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 003, Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 999 and Mountain View, California in March 00. The Company s quality system processes and procedures are QS-9000 compliant for its PICmicro 8-bit MCUs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, s quality system for the design and manufacture of development systems is ISO 900 certified. DS00880A-page Technology Inc.

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