PIC18F23K20/24K20/25K20/26K20/ 43K20/44K20/45K20/46K20 Data Sheet

Transcription

1 PIC18F23K20/24K20/25K20/26K20/ 43K20/44K20/45K20/46K20 Data Sheet 28/40/44-Pin Flash Microcontrollers with nanowatt XLP Technology DS41303G

2 Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dspic, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfpic and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dspicdem, dspicdem.net, dspicworks, dsspeak, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mtouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC 32 logo, REAL ICE, rflab, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company s quality system processes and procedures are for its PIC MCUs and dspic DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS41303G-page 2

3 28/40/44-Pin Flash Microcontrollers with nanowatt XLP Technology High-Performance RISC CPU: C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code Up to 1024 bytes Data EEPROM Up to 64 Kbytes Linear Program Memory Addressing Up to 3936 bytes Linear Data Memory Addressing Up to 16 MIPS Operation 16-bit Wide Instructions, 8-bit Wide Data Path Priority Levels for Interrupts 31-Level, Software Accessible Hardware Stack 8 x 8 Single-Cycle Hardware Multiplier Flexible Oscillator Structure: Precision 16 MHz Internal Oscillator Block: - Factory calibrated to ± 1% - Software selectable frequencies range of 31 khz to 16 MHz - 64 MHz performance available using PLL no external components required Four Crystal modes up to 64 MHz Two External Clock modes up to 64 MHz 4X Phase Lock Loop (PLL) Secondary Oscillator using 32 khz Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops - Two-Speed Oscillator Start-up Special Microcontroller Features: Operating Voltage Range: 1.8V to 3.6V Self-Programmable under Software Control Programmable 16-Level High/Low-Voltage Detection (HLVD) module: - Interrupt on High/Low-Voltage Detection Programmable Brown-out Reset (BOR): - With software enable option Extended Watchdog Timer (WDT): - Programmable period from 4 ms to 131s Single-Supply 3V In-Circuit Serial Programming (ICSP ) via Two Pins In-Circuit Debug (ICD) via Two Pins Extreme Low-Power Management with nanowatt XLP: Sleep mode: < V Watchdog Timer: < V Timer1 Oscillator: < khz and 1.8V Analog Features: Analog-to-Digital Converter (ADC) module: - 10-bit resolution, 13 External Channels - Auto-acquisition capability - Conversion available during Sleep - 1.2V Fixed Voltage Reference (FVR) channel - Independent input multiplexing Analog Comparator module: - Two rail-to-rail analog comparators - Independent input multiplexing Voltage Reference (CVREF) module - Programmable (% VDD), 16 steps - Two 16-level voltage ranges using VREF pins Peripheral Highlights: Up to 35 I/O Pins plus 1 Input-only Pin: - High-Current Sink/Source 25 ma/25 ma - Three programmable external interrupts - Four programmable interrupt-on-change - Eight programmable weak pull-ups - Programmable slew rate Capture/Compare/PWM (CCP) module Enhanced CCP (ECCP) module: - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-Shutdown and Auto-Restart Master Synchronous Serial Port (MSSP) module - 3-wire SPI (supports all 4 modes) - I 2 C Master and Slave modes with address mask Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module: - Supports RS-485, RS-232 and LIN - RS-232 operation using internal oscillator - Auto-Wake-up on Break - Auto-Baud Detect DS41303G-page 3

4 - Device Program Memory Flash (bytes) # Single-Word Instructions Data Memory SRAM (bytes) EEPROM (bytes) I/O (1) 10-bit A/D (ch) (2) CCP/ ECCP (PWM) PIC18F46K20 64k /1 Y Y 1 2 1/3 Note 1: One pin is input only. 2: Channel count includes internal fixed voltage reference channel. SPI MSSP Master I 2 C EUSART Comp. Timers 8/16-bit PIC18F23K20 8K /1 Y Y 1 2 1/3 PIC18F24K20 16K /1 Y Y 1 2 1/3 PIC18F25K20 32K /1 Y Y 1 2 1/3 PIC18F26K20 64k /1 Y Y 1 2 1/3 PIC18F43K20 8K /1 Y Y 1 2 1/3 PIC18F44K20 16K /1 Y Y 1 2 1/3 PIC18F45K20 32K /1 Y Y 1 2 1/3 DS41303G-page 4

5 Pin Diagrams 28-pin PDIP, SOIC, SSOP MCLR/VPP/RE3 RA0/AN0/C12IN0- RA1/AN1/C12IN1- RA2/AN2/VREF-/CVREF/C2IN+ RA3/AN3/VREF+/C1IN+ RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT VSS OSC1/CLKIN/RA7 OSC2/CLKOUT/RA6 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2 (1) RC2/CCP1/P1A RC3/SCK/SCL PIC18F23K20 PIC18F24K20 PIC18F25K20 PIC18F26K RB7/KBI3/PGD RB6//KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11/P1D RB3/AN9/C12IN2-/CCP2 (1) RB2/INT2/AN8/P1B RB1/INT1/AN10/C12IN3-/P1C RB0/INT0/FLT0/AN12 VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA 40-pin PDIP MCLR/VPP/RE3 RA0/AN0/C12IN0- RA1/AN1/C12IN1- RA2/AN2/VREF-/CVREF/C2IN+ RA3/AN3/VREF+/C1IN+ RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN/RA7 OSC2/CLKOUT/RA6 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2 (1) RC2/CCP1/P1A RC3/SCK/SCL RD0/PSP0 RD1/PSP PIC18F43K20 PIC18F44K20 PIC18F45K20 PIC18F46K RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 RB3/AN9/C12IN2-/CCP2 (1) RB2/INT2/AN8 RB1/INT1/AN10/C12IN3- RB0/INT0/FLT0/AN12 VDD VSS RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 28-pin QFN/UQFN (2) RA1/AN1/C12IN1- RA0/AN0/C12IN0- MCLR/VPP/RE3 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11/P1D RA2/AN2/VREF-/CVREF/C2IN+ RA3/AN3/VREF+/C1IN+ RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT VSS OSC1/CLKIN/RA7 OSC2/CLKOUT/RA PIC18F23K20 PIC18F24K20 PIC18F25K20 PIC18F26K20 RB3/AN9/C12IN2-/CCP2 (1) RB2/INT2/AN8/P1B RB1/INT1/AN10/C12IN3-/P1C RB0/INT0/FLT0/AN12 VDD VSS RC7/RX/DT Note 1: RB3 is the alternate pin for CCP2 multiplexing. 2: UQFN package availability applies only to PIC18F23K20. RC0/T1OSO/T13CKI RC1/T1OSI/CCP2 (1) RC2/CCP1/P1A RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK DS41303G-page 5

6 Pin Diagrams (Cont. d) 44-pin TQFP RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1/P1A RC1/T1OSI/CCP2 (1) NC RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D VSS VDD RB0/INT0/FLT0/AN12 RB1/INT1/AN10/C12IN3- RB2/INT2/AN8 RB3/AN9/C12IN2-/CCP2 (1) PIC18F43K20 PIC18F44K20 PIC18F45K20 PIC18F46K NC RC0/T1OSO/T13CKI OSC2/CLKOUT/RA6 OSC1/CLKIN/RA7 VSS VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS/HLVDIN/C2OUT RA4/T0CKI/C1OUT 44-pin QFN NC NC RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0/C12IN0- RA1/AN1/C12IN1- RA2/AN2/VREF-/CVREF/C2IN+ RA3/AN3/VREF+/C1IN+ RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1/P1A RC1/T1OSI/CCP2 (1) RC0/T1OSO/T13CKI RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D VSS VDD VDD RB0/INT0/FLT0/AN12 RB1/INT1/AN10/C12IN3- RB2/INT2/AN PIC18F43K20 PIC18F44K20 PIC18F45K20 PIC18F46K OSC2/CLKOUT/RA6 OSC1/CLKIN/RA7 VSS VSS VDD VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS/HLVDIN/C2OUT RA4/T0CKI/C1OUT Note 1: RB3 is the alternate pin for CCP2 multiplexing. RB3/AN9/C12IN2-/CCP2 (1) NC RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0/C12IN0- RA1/AN1/C12IN1- RA2/AN2/VREF-/CVREF/C2IN+ RA3/AN3/VREF+/C1IN+ DS41303G-page 6

7 TABLE 1: PIC18F4XK20 PIN SUMMARY DIL Pin TQFP Pin QFN Pin I/O Analog Comparator Reference ECCP RA0 AN0 C12IN RA1 AN1 C12IN RA2 AN2 C2IN+ VREF-/ CVREF RA3 AN3 C1IN+ VREF RA4 C1OUT T0CKI RA5 AN4 C2OUT HLVDIN SS RA6 OSC2/ CLKOUT RA7 OSC1/CLKIN RB0 AN12 FLT0 INT0 Yes RB1 AN10 C12IN3- INT1 Yes RB2 AN8 INT2 Yes RB3 AN9 C12IN2- CCP2 (1) Yes RB4 AN11 KBI0 Yes RB5 KBI1 Yes PGM RB6 KBI2 Yes PGC RB7 KBI3 Yes PGD RC0 T1OSO/ T13CKI RC1 CCP2 (2) T1OSI RC2 CCP1/ P1A RC3 SCK/ SCL RC4 SDI/ SDA RC5 SDO RC6 TX/CK RC7 RX/DT RD0 PSP RD1 PSP RD2 PSP RD3 PSP RD4 PSP RD5 P1B PSP RD6 P1C PSP RD7 P1D PSP RE0 AN5 RD RE1 AN6 WR RE2 AN7 CS EUSART MSSP Timers Slave Interrupts Pull-up Basic RE3 (3) MCLR/VPP VDD VDD VSS VSS NC 8 VDD NC 29 VDD - NC 31 VSS Note 1: CCP2 multiplexed with RB3 when CONFIG3H<0> = 0 2: CCP2 multiplexed with RC1 when CONFIG3H<0> = 1 3: Input-only. DS41303G-page 7

8 TABLE 2: PIC18F2XK20 PIN SUMMARY Pin DIL Pin QUAD I/O Analog Comparator Reference ECCP EUSART MSSP Timers Slave Interrupts Pull-up Basic 2 27 RA0 AN0 C12IN RA1 AN1 C12IN1-4 1 RA2 AN2 C2IN+ VREF-/ CVREF 5 2 RA3 AN3 C1IN+ VREF+ 6 3 RA4 C1OUT T0CKI 7 4 RA5 AN4 C2OUT HLVDIN SS 10 7 RA6 OSC2/ CLKOUT 9 6 RA7 OSC1/ CLKIN RB0 AN12 FLT0 INT0 Yes RB1 AN10 C12IN3- P1C INT1 Yes RB2 AN8 P1B INT2 Yes RB3 AN9 C12IN2- CCP2 (1) Yes RB4 AN11 P1D KBI0 Yes RB5 KBI1 Yes PGM RB6 KBI2 Yes PGC RB7 KBI3 Yes PGD 11 8 RC0 T1OSO/ T13CKI 12 9 RC1 CCP2 (2) T1OSI RC2 CCP1/ P1A RC3 SCK/ SCL RC4 SDI/ SDA RC5 SDO RC6 TX/CK RC7 RX/DT 1 26 RE3 (3) MCLR/ VPP 8 5 VSS VSS VDD Note 1: CCP2 multiplexed with RB3 when CONFIG3H<0> = 0 2: CCP2 multiplexed with RC1 when CONFIG3H<0> = 1 3: Input-only DS41303G-page 8

9 Table of Contents 1.0 Device Overview Oscillator Module (With Fail-Safe Clock Monitor) Power-Managed Modes Reset Memory Organization Flash Program Memory Data EEPROM Memory x 8 Hardware Multiplier Interrupts I/O Ports Capture/Compare/PWM (CCP) Modules Timer0 Module Timer1 Module Timer2 Module Timer3 Module Enhanced Capture/Compare/PWM (ECCP) Module Master Synchronous Serial Port (MSSP) Module Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) Analog-to-Digital Converter (ADC) Module Comparator Module Voltage References High/Low-Voltage Detect (HLVD) Special Features of the CPU Instruction Set Summary Development Support Electrical Characteristics DC and AC Characteristics Graphs and Tables Packaging Information Appendix A: Revision History Appendix B: Device Differences Index The Microchip Web Site Customer Change Notification Service Customer Support Reader Response Product Identification System DS41303G-page 9

10 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via at or fax the Reader Response Form in the back of this data sheet to (480) We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: Microchip s Worldwide Web site; Your local Microchip sales office (see last page) The Microchip Corporate Literature Center; U.S. FAX: (480) When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at to receive the most current information on all of our products. DS41303G-page 10

11 1.0 DEVICE OVERVIEW This document contains device specific information for the following devices: PIC18F23K20 PIC18F24K20 PIC18F25K20 PIC18F26K20 This family offers the advantages of all PIC18 microcontrollers namely, high computational performance at an economical price with the addition of high-endurance, Flash program memory. On top of these features, the PIC18F2XK20/4XK20 family introduces design enhancements that make these microcontrollers a logical choice for many highperformance, power sensitive applications. 1.1 New Core Features PIC18F43K20 PIC18F44K20 PIC18F45K20 PIC18F46K nanowatt TECHNOLOGY All of the devices in the PIC18F2XK20/4XK20 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. On-the-fly Mode Switching: The powermanaged modes are invoked by user code during operation, allowing the user to incorporate powersaving ideas into their application s software design. Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 26.0 Electrical Characteristics for values MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F2XK20/4XK20 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. These include: Four Crystal modes, using crystals or ceramic resonators Two External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O) Two External RC Oscillator modes with the same pin options as the External Clock modes An internal oscillator block which contains a 16 MHz HFINTOSC oscillator and a 31 khz LFINTOSC oscillator which together provide 8 user selectable clock frequencies, from 31 khz to 16 MHz. This option frees the two oscillator pins for use as additional general purpose I/O. A Phase Lock Loop (PLL) frequency multiplier, available to both the high-speed crystal and internal oscillator modes, which allows clock speeds of up to 64 MHz. Used with the internal oscillator, the PLL gives users a complete selection of clock speeds, from 31 khz to 64 MHz all without using an external crystal or clock circuit. Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the LFINTOSC. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued operation or a safe application shutdown. Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available. DS41303G-page 11

12 1.2 Other Special Features Memory Endurance: The Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles up to 10K for program memory and 100K for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. Self-programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. Extended Instruction Set: The PIC18F2XK20/ 4XK20 family introduces an optional extension to the PIC18 instruction set, which adds 8 new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as C. Enhanced CCP module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include: - Auto-Shutdown, for disabling PWM outputs on interrupt or other select conditions - Auto-Restart, to reactivate outputs once the condition has cleared - Output steering to selectively enable one or more of 4 outputs to provide the PWM signal. Enhanced Addressable USART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN bus protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the USART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). 10-bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit postscaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section 26.0 Electrical Characteristics for time-out periods. 1.3 Details on Individual Family Members Devices in the PIC18F2XK20/4XK20 family are available in 28-pin and 40/44-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in five ways: 1. Flash program memory (8 Kbytes for PIC18F23K20/43K20 devices, 16 Kbytes for PIC18F24K20/44K20 devices, 32 Kbytes for PIC18F25K20/45K20 AND 64 Kbytes for PIC18F26K20/46K20). 2. A/D channels (11 for 28-pin devices, 14 for 40/44-pin devices). 3. I/O ports (3 bidirectional ports on 28-pin devices, 5 bidirectional ports on 40/44-pin devices). 4. Parallel Slave Port (present only on 40/44-pin devices). All other features for devices in this family are identical. These are summarized in Table 1-1. The pinouts for all devices are listed in the pin summary tables: Table 1 and Table 2, and I/O description tables: Table 1-2 and Table 1-3. DS41303G-page 12

13 DS41303G-page 13 TABLE 1-1: DEVICE FEATURES Features PIC18F23K20 PIC18F24K20 PIC18F25K20 PIC18F26K20 PIC18F43K20 PIC18F44K20 PIC18F45K20 PIC18F46K20 Operating Frequency (2) DC 64 MHz DC 64 MHz DC 64 MHz DC 64 MHz DC 64 MHz DC 64 MHz DC 64 MHz DC 64 MHz Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Data EEPROM Memory (Bytes) Interrupt Sources I/O Ports A, B, C, (E) (1) A, B, C, (E) (1) A, B, C, (E) (1) A, B, C, (E) (1) A, B, C, D, E A, B, C, D, E A, B, C, D, E A, B, C, D, E Timers Capture/Compare/PWM Modules Enhanced Capture/ Compare/PWM Modules Serial Communications MSSP, Enhanced USART MSSP, Enhanced USART MSSP, Enhanced USART MSSP, Enhanced USART MSSP, Enhanced USART MSSP, Enhanced USART MSSP, Enhanced USART MSSP, Enhanced USART Parallel Communications (PSP) No No No No Yes Yes Yes Yes 10-bit Analog-to-Digital Module Resets (and Delays) 1 internal plus 10 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT Programmable High/ Low-Voltage Detect Programmable Brownout Reset Instruction Set 75 Instructions; 83 with Extended Instruction Set enabled Packages 28-pin PDIP 28-pin SOIC 28-pin QFN 28-pin SSOP 28-pin UQFN 1 internal plus 10 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT 1 internal plus 10 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT 1 internal plus 10 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT 1 internal plus 13 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT 1 internal plus 13 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT 1 internal plus 13 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT 1 internal plus 13 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 75 Instructions; 83 with Extended Instruction Set enabled 28-pin PDIP 28-pin SOIC 28-pin QFN 28-pin SSOP 75 Instructions; 83 with Extended Instruction Set enabled 28-pin PDIP 28-pin SOIC 28-pin QFN 28-pin SSOP 75 Instructions; 83 with Extended Instruction Set enabled 28-pin PDIP 28-pin SOIC 28-pin QFN 28-pin SSOP 75 Instructions; 83 with Extended Instruction Set enabled 40-pin PDIP 44-pin QFN 44-pin TQFP Note 1: PORTE contains the single RE3 read-only bit. The LATE and TRISE registers are not implemented. 2: Frequency range shown applies to industrial range devices only. Maximum frequency for extended range devices is 48 MHz. 75 Instructions; 83 with Extended Instruction Set enabled 40-pin PDIP 44-pin QFN 44-pin TQFP 75 Instructions; 83 with Extended Instruction Set enabled 40-pin PDIP 44-pin QFN 44-pin TQFP 75 Instructions; 83 with Extended Instruction Set enabled 40-pin PDIP 44-pin QFN 44-pin TQFP PIC18F2XK20/4XK20

14 FIGURE 1-1: Table Pointer<21> PIC18F2XK20 (28-PIN) BLOCK DIAGRAM Data Bus<8> inc/dec logic PCLATU PCLATH PCU PCH PCL Program Counter Data Latch Data Memory Address Latch 12 Data Address<12> PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT OSC2/CLKOUT (3) /RA6 OSC1/CLKIN (3) /RA7 Address Latch Program Memory (8/16/32/64 Kbytes) Data Latch 8 Instruction Bus <16> 31-Level Stack STKPTR Table Latch ROM Latch IR BSR FSR0 Access Bank FSR1 FSR2 12 inc/dec logic Address Decode PORTB RB0/INT0/FLT0/AN12 RB1/INT1/AN10/C12IN3- RB2/INT2/AN8 RB3/AN9/CCP2 (1) /C12IN2- RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD OSC1 (3) OSC2 (3) T1OSI T1OSO MCLR (2) VDD, VSS Internal Oscillator Block Instruction Decode and Control LFINTOSC Oscillator 16 MHz Oscillator Single-Supply Programming In-Circuit Debugger State machine control signals Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Fail-Safe Clock Monitor 8 PRODH PRODL 8 x 8 Multiply 3 8 BITOP W ALU<8> 8 Precision FVR Band Gap Reference PORTC PORTE RC0/T1OSO/T13CKI RC1/T1OSI/CCP2 (1) RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT MCLR/VPP/RE3 (2) BOR HLVD Data EEPROM Timer0 Timer1 Timer2 Timer3 FVR CVREF Comparator ECCP1 CCP2 MSSP EUSART ADC 10-bit FVR Note 1: CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set, or RB3 when CCP2MX is not set. 2: RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 Oscillator Module (With Fail-Safe Clock Monitor) for additional information. DS41303G-page 14

15 FIGURE 1-2: PIC18F4XK20 (40/44-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 Address Latch Program Memory (8/16/32/64 Kbytes) Data Latch 20 8 PCLATU PCLATH PCU PCH PCL Program Counter 31-Level Stack Table Latch STKPTR Data Bus<8> 8 8 Data Latch Data Memory Address Latch 12 Data Address<12> BSR FSR0 Access Bank FSR1 FSR2 12 inc/dec logic PORTA PORTB RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT OSC2/CLKOUT (3) /RA6 OSC1/CLKIN (3) /RA7 RB0/INT0/FLT0/AN12 RB1/INT1/AN10/C12IN3- RB2/INT2/AN8 RB3/AN9/CCP2 (1) /C12IN2- RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD OSC1 (3) OSC2 (3) T1OSI T1OSO MCLR (2) VDD, VSS Instruction Bus <16> Internal Oscillator Block ROM Latch IR Instruction Decode and Control LFINTOSC Oscillator 16 MHz Oscillator Single-Supply Programming In-Circuit Debugger State machine control signals Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Fail-Safe Clock Monitor Address Decode 8 PRODH PRODL 8 x 8 Multiply 3 8 BITOP W ALU<8> 8 Precision FVR Band Gap Reference PORTC PORTD PORTE RC0/T1OSO/T13CKI RC1/T1OSI/CCP2 (1) RC2/CCP1/P1A RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 MCLR/VPP/RE3 (2) BOR HLVD Data EEPROM Timer0 Timer1 Timer2 Timer3 FVR CVREF Comparator ECCP1 CCP2 MSSP EUSART ADC 10-bit FVR PSP Note 1: CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set, or RB3 when CCP2MX is not set. 2: RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 Oscillator Module (With Fail-Safe Clock Monitor) for additional information. DS41303G-page 15

16 TABLE 1-2: Pin Name MCLR/VPP/RE3 MCLR VPP RE3 OSC1/CLKIN/RA7 OSC1 CLKIN RA7 OSC2/CLKOUT/RA6 OSC2 CLKOUT PIC18F2XK20 PINOUT I/O DESCRIPTIONS Pin Number PDIP, SOIC QFN RA6 Legend: TTL = TTL compatible input Pin Type I P I I I I/O O O I/O Buffer Type ST ST ST CMOS TTL TTL ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Description Master Clear (input) or programming voltage (input) Active-low Master Clear (device Reset) input Programming voltage input Digital input Oscillator crystal or external clock input Oscillator crystal input or external clock source input ST buffer when configured in RC mode; CMOS otherwise External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKIN, OSC2/CLKOUT pins) General purpose I/O pin Oscillator crystal or clock output Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate General purpose I/O pin CMOS = CMOS compatible input or output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. DS41303G-page 16

17 TABLE 1-2: Pin Name RA0/AN0/C12IN0- RA0 AN0 C12IN0- RA1/AN1/C12IN1- RA1 AN1 C12IN1- RA2/AN2/VREF-/CVREF/ C2IN+ RA2 AN2 VREF- CVREF C2IN+ RA3/AN3/VREF+/C1IN+ RA3 AN3 VREF+ C1IN+ RA4/T0CKI/C1OUT RA4 T0CKI C1OUT RA5/AN4/SS/HLVDIN/ C2OUT RA5 AN4 SS HLVDIN C2OUT RA6 RA7 PIC18F2XK20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP, SOIC QFN Pin Type I/O I I I/O I I I/O I I O I I/O I I I I/O I O I/O I I I O Buffer Type TTL Analog Analog TTL Analog Analog TTL Analog Analog Analog Analog TTL Analog Analog Analog ST ST CMOS TTL Analog TTL Analog CMOS PORTA is a bidirectional I/O port. Digital I/O Analog input 0, ADC channel 0 Comparators C1 and C2 inverting input Digital I/O ADC input 1, ADC channel 1 Comparators C1 and C2 inverting input Digital I/O Analog input 2, ADC channel 2 A/D reference voltage (low) input Comparator reference voltage output Comparator C2 non-inverting input Digital I/O Analog input 3, ADC channel 3 A/D reference voltage (high) input Comparator C1 non-inverting input Digital I/O Timer0 external clock input Comparator C1 output Description Digital I/O Analog input 4, ADC channel 4 SPI slave select input High/Low-Voltage Detect input Comparator C2 output See the OSC2/CLKOUT/RA6 pin See the OSC1/CLKIN/RA7 pin Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. DS41303G-page 17

18 TABLE 1-2: Pin Name RB0/INT0/FLT0/AN12 RB0 INT0 FLT0 AN12 RB1/INT1/AN10/C12IN3- /P1C RB1 INT1 AN10 C12IN3- P1C RB2/INT2/AN8/P1B RB2 INT2 AN8 P1B RB3/AN9/C12IN2-/CCP2 RB3 AN9 C12IN2- CCP2 (2) RB4/KBI0/AN11/P1D RB4 KBI0 AN11 P1D RB5/KBI1/PGM RB5 KBI1 PGM RB6/KBI2/PGC RB6 KBI2 PGC RB7/KBI3/PGD RB7 KBI3 PGD PIC18F2XK20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP, SOIC QFN Pin Type I/O I I I I/O I I I O I/O I I O I/O I I I/O I/O I I O I/O I I/O I/O I I/O I/O I I/O Buffer Type TTL ST ST Analog TTL ST Analog Analog CMOS TTL ST Analog CMOS TTL Analog Analog ST TTL TTL Analog CMOS TTL TTL ST TTL TTL ST TTL TTL ST Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-up on each input. Digital I/O External interrupt 0 PWM Fault input for CCP1 Analog input 12, ADC channel 12 Digital I/O External interrupt 1 Analog input 10, ADC channel 10 Comparators C1 and C2 inverting input Enhanced CCP1 PWM output Digital I/O External interrupt 2 Analog input 8, ADC channel 8 Enhanced CCP1 PWM output Digital I/O Analog input 9, ADC channel 9 Comparators C1 and C2 inverting input Capture 2 input/compare 2 output/pwm 2 output Digital I/O Interrupt-on-change pin Analog input 11, ADC channel 11 Enhanced CCP1 PWM output Digital I/O Interrupt-on-change pin Low-Voltage ICSP Programming enable pin Digital I/O Interrupt-on-change pin In-Circuit Debugger and ICSP programming clock pin Digital I/O Interrupt-on-change pin In-Circuit Debugger and ICSP programming data pin Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. DS41303G-page 18

19 TABLE 1-2: Pin Name RC0/T1OSO/T13CKI RC0 T1OSO T13CKI RC1/T1OSI/CCP2 RC1 T1OSI CCP2 (1) RC2/CCP1/P1A RC2 CCP1 P1A RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO RC5 SDO RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT PIC18F2XK20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP, SOIC QFN Pin Type I/O O I I/O I I/O I/O I/O O I/O I/O I/O I/O I I/O I/O O I/O O I/O I/O I I/O Buffer Type ST ST ST Analog ST ST ST CMOS ST ST ST ST ST ST ST ST ST ST ST ST PORTC is a bidirectional I/O port. Digital I/O Timer1 oscillator output Timer1/Timer3 external clock input Digital I/O Timer1 oscillator input Capture 2 input/compare 2 output/pwm 2 output Digital I/O Capture 1 input/compare 1 output Enhanced CCP1 PWM output Digital I/O Synchronous serial clock input/output for SPI mode Synchronous serial clock input/output for I 2 C mode Digital I/O SPI data in I 2 C data I/O Digital I/O SPI data out Description Digital I/O EUSART asynchronous transmit EUSART synchronous clock (see related RX/DT) Digital I/O EUSART asynchronous receive EUSART synchronous data (see related TX/CK) RE3 See MCLR/VPP/RE3 pin VSS 8, 19 5, 16 P Ground reference for logic and I/O pins VDD P Positive supply for logic and I/O pins Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. DS41303G-page 19

20 TABLE 1-3: Pin Name MCLR/VPP/RE3 MCLR VPP RE3 OSC1/CLKIN/RA7 OSC1 CLKIN RA7 OSC2/CLKOUT/RA6 OSC2 CLKOUT PIC18F4XK20 PINOUT I/O DESCRIPTIONS Pin Number PDIP QFN TQFP RA6 Legend: TTL = TTL compatible input Pin Type I P I I I I/O O O I/O Buffer Type ST ST ST CMOS TTL TTL ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Description Master Clear (input) or programming voltage (input) Active-low Master Clear (device Reset) input Programming voltage input Digital input Oscillator crystal or external clock input Oscillator crystal input or external clock source input ST buffer when configured in RC mode; analog otherwise External clock source input. Always associated with pin function OSC1 (See related OSC1/CLKIN, OSC2/CLKOUT pins) General purpose I/O pin Oscillator crystal or clock output Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate General purpose I/O pin CMOS = CMOS compatible input or output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. DS41303G-page 20

21 TABLE 1-3: Pin Name RA0/AN0/C12IN0- RA0 AN0 C12IN0- RA1/AN1/C12IN0- RA1 AN1 C12IN0- RA2/AN2/VREF-/CVREF/ C2IN+ RA2 AN2 VREF- CVREF C2IN+ RA3/AN3/VREF+/ C1IN+ RA3 AN3 VREF+ C1IN+ RA4/T0CKI/C1OUT RA4 T0CKI C1OUT RA5/AN4/SS/HLVDIN/ C2OUT RA5 AN4 SS HLVDIN C2OUT RA6 RA7 PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP QFN TQFP Pin Type I/O I I I/O I I I/O I I O I I/O I I I I/O I O I/O I I I O Buffer Type TTL Analog Analog TTL Analog Analog TTL Analog Analog Analog Analog TTL Analog Analog Analog ST ST CMOS TTL Analog TTL Analog CMOS Description PORTA is a bidirectional I/O port. Digital I/O Analog input 0, ADC channel 0 Comparator C1 and C2 inverting input Digital I/O Analog input 1, ADC channel 1 Comparator C1 and C2 inverting input Digital I/O Analog input 2, ADC channel 2 A/D reference voltage (low) input Comparator reference voltage output Comparator C2 non-inverting input Digital I/O Analog input 3, ADC channel 3 A/D reference voltage (high) input Comparator C1 non-inverting input Digital I/O Timer0 external clock input Comparator C1 output Digital I/O Analog input 4, ADC channel 4 SPI slave select input High/Low-Voltage Detect input Comparator C2 output See the OSC2/CLKOUT/RA6 pin See the OSC1/CLKIN/RA7 pin Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. DS41303G-page 21

22 TABLE 1-3: Pin Name RB0/INT0/FLT0/AN12 RB0 INT0 FLT0 AN12 RB1/INT1/AN10/ C12IN3- RB1 INT1 AN10 C12IN3- RB2/INT2/AN8 RB2 INT2 AN8 RB3/AN9/C12IN2-/ CCP2 RB3 AN9 C12IN23- CCP2 (2) RB4/KBI0/AN11 RB4 KBI0 AN11 RB5/KBI1/PGM RB5 KBI1 PGM RB6/KBI2/PGC RB6 KBI2 PGC RB7/KBI3/PGD RB7 KBI3 PGD PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP QFN TQFP Pin Type I/O I I I I/O I I I I/O I I I/O I I I/O I/O I I I/O I I/O I/O I I/O I/O I I/O Buffer Type TTL ST ST Analog TTL ST Analog Analog TTL ST Analog TTL Analog Analog ST TTL TTL Analog TTL TTL ST TTL TTL ST TTL TTL ST Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-up on each input. Digital I/O External interrupt 0 PWM Fault input for Enhanced CCP1 Analog input 12, ADC channel 12 Digital I/O External interrupt 1 Analog input 10, ADC channel 10 Comparator C1 and C2 inverting input Digital I/O External interrupt 2 Analog input 8, ADC channel 8 Digital I/O Analog input 9, ADC channel 9 Comparator C1 and C2 inverting input Capture 2 input/compare 2 output/pwm 2 output Digital I/O Interrupt-on-change pin Analog input 11, ADC channel 11 Digital I/O Interrupt-on-change pin Low-Voltage ICSP Programming enable pin Digital I/O Interrupt-on-change pin In-Circuit Debugger and ICSP programming clock pin Digital I/O Interrupt-on-change pin In-Circuit Debugger and ICSP programming data pin Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. DS41303G-page 22

23 TABLE 1-3: Pin Name RC0/T1OSO/T13CKI RC0 T1OSO T13CKI RC1/T1OSI/CCP2 RC1 T1OSI CCP2 (1) RC2/CCP1/P1A RC2 CCP1 P1A RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO RC5 SDO RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP QFN TQFP Pin Type I/O O I I/O I I/O I/O I/O O I/O I/O I/O I/O I I/O I/O O I/O O I/O I/O I I/O Buffer Type ST ST ST CMOS ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST PORTC is a bidirectional I/O port. Digital I/O Timer1 oscillator output Timer1/Timer3 external clock input Digital I/O Timer1 oscillator input Capture 2 input/compare 2 output/pwm 2 output Digital I/O Capture 1 input/compare 1 output/pwm 1 output Enhanced CCP1 output Digital I/O Synchronous serial clock input/output for SPI mode Synchronous serial clock input/output for I 2 C mode Digital I/O SPI data in I 2 C data I/O Digital I/O SPI data out Description Digital I/O EUSART asynchronous transmit EUSART synchronous clock (see related RX/DT) Digital I/O EUSART asynchronous receive EUSART synchronous data (see related TX/CK) Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. DS41303G-page 23

24 TABLE 1-3: Pin Name RD0/PSP0 RD0 PSP0 RD1/PSP1 RD1 PSP1 RD2/PSP2 RD2 PSP2 RD3/PSP3 RD3 PSP3 RD4/PSP4 RD4 PSP4 RD5/PSP5/P1B RD5 PSP5 P1B RD6/PSP6/P1C RD6 PSP6 P1C RD7/PSP7/P1D RD7 PSP7 P1D PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP QFN TQFP Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O O I/O I/O O Buffer Type ST TTL ST TTL ST TTL ST TTL ST TTL ST TTL ST TTL ST TTL PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled. Digital I/O Parallel Slave Port data Digital I/O Parallel Slave Port data Digital I/O Parallel Slave Port data Digital I/O Parallel Slave Port data Digital I/O Parallel Slave Port data Digital I/O Parallel Slave Port data Enhanced CCP1 output Digital I/O Parallel Slave Port data Enhanced CCP1 output Digital I/O Parallel Slave Port data Enhanced CCP1 output Description Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. DS41303G-page 24

25 TABLE 1-3: Pin Name RE0/RD/AN5 RE0 RD AN5 RE1/WR/AN6 RE1 WR AN6 RE2/CS/AN7 RE2 CS PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP QFN TQFP Pin Type I/O I I I/O I I ST TTL Analog ST TTL Analog PORTE is a bidirectional I/O port Digital I/O Read control for Parallel Slave Port (see related WR and CS pins) Analog input 5, ADC channel 5 Digital I/O Write control for Parallel Slave Port (see related CS and RD pins) Analog input 6, ADC channel 6 AN7 I Analog RE3 See MCLR/VPP/RE3 pin I/O I Buffer Type ST TTL Description Digital I/O Chip Select control for Parallel Slave Port (see related RD and WR) Analog input 7, ADC channel 7 VSS 12, 31 6, 30, 6, 29 P Ground reference for logic and I/O pins 31 VDD 11, 32 7, 8, 7, 28 P Positive supply for logic and I/O pins 28, 29 NC 13 12, 13, 33, 34 No connect Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. DS41303G-page 25

26 NOTES: DS41303G-page 26

27 2.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 2.1 Overview The Oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 2-1 illustrates a block diagram of the Oscillator module. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of two internal oscillators, with a choice of speeds selectable via software. Additional clock features include: Selectable system clock source between external or internal via software. Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator. The Oscillator module can be configured in one of ten primary clock modes. 1. LP Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. HSPLL High-Speed Crystal/Resonator with PLL enabled 5. RC External Resistor/Capacitor with FOSC/4 output on RA6 6. RCIO External Resistor/Capacitor with I/O on RA6 7. INTOSC Internal Oscillator with FOSC/4 output on RA6 and I/O on RA7 8. INTOSCIO Internal Oscillator with I/O on RA6 and RA7 9. EC External Clock with FOSC/4 output 10. ECIO External Clock with I/O on RA6 Primary Clock modes are selected by the FOSC<3:0> bits of the CONFIG1H Configuration Register. The HFINTOSC and LFINTOSC are factory calibrated highfrequency and low-frequency oscillators, respectively, which are used as the internal clock sources. FIGURE 2-1: PIC MCU CLOCK SOURCE BLOCK DIAGRAM OSC2 OSC1 T1OSO T1OSI Primary Oscillator Sleep Secondary Oscillator T1OSCEN Enable Oscillator FOSC<3:0> OSCCON<1:0> Internal Oscillator Block 16 MHz Source 31 khz Source OSCTUNE<6> (1) 16 MHz (HFINTOSC) 31 khz (LFINTOSC) PIC18F2XK20/4XK20 Postscaler 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 khz 250 khz 1 31 khz 0 4 x PLL OSCCON<6:4> MUX LP, XT, HS, RC, EC HSPLL, HFINTOSC/PLL T1OSC Internal Oscillator MUX FOSC<3:0> Clock Control IDLEN Sleep Main Sleep OSCCON<1:0> Clock Source Option for other Modules Peripherals CPU OSCTUNE<7> WDT, PWRT, FSCM and Two-Speed Start-up Note 1: Operates only when HFINTOSC is the primary oscillator. DS41303G-page 27

28 2.2 Oscillator Control The OSCCON register (Register 2-1) controls several aspects of the device clock s operation, both in full power operation and in power-managed modes. Main System Clock Selection (SCS) Internal Frequency selection bits (IRCF) Clock Status bits (OSTS, IOFS) Power management selection (IDLEN) MAIN SYSTEM CLOCK SELECTION The System Clock Select bits, SCS<1:0>, select the main clock source. The available clock sources are Primary clock defined by the FOSC<3:0> bits of CONFIG1H. The primary clock can be the primary oscillator, an external clock, or the internal oscillator block. Secondary clock (Timer1 oscillator) Internal oscillator block (HFINTOSC and LFINTOSC). The clock source changes immediately after one or more of the bits is written to, following a brief clock transition interval. The SCS bits are cleared to select the primary clock on all forms of Reset INTERNAL FREQUENCY SELECTION The Internal Oscillator Frequency Select bits (IRCF<2:0>) select the frequency output of the internal oscillator block. The choices are the LFINTOSC source (31 khz), the HFINTOSC source (16 MHz) or one of the frequencies derived from the HFINTOSC postscaler (31.25 khz to 8 MHz). If the internal oscillator block is supplying the main clock, changing the states of these bits will have an immediate change on the internal oscillator s output. On device Resets, the output frequency of the internal oscillator is set to the default frequency of 1 MHz LOW FREQUENCY SELECTION When a nominal output frequency of 31 khz is selected (IRCF<2:0> = 000), users may choose which internal oscillator acts as the source. This is done with the INTSRC bit of the OSCTUNE register. Setting this bit selects the HFINTOSC as a khz clock source by enabling the divide-by-512 output of the HFINTOSC postscaler. Clearing INTSRC selects LFINTOSC (nominally 31 khz) as the clock source. This option allows users to select the tunable and more precise HFINTOSC as a clock source, while maintaining power savings with a very low clock speed. Regardless of the setting of INTSRC, LFINTOSC always remains the clock source for features such as the Watchdog Timer and the Fail-Safe Clock Monitor CLOCK STATUS The OSTS and IOFS bits of the OSCCON register, and the T1RUN bit of the T1CON register, indicate which clock source is currently providing the main clock. The OSTS bit indicates that the Oscillator Start-up Timer has timed out and the primary clock is providing the device clock. The IOFS bit indicates when the internal oscillator block has stabilized and is providing the device clock in HFINTOSC Clock modes. The IOFS and OSTS Status bits will both be set when SCS<1:0> = 00 and HFINTOSC is the primary clock. The T1RUN bit indicates when the Timer1 oscillator is providing the device clock in secondary clock modes. When SCS<1:0> 00, only one of these three bits will be set at any time. If none of these bits are set, the LFINTOSC is providing the clock or the HFINTOSC has just started and is not yet stable POWER MANAGEMENT The IDLEN bit of the OSCCON register determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed. The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 3.0 Power-Managed Modes. Note 1: The Timer1 oscillator must be enabled to select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit of the T1CON register. If the Timer1 oscillator is not enabled, then the main oscillator will continue to run from the previously selected source. The source will then switch to the secondary oscillator after the T1OSCEN bit is set. 2: It is recommended that the Timer1 oscillator be operating and stable before selecting the secondary clock source or a very long delay may occur while the Timer1 oscillator starts. DS41303G-page 28