FFT, REALIZATION AND IMPLEMENTATION IN FPGA. Griffith University/Ericsson Microwave System AB 2000/2001. Magnus Nilsson


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1 EMWMS (Magus ilsso) EMW/FX/DC (Aders Waer) 1(5) FFT, REALIZATIO AD IMPLEMETATIO I FPGA Griffith Uiversity/Ericsso Microwave System AB /1 by Magus ilsso 1 cos(*pi*4.5/16*t)+i*si(*pi*4.5/16*t) Supervisor, EMW: Rue Olsso Supervisor, GU: Prof. Kuldip K. Paliwal Sigal Processig Laboratory, School of Microelectroic Egieerig, Griffith Uiversity Brisbae/Gotheburg /1 /proj/fmd/fft/report.fm
2 (5) Abstract Ericsso Microwave Systems develops radar systems for military ad civilia applicatios. I military eviromets high radar resolutio ad log rage are desired, thus high demads must be met by the geerated ad trasmitted radar sigal. I this report the desig of a parallel Radix4 Fast Fourier Trasform algorithm is described. A theoretical review regardig Fourier theory ad Fast Fourier Trasform (Radix ad Radix4) is doe. A complex parallel Radix4 algorithm is simulated, implemeted ad realized i hardware usig VHDL ad a Xilix VirtexE 1 FPGA circuit. The VHDL code was simulated ad sythesized i Ease ad Syplify eviromet. The desig was verified ad the output was idetical with the Matlab ad VHDL simulatios, provig speed improvemets due to a parallel approach.
3 3(5) Preface This thesis is a part of my educatio towards a Master degree i Computer ad Iformatio Egieerig at Griffith Uiversity, Brisbae, Australia. Project 1, ad 3. MEE797,MEE798 ad MEE799. The work has bee doe at Ericsso Microwave System AB i Möldal Swede, at the departmet FX/D I would like to thak the followig people who has bee of great help to me durig my work. My supervisor Rue Olsso, EMW. My maager Håka Olsso/Aders Waer, EMW. Prof. Kuldip K. Paliwal, supervisor GU. Daiel Wallström, EMW, for help with VHDL. Deis Eriksso, EMW, for help with Logical Aalyser/Patter geerator. ils Dagås ad Gabriel Gitye, EMW, for help with Matlab. I would also like to thak the remaiig staff at EMW/FX ad GU who have bee helpful to me.
4 4(5) Cotets Page 1 Itroductio Backgroud Task Techical fuctio JeaBaptisteJoseph Fourier The Fourier Trasform The Discrete Fourier Trasform Developmet of the Fast Fourier Trasform Theory of the Fast Fourier Trasform History of the Fast Fourier Trasform The Radix  Algorithm Fig.1. : FFTButterfly Fig.. : Radix DFT structure Fig.3. : Radix vs. Direct calculatio i flops Fig.4. : Radix algorithm comp. with MATLAB fuctio FFT. 4 7 The Radix4 Algorithm Fig.5. : Radix4 Butterfly, also referred to as Dragofly Fig.6. : Radix4 FFT algorithm compared with Matlab FFT Implemetatio ad Realizatio i hardware FPGA Fig.7. : CLB, Cofigurable logic block. Courtesy of Xilix Ic Complex FFT Fig.8. : Costructio cofiguratio Bitlegth Fig.9. : Radix4 FFT, 1bit legth of samples Fig.1. : Radix4 FFT, 14bit legth of samples Fig.11. : Radix4 FFT, 16bit legth of samples Radix4 FFT algorithm, = Fig.1. : Radix4 FFT, = Fig.13. : First FFT costructio vs. Matlab FFT Fig.14. : Timig diagram for Radix4 FFT, shared multiplier Radix4 FFT algorithm, = Fig.15. : Iput sigal X1 ad X Fig.16. : Iput sigal X3 ad X Fig.17. : Radix4 = Fig.18. : Timig diagram for Radix4 FFT legth 16, 16 bits.. 39 Fig.19. : Absolute value block
5 5(5) 9 Verificatio ad Results Test patter Matlab verificatio Fig.. : Output graph sigal X1, absolute = Fig.1. : Output graph sigal X, absolute = Fig.. : Output graph sigal X3, absolute = Fig.3. : Output graph sigal X4, absolute = Fig.4. : Output complex ad absolute, sigal 1 vs. Matlab...44 Fig.5. : Output complex ad absolute, sigal vs. Matlab...44 Fig.6. : Output complex ad absolute, sigal 3 vs. Matlab...45 Fig.7. : Output complex ad absolute, sigal 4 vs. Matlab Coclusio Ideas for further studies Refereces Appedix A Ease block structure of Radix4 FFT, = 64 AppedixA... Ease block structure of Radix4 FFT, = 64, shared mult Appedix A Ease block structure of Radix4 FFT, = 16 Appedix B Matlab code Appedix C Output listig
6 6(5) 1 ITRODUCTIO 1.1 BACKGROUD To implemet the DFT (FFT) i hardware (real time system) required expesive solutio ofte with ASIC (Applicatio Specific Itegrated Circuit). With the latest geeratio of FPGA (Field Programmable Gate Arrays) it is possible to implemet very large amouts of logic i a sigle itegrated circuit. A maufacturer of FPGA amed XILIX ow has a dropi module for their FPGAs which ca execute a 14poits FFT. It is iterestig to evaluate ad develop such a DFT or similar. 1. TASK To study, implemet ad evaluate the DFT (Discrete Fourier Trasform) i FPGA or similar. 1.3 TECHICAL FUCTIO The DFT shall collect data, execute a DFT or IDFT ad output the data. The implemetatio shall be optimized o executio time, size (area) ad cost.
7 7(5) JEABAPTISTEJOSEPH FOURIER The 1:st of March 1768, JeaBaptisteJoseph Fourier was bor. He was bor i poor circumstaces i the small village of Auxerre, Frace. JeaBaptisteJoseph Fourier itroduced the idea that a arbitrary fuctio, eve a fuctio defied by differet aalytic expressios i adjacet segmets of its rage (such as a staircase waveform) could evertheless be represeted by a sigle aalytic expressio. Fourier s ideas ecoutered resistace at the time but has prove to be a cetral theorem to may of the later developmets i mathematics, sciece ad also egieerig. As we all kow, it is at the heart of the electrical curriculum today. Fourier came across the idea i the coectio with the problem of flow of heat i solid bodies, icludig the heat from the earth. We have leared that Fourier was obsessed with heat, keepig his room really hot, ucomfortably hot for visitors, this whe eve wearig a heavy coat himself. Some has traced this obsessio back to Egypt where he wet 1798 with apoleo o a expeditio to civilize the coutry. By this time Fourier worked with his theories parallel to his official duties as a secretary of the Istitut d Egypte. At the time i Egypt, Fourier came i cotact with the Eglish Physisist Thomas Youg ( ), father of liearity, with whom he discussed his ideas ad worked together o, amog other thigs, the Rosetta Stoe. After returig back to Paris, Fourier had by 187, despite official duties, completed his theory of heat coductio, which depeded o the essetial idea of aalysig the temperature distributio ito spatially siusoidal compoets. He was very criticized for his theory amog the frech scietists, amog them where Biot ad Poisso. Eve though he was criticized for his theory he received a mathematic prize i 1811 for his heat theory. The publicatio of his writig report "Théorie aalytique de la chaleur" (The aalytical theory of heat) i 1815 was also met with some criticism ad this might be see as a idicatio of the deep ueasiess about Fourier aalysis that was felt by the great mathematicias of that day. JeaBaptisteJoseph Fourier died i Paris the 16:th of May 183. He ever got married.
8 8(5) 3 THE FOURIER TRASFORM Oe of todays pricipal aalysis tool i may of todays scietific challeges is the Fourier Trasform. Maybe the most kow applicatio of this mathematical techique is the aalysis of liear timeivariat system. As this might be the most well kow applicatio, the Fourier Trasform is essetially a uiversal problem solvig techique. Its importace is based o the fudametal property that oe ca examie a particular relatioship from a etirely differet viewpoit. Simultaeous visualizatio of a fuctio ad its Fourier Trasform is ofte the key to successful problem solvig. If we defie a sigal: lim yt () = t ± (EQ 1) 7 Trasiet sigal A trasiet sigals spectrum is characterised by the fact that it is cotiuous, this meas that it holds ifiite umbers of frequecy compoets, although usually they are i a fiite iterval.
9 9(5) Mathematically oe ca defie a sigal, that vary periodically with time, to be a sum of discrete frequecy compoets, where a simple relatioship exists betwee the frequecy compoets. This ca be defied as a formula: yt () = A { cos( ω t) + B si( ω t) } = 1 (EQ ) where ω = π T T = Periodicaltime If we look back o our trasiet sigal above, the mathematical cosequece will be that the coefficiets will be cotiues fuctios of the phase w. Equatio 3 becomes: yt () = A( ω) cos( ωt) + B( ω) si( ωt) (EQ 3)
10 1(5) If we compare this equatio with equatio we will see that the costat A / has disappeared, this though A / represets the time mea value of the sigal ad though it is a trasiet, the time mea value is zero. The Fourier coefficiets A(w) ad B(w) is defied by the Fourier itegrals: A( ω) = yt () cosωtdt (EQ 4) B( ω) = yt () siωtdt where (EQ 5) ω > Whe oe wats to calculate the Fourier coefficiets i the geeral case for the sigal f(t), oe should facilitate the calculatios by itroduce complex otatio.the startig poit for complex otatio of the Fourier Trasform is based o the formulas by Euler which gives a relatio betwee the complex umber j ad the trigoometrical fuctios sie ad cosie: cosα = e jα e jα (EQ 6) siα = e jα e jα j (EQ 7)
11 11(5) The equatios, 6 ad 7 will give us: yt () A( ω) e jωt + e jωt B( ω) e jωt e jωt = dω j yt () A e jωt + e jωt jb e jωt e jωt = dω yt () = 1  ( A jb)e jωt ( A+ jb)e j ωt dω (EQ 8) If we defie Y(w): Y ( ω) = 1  ( A( ω) jb( ω) ) Y ( ω) = 1  ( A( ω) + jb( ω) ) Equatio 9a ad 9b (EQ 9) The the equatio 8 ca be simplified by makig the itegratio over the real area: yt () = Y ( ω)e jωt (EQ 1)
12 1(5) This will the give us, by lookig at equatio 4 ad 5: Y ( ω) = yt () cosωtdt j y() t siωtdt Y ( ω) = yt ()( cosωt jsiωt) dt Y ( ω) = yt ()e jωt (EQ 11) We will the defie Y(w) as the Fourier Trasform of y(t) ad equatio 1 as the Iverse Fourier Trasform.
13 13(5) 4 THE DISCRETE FOURIER TRASFORM Whe samplig a arbitrary aalog sigal the sampled sigal ca be expressed as: yt () = y( )δ( ) + yt ( S )δ( t T S ) + y( T S )δ( t T S ) + + y( ( 1)T S )δ( t ( 1)T S ) Where (EQ 1) f T max S Accordig to the yquist theorem. The fuctio described above is a sum of time delayed delta fuctios, each of them with the height y(t S ). The Fourier Trasform for all of those fuctios equals the Fourier Trasform for the udelayed fuctio ie. F{ y( T S )δ( ) } = yt ( S )F{ δ( ) } multiplied with respectively time delay factor: Y ( ω) y( ) yt ( S )e jωt S = y( ( 1)T S )e jω 1 ( )T S 1 Y ( ω) yt ( S )e jωt S = = (EQ 13) Sice f = w/pi is a discrete variable whe we deal with a sampled sigal ad oly adopt the discrete values:
14 14(5) 1, , T , s T, s T s = k T s (EQ 14) Where k =,1,,...,1 Equatio 13 becomes: 1 j t πk S Y πk T = yt ( T s S )e s = = 1 = yt ( S ) e j π k (EQ 15) Oce agai k =,1,,...,1 If we simplify the equatio: W = e j π (EQ 16) We will get the fial expressio for the Fourier Trasform: 1 k Y( k) = y ( )W = (EQ 17) k =,1,,...,1 The factor W is called the Twiddle Factor.
15 15(5) 5 DEVELOPMET OF THE FAST FOURIER TRASFORM 5.1 THEORY OF THE FAST FOURIER TRASFORM If we cosider the equatio 17: 1 k Y( k) = y ( )W = k = 1,,,, 1 ad we cosider the amout of additios ad multiplicatios eeded for computig the algorithm. For istace, let us cosider the case whe = 4 Y ( ) = y W + y 1 W + y W + y 3 W Y ( 1) = y W + y 1 W 1 + y W + y 3 W 3 Y ( ) = y W + y 1 W + y W 4 + y 3 W 6 Y ( 3) = y W + y 1 W 3 + y W 6 + y 3 W 9 Or simplified i the compact form: Y( ) = W k yk ( ) (EQ 18) If we the cosider the twiddle factor ad y(k) we will i the worst case have two complex umbers. This fact will give us complex multiplicatios ad ()(1) complex additios. Suppose that we have a microprocessor that ca do a additio or a multiplicatio i 1 micro secod ad that this processor should compute a DFT o a 1 kbyte set of samples. If we have complex multiplicatios ad ()(1) complex additios ~ additios ad multiplicatios: x 14 x 1 micro secod =,1 secod. This without takig ito cosideratio the fact that the processor has to update poiters a so o. If we wat the aalyse to be made i real time we will have to have a distace betwee the samples that exceeds,1 secod:
16 16(5) =.5ms 14 Which gives us: = 488Hz.5 as the maximum samplig frequecy. By takig the yquist theorem i respect, we ca ot sample a sigal that holds a frequecy compoet that exceeds half the maximum samplig frequecy = 488Hz/ = 44Hz. There are two obvious ways to improve ad icrease the badwidth; a faster processor or optimizig the algorithm. 5. HISTORY OF THE FAST FOURIER TRASFORM I the begiig of the 196 s, durig a meetig of the Presidet s Scietific Advisory Commitee, Richard L. Garwi foud out that Joh W. Tukey was writig about the Fourier Trasform. Garwi was i his ow research i a desperate eed for a fast way to compute the Fourier Trasform. Whe questioed, Tukey outlied to Garwi essetially what has led to the famous CooleyTukey algorithm. To get some programmig techique, Tukey wet to IBM Research i Yorktow Heights ad meet there James W Cooley, who quickly worked out a computer program for this algorithm. After a while, request for copies ad a writeup bega accumulatig, ad also Cooley was asked to write a paper o the algorithm which i 1965 became the famous paper "A algorithm for the machie calculatio of complex Fourier series", that he published together with Tukey. Whe publishig this paper, reports of other people usig the same techique became kow, but the origial idea usually ascribe to Ruge ad Köig. The Cooley  Tukey algorithm is also called the Radix  algorithm, due to its sigal splittig.
17 17(5) 6 THE RADIX  ALGORITHM Oce agai cosider equatio 17: 1 k Y( k) = y ( )W = k = 1,,,, 1 ad we wat to aalyse the samples: { y ( )} = { y( ), y( 1), y( ),, y ( 1) } If we cosider the possibility to split the samples ito odd ad eve samples: { y( ) } = { y( ), y( ), y( 4), y ( ) } { y( + 1) } = { y( 1), y( 3), y( 5),, y ( 1) } Doig the DFT for those two sequeces will give: k Y( k) = y( )W + = = + 1 y( + 1)W ( )k (EQ 19) By extractig ad simplifyig the twiddle factor we are able to simplify eve further: k Y( k) = y( )W + = W k = k y( + 1)W (EQ )
18 18(5) W = e = e = e = j π j π j π W k Y( k) = y( )W + = W k = k y( + 1)W (EQ 1) (EQ ) By comparig this equatio with equatio 17 we will fid that this by defiitio are two DFT s with legth /. k Y( k) = Dk ( ) + W Ek ( ) k = 1,,,, 1 (EQ 3) Where D ad E represets the sums from equatio. The computatio gai by doig this will be: (as the multiplicatios i a ordiary DFT = ) = = This umber should be adjusted a bit though the twiddle factor should be multiplied with the odd sum, but this is of a first order of. If we study equatio 3, we will fid that k goes from to 1 but that D ad E represets DFT of /. Geerally for a DFT of legth is that it is periodical i k with. This leads to that D ad E i equatio 3 is periodical with /.
19 19(5) D k = Dk ( ) (EQ 4) E k = Ek ( ) (EQ 5) Calculatig the DFT: Y ( ) = D( ) + W 1 Y ( 1) = D( 1) + W Y ( ) = D( ) + W Y D = + W E( ) E( 1) E( ) E Y  D W E = = D( ) + W E( ) Y D W E = = D( 1) + W Y( 1) D ( 1) + W E( 1) D W = = + 1 E( 1) E (EQ 6) By symmetrically, the twiddle factor ca be expressed as:
20 (5) W k = W k (EQ 7) Which gives us: Y ( ) = D( ) + W 1 Y ( 1) = D( 1) + W Y D = + W E( ) E( 1) E Y  D ( = ) W E( ) Y D ( 1 1 = ) W Y( 1) = D W E( 1) E (EQ 8) By lookig ito equatio 8 we will fid oe elemetary buildigblock, the so called FFTButterfly. D(k) E(k) W K W K Y(k) Y(k+/) Fig.1. FFTButterfly
21 1(5) Which gives the equatios: k Y( k) = Dk ( ) + W Ek ( ) (EQ 9) Y( k) = Dk ( ) W k Ek ( ) (EQ 3) Sice dividig the sequeces ito smaller buildig blocks reduce the amout of multiplicatios, we will cotiue to divide the sequeces ito ew blocks. If we start with equatio ad divide the sum ito four ew sums: k Y( k) = y( 4)W + W k W k = = = k y( 4 + 1)W k y( 4)W = + k W k y( 4 + 1)W = = = y( 4 + )W y( 4 + 3)W k W ( + 1)k + ( + 1)k k + y( 4 + )W = = k y( 4 + 3)W (EQ 31)
22 (5) Ad sice W = W k Y( k) = y( 4)W 4 + W k = = k y( 4 + 1)W 4 k W + k W = = k y( 4 + )W 4 k + y( 4 + 3)W 4 (EQ 3) Ad by usig equatio 1 backwards k W = W k k Y( k) = y( 4)W 4 + W k = = k y( 4 + 1)W 4 W k + W k = = k y( 4 + )W 4 k + y( 4 + 3)W 4 (EQ 33) Ad if we cotiue to divide ito smaller sums util we oly have / poits DFT s we will get the structure described below, the costrai though is that the legth should be a power of two. The example below shows the structure for = 8.
23 3(5) x() Stage 1 Stage Stage 3 X() x(1) 1 X(1) x() W 81 X() x(3) 1 W 81 X(3) x(4) W 81 X(4) x(5) 1 W X(5) x(6) W 81 W 81 X(6) x(7) 1 W 81 W X(7) Fig.. Radix DFT structure Whe computig a DFT usig a Radix algorithm for the case whe = x the decimatio ito smaller sums ca be doe x=log times, ad this will give a total umber of complex multiplicatios = (/)log ad log complex additios. The gai whe comparig with a direct calculatio is eormous as show i the figure below: x 1 7 Radix vs. Direct Calculatio i flops 4.5 Radix Direct Calculatio umber of flops Fig.3. Radix vs. Direct calculatio i flops
24 4(5) Part of radix Matlab algorithm. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Iitialize variables. t = 1:1:14; x = si(*pi*.35*t)+si(*pi*.5*t); = legth(x); b = bidec(fliplr(decbi(:1:legth(x)1)))+1; MC = x(b); % Make i bit reversed order alfa = /; beta = 1; %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Calculate Twiddle factor for = 1:/ W() = exp(j**pi*(1)/); W_r() = cos(*pi*(1)/); W_i() = si(*pi*(1)/); ed %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Calculate FFT usig iplace orecursive DIT FFT, radix for h = 1:(log()/log()) b = ^(h1); a = 1; ao = 1; for d = 1:alfa c = 1; for e = 1:beta a+b; temp1 = W(c)*MC(a+b); temp = MC(a); MC(a) = MC(a) + temp1; MC(a+b) = temp  temp1; a = a + 1; c = c + alfa; ed a = ao + ^(h); ao = a; ed alfa = alfa/; beta = beta*; ed 6 5 y(x) = si(*pi*.35*t)+si(*pi*.5*t) Radix FFT algorithm y(x) = si(*pi*.35*t)+si(*pi*.5*t) MATLAB FFT algorithm Fig.4. Radix algorithm comp. with MATLAB fuctio FFT
25 5(5) 7 THE RADIX4 ALGORITHM By developig the Radix algorithm eve further ad usig the base 4 istead we will get the a more complex algorithm but with less computatio power. As we will uderstad, we will get the ew costrai where the umber of data poits i the DFT has to be the power of 4 (i.e.=4 x ). By doig i the same way as we did with the Radix algorithm we divide the data sequece ito four subsequece { y( 4) } = { y( ), y( 4), y( 8),, y ( 4) } { y( 4 + 1) } = { y( 1), y( 5), y( 9),, y ( 3) } { y( 4 + ) } = { y( ), y( 6), y( 1),, y ( ) } { y( 4 + 3) } = { y( 3), y( 7), y( 11),, y ( 1) } By usig the approach described i [8] ad by applyig: 3 lq lp X( p, q) = [ W Flq (, )]W 4 l = p = 13,,, where F(l,q) is give by: mq Flq (, ) = xlm (, )W m = l = 13,,, q = 1,,,, (EQ 34) Ad where: xlm (, ) = x( 4m+ l) X( p, q) = X p + q (EQ 35) (EQ 36)
26 6(5) Ad the four /4poit DFT s obtaied from equatio 35 are combied accordig to equatio 34 ad ca be combied to yield the poit DFT, as described i [8]: X(, q) X( 1, q) X(, q) X( 3, q) = j 1 j j 1 j W F(, q) q W F( 1, q) q W F(, q) 3q W F( 3, q) (EQ 37) We also have to ote that W = 1, which will give us three complex multiplicatios ad 1 complex additios per Radix4 butterfly. As the Radix 4 algorithm cosists of v steps (log()/log(4)) where each step ivolves /4 umber of butterflies we will get 3*v*/4 = (3/8)log umber of complex multiplicatios ad (3/)log complex additios. If compared with the computatioal power used by the Radix algorithm i chapter 5, we will fid that we have a computer gai of 5% regardig the complex multiplicatios, but that the umber of complex additios icreases by 5%. The matrix i equatio 37 is better described with a Radix4 butterfly: W i x A W q i1 x j 1 j B i W q x 11 C i3 W 3q x j 1 j D Fig.5. Radix4 Butterfly, also referred to as Dragofly
27 7(5) As we are iterested i a complex FFT we eed to derive the equatios for the complex radix4 algorithm. a = i 1 b = i1 W q c = i W q d = i3 W 3q A = a+ b + c + d B = a c jb ( d) C = a + c ( b + d) D = a c+ jb ( d) Which i the complex matter will give us, startig with the easiest oes: (r =real, i = imag) Ar = ar + br + cr + dr Ai = ai + bi + ci + di Cr = ar br + cr dr Ci = ai bi + ci di (EQ 38) Ad cotiuig with B gives: B = ar + ai cr ci jbr jbi + jdr + jdi B = ar + ai cr ci jbr + bi + jdr di (EQ 39) imag real (EQ 4) Divided ito real ad imagiary part: Br = ar cr + bi di Bi = ai ci br + dr (EQ 41)
28 8(5) Ad the last oe gives: D = ar + ai cr ci + jbr + jbi jdr jdi D = ar + ai cr ci + jbr bi jdr + di imag real (EQ 4) Divided ito real ad imagiary part: Dr = ar cr bi + di Di = ai ci + br dr (EQ 43) To get the iputs ar, ai, br, bi, cr, ci, dr ad di, we will have to multiply the iput ir, ii ad so o with the twiddle factor. This reder i: br = i1r cos( x) + i1i si( x) bi = i1i cos( x) i1r si( x) This is adequate for all iput sigals. X = dragofly specific value (twiddle factor) (EQ 44) As the goal of this project is to implemet a very fast fourier trasform i a realtime programmable logic system, we wat as few complex multiplicatios as possible, which yields lots of logic. With this i thoughts, to choose the Radix4 algorithm for implemetatio was obvious, as it has less complex multiplicatios tha the Radix algorithm.
29 9(5) Part of radix4 Matlab algorithm %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Iitialize variables. t = 1:1:56; x = si(*pi*.35*t)+si(*pi*.38*t); x1 = x; = legth(x); t = log()/log(4); %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Radix4 Algorithm for q = 1:t L = 4^q; r = /L; Lx = L/4; rx = 4*r; y = x; for j = :Lx1 for k = :r1 a = y(j*rx + k + 1); b = exp(i**pi*j/l)*y(j*rx + r + k + 1); c = exp(i**pi**j/l)*y(j*rx + *r + k + 1); d = exp(i**pi*3*j/l)*y(j*rx + 3*r + k + 1); t = a + c; t1 = a  c; t = b + d; t3 = b  d; x(j*r + k + 1) = t + t; x((j + Lx)*r + k + 1) = t1  i*t3; x((j + *Lx)*r + k + 1) = t  t; x((j + 3*Lx)*r + k + 1) = t1 + i*t3; ed ed ed 1 Radix 4 FFT algorithm Matlab FFT algorithm Fig.6. Radix4 FFT algorithm compared with Matlab FFT
30 3(5) 8 IMPLEMETATIO AD REALIZATIO I HARDWARE Classical implemetatio of the FFT algorithm, with a processor or i hardware usually requires a sequetial algorithm, i some cases recursive, this due to space ad memory requiremets. This slows dow the executio time. By utilizig moder programmable circuits, like a FPGA, a parallel approach to the realizatio of FFT is available. 8.1 FPGA The realtime FFT costructio was meat to be realized i a FPGA, a field programmable gate array, costructed ad maufactured by Xilix, Ic. The Xilix FPGA model VirtexE is a state of the art programmable gate array for high speed, high complex logical costructio. There is a great field of models, from small to large circuits. The logic iside a FPGA is costructed aroud a buildig block called CLB, Cofigurable logic block. Fig.7. CLB, Cofigurable logic block. Courtesy of Xilix Ic. Each of these blocks are divided ito two slices, where each slice cosists of two lookup tables ad some storage elemets. The slices are iterally coected i betwee ad are the basic highspeed logic i the circuit. Available for implemetatio of this project was a PCB with a Xilix VirtexE 1 mouted. This circuit holds a CLB array of 64 x 96 = 6144 CLB blocks. For more iformatio about Xilix VirtexE, refer to Xilix VertexE data book [13].
31 31(5) 8. COMPLEX FFT The Ericsso Microwave specificatio for the project was to simulate, realize ad implemet a complex FFT i a FPGA, a Xilix VirtexE 1. The specificatios for the FFT was: FFTlegth Miimum: 16 complex samples Maximum: 14 complex samples Typical: 64 or 56 (16) umber of bits for the iput sigal Miimum: 1 bits Maximum: 16 bits Typical: 1 The idea was to implemet the FFT as a buildigblock i a costructio, where the FFTblock will be placed after a quadrature divided A/D coverted sigal as described i the figure below: FPGA, Xilix VirtexE 1 f(x) A/D x() I/Q I Q FFT I Q Fig.8. Costructio cofiguratio
32 3(5) 8.3 BITLEGTH The first thig to cosider whe implemetig somethig discrete i hardware is to cosider the bit legth with which you wat to represet your sample. The best way to do this is to simulate differet types of bit legths ad compare the phase error ad amplitude error factor with the costrais for your costructio. 4 Radix 4 FFT, Bits = 1 si(*pi*f1*p/fs) 4 MATLAB FFT si(*pi*f1*p/fs) db db Amplitude error factor Radix 4 FFT/MATLAB FFT Phase error 15 db 1 Phase error Fig.9. Radix4 FFT, 1bit legth of samples 4 Radix 4 FFT, Bits = 14 si(*pi*f1*p/fs) 4 MATLAB FFT si(*pi*f1*p/fs) db db Amplitude error factor Radix 4 FFT/MATLAB FFT Phase error db Phase error Fig.1. Radix4 FFT, 14bit legth of samples 4 Radix 4 FFT, Bits = 16 si(*pi*f1*p/fs) 4 MATLAB FFT si(*pi*f1*p/fs) db db Amplitude error factor Radix 4 FFT/MATLAB FFT Phase error db Phase error Fig.11. Radix4 FFT, 16bit legth of samples
33 33(5) As the costrais for the realtime FFT costructio was to miimize the phase ad amplitude error as much as possible, but ot more tha that the costructio could be realizable. The simulatio results poited towards 16 bits, as this result had a small value of phase error. 8.4 RADIX4 FFT ALGORITHM, = 64 The first attempt of the implemetatio phase was to implemet a Radix4 FFT algorithm, with legth 64 complex samples. For a Radix4 FFT with legth = 64, there are 3 dragofly raks, with each rak comprisig 16 dragoflies. I the first revisio of the costructio, the bitlegth of the iput samples to the first dragofly rak was 1, this due to the precisio of the quadrature block i figure 8. Those iput samples were the multiplied with the phase factor for the correct block, also with a precisio of 1 bits. As the complex output of the multiplicatio will geerate 1 * 1 => 4 bits, the complex output of the multiplicatio is rouded of ad trucated to 14 bits. This results i a 14 bits iput to the secod rak of dragoflies, which will by usig the same model as for the first rak of dragoflies, geerate a complex output with the legth of 16 bits. As we also have a third rak of dragoflies, the complex output from our FFT costructio will have 18 bits. Radix4 FFT, = 64 I 1bits Q 1bits Dragofly rak I I I 14 bits 16 bits 18 bits Dragofly rak Dragofly rak Q Q Q 14 bits 16 bits 18 bits Fig.1. Radix4 FFT, = 64 The FFTblock was costructed usig the software EASE ad the programmig laguage VHDL, i.e. Very high speed itegrated circuit Hardware Descriptio Laguage. The software Ease is a block model descriptio laguage that lets you costruct the algorithm as blocks ad takes care of the itercoectio betwee the blocks ad the geerates the VHDL code for this itercoectio [1].
34 34(5) Part of the VHDL  code for oe of the dragoflies i the first of the raks is as follows: begi  process radix4 if clk'evet ad clk = '1' the ar_temp <= ir*cos_j; ai_temp <= ii*si_j; br_temp1 <= i1r*cos_1j; br_temp <= i1i*si_1j; bi_temp1 <= i1i*cos_1j; bi_temp <= i1r*si_1j; cr_temp1 <= ir*cos_j; cr_temp <= ii*si_j; ci_temp1 <= ii*cos_j; ci_temp <= ir*si_j; dr_temp1 <= i3r*cos_3j; dr_temp <= i3i*si_3j; di_temp1 <= i3i*cos_3j; di_temp <= i3r*si_3j; br_temp <= br_temp1 + br_temp; bi_temp <= bi_temp1  bi_temp; cr_temp <= cr_temp1 + cr_temp; ci_temp <= ci_temp1  ci_temp; dr_temp <= dr_temp1 + dr_temp; di_temp <= di_temp1  di_temp; ar_roud <= ar_temp((*1) dowto (3)) + roud; ai_roud <= ai_temp((*1) dowto (3)) + roud; br_roud <= br_temp((*1) dowto (3)) + roud; bi_roud <= bi_temp((*1) dowto (3)) + roud; cr_roud <= cr_temp((*1) dowto (3)) + roud; ci_roud <= ci_temp((*1) dowto (3)) + roud; dr_roud <= dr_temp((*1) dowto (3)) + roud; di_roud <= di_temp((*1) dowto (3)) + roud; temp1r <= ar_roud((+) dowto 1) + cr_roud((+) dowto 1); temp1i <= ai_roud((+) dowto 1) + ci_roud((+) dowto 1); tempr <= ar_roud((+) dowto 1)  cr_roud((+) dowto 1); tempi <= ai_roud((+) dowto 1)  ci_roud((+) dowto 1); ar_out <= temp1r + br_roud((+) dowto 1) + dr_roud((+) dowto 1); ai_out <= temp1i + bi_roud((+) dowto 1) + di_roud((+) dowto 1); br_out <= tempr + bi_roud((+) dowto 1)  di_roud((+) dowto 1); bi_out <= tempi  br_roud((+) dowto 1) + dr_roud((+) dowto 1); cr_out <= temp1r  br_roud((+) dowto 1)  dr_roud((+) dowto 1); ci_out <= temp1i  bi_roud((+) dowto 1)  di_roud((+) dowto 1); dr_out <= tempr  bi_roud((+) dowto 1) + di_roud((+) dowto 1); di_out <= tempi + br_roud((+) dowto 1)  dr_roud((+) dowto 1); ed if; ed process radix4; ed a ;  of Block1 The VHDL code above describes exactly the dragofly illustrated i figure 5. For this block the phase/twiddle factor is simple ad ca easy be realized as a right shift of the iput sigal, but as we get towards the last dragofly i the costructio, the phase factor costat gets more complex ad has to be realized as a high performace multiplier. The total block descriptio is described i appedix A1. The 64 complex iput sigals is shifted ito the FFTblock usig a shift register. This register is divided ito a real ad a imagiary part where the iput (complex) gets a ew sample every clock cycle. Whe the shift register gets full, it geerates a valid sigal that triggs the FFTblock that starts the FFT process. Whe the process is doe, a ew valid sigal is geerated, ad a output shift register is started. For every clock cycle, a ew processed value is delivered to the output. After all 64 values are delivered the valid sigal gets low ad shows that every sample has bee shifted out.
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