# A MOSFET only, Step-Up DC-DC Micro Power Converter, for Solar Energy Harvesting Applications

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2 II. SYSTEM ARCHITECTURE A. Circuit Concept A simplified schematic of the step-up converter circuit is depicted in Figure. the parasitic capacitance nodes. This circuit is depicted in Figure 2. In here, C p{,2} stand for the parasitic capacitance at the bottom plate nodes of each of the MOS capacitors, M and M 2, respectively. This capacitance is constituted by (C db + C sb ). to 2 v dd C v in 2 bottom R L C O Figure. Simplified schematic of the step-up converter. The principle of operation of the circuit is that of the capacitive voltage doubler [6]: during phase, capacitor C is charged with the input voltage value and then, during phase 2, it is connect in series with the input voltage source, resulting in an output voltage (v dd ) that is two times larger than the input voltage value. Assuming that the output of this circuit is connected to a load resistance (R L ) in parallel with a large external capacitance C o, the resulting equivalent circuit consists of a voltage source (with a voltage value equal to 2 v in ) in series with two impedances. The first one is the equivalent impedance of the switched-capacitor and the second one is the load resistance. The average output voltage of this circuit is the voltage division of 2 v in by the resistive divider formed by these two impedances. The output voltage will have a ripple that is inversely proportional to the value of C o. The value of this capacitance will regulate the upper limit of the output voltage ripple, being inversely proportional to it. The output voltage value can be regulated by adjusting the value of the equivalent impedance of the switched capacitor. This is done by dynamically changing the frequency of the clock signals that control the switches of the circuit. This change is achieved by an asynchronous state machine (ASM) phase controller. Any real implementation of the previous circuit is plagued by a parasitic capacitance in the bottom plate node. The capacitance is charged up to v in during phase and discharged during phase 2. This is equivalent to a resistance that dissipates energy, thus lowering the efficiency of the circuit. This problem can be particularly serious if MOS capacitances are used, because of the large parasitic capacitance value they introduce. In order to improve the efficiency, it is necessary to reduce the amount of charge that is lost in the parasitic capacitance. This is achieved by splitting the capacitance in two and duplicating the circuit, resulting in an operation with the double of the frequency. Now, the circuit can have a third phase, where the bottom plate nodes of the two half-circuits are connected together, thus transferring half of the charge in one parasitic capacitance to the other, before shorting the first bottom node to ground. This reduces the amount of lost charge by half in Figure 2. Complete schematic of the proposed step-up converter. Since both MOS capacitors have the same area, it will be considered that both parasitic capacitances have the same value. Considering ideal voltages and operation, M and M 2 will alternate their role: when is active, M and C p2 are connected in parallel with the input voltage, putting M 2 in series with the input voltage, achieving the voltage doubling at the output, v dd. During this time interval, C p is discharged, as both of its plates are grounded. When 3 is active, M 2 and C p change role with M and C p2, leading to the same behavior that took place when was active. When 2 is active, C p and C p2 are connected in parallel, accomplishing a charge distribution between these two parasitic capacitances. Due to the fact that one of these capacitances is charged to v in while the other is completely discharged, when they are connected together, the charge is equally divided, and each capacitor will have half of the charge of the capacitor that was charged to v in. Ideally, the voltage across this parallel circuit will be v in /2. By doing this, when the circuit returns to or 3 (depending on which was first), the parasitic capacitor that will steal charge from the input voltage will be already pre-charged to half of this voltage value. This leads to a lower waste of charge, coming from the input (PV cell), since half of the charge that would be lost is already present. B. Generation of the clock phases The state diagram of the ASM is shown in Figure 3. The state machine for the phase controller has four states. Each of these states determines which clock phase is active. The time needed to charge the capacitance M (state, phase active) depends upon the maximum current available from the PV cell and on the RC time constant of the switches and capacitor M. Since this time can change with the available light, a minimum time span, for each state, must be adjusted. The minimum

3 duration for phase is given by the time needed to charge M up to 9% of v in, which is a voltage named v B. This is determined by comparing the voltage of the top plate node of M (which is named v MOSa ) to v B. The output voltage decreases slowly because of the large value of the output capacitance C o. When v MOSa is larger than v B, and when the output voltage is smaller than a reference value, phase 3 must be activated in order to connect M to the output node, thus transferring its charge to C o and restoring the output voltage value. next. There is a delay circuit after each latch, in order to prevent a premature change to the next state. A reset signal guarantees that during start-up, the ASM is at state2. The reference voltage, V ref, is an absolute voltage and it must be generated by a bandgap circuit such as the one described in [7]. This circuit needs less than A to work. Figure 3. State diagram of the state machine for the phase controller. The transition from state to state3 occurs having state2 in between. In this state, capacitor C p (which was fully discharged) is connected in parallel with C p2, replenishing the charge of C p by connecting this capacitance in parallel with C p2 (which was charged up to v B ), thus obtaining half of C p2 charge. This is done by activating phase 2. In state3, capacitors M and M 2 exchange their role, and the circuit behaves like in state, except for the fact that the main (and the parasitic) capacitances are swapped. Also, instead of considering v MOSa, it should be considered v MOSb. This voltage is the counterpart for v MOSa in the lower half of the circuit depicted in Figure 2. Before changing from state3, back to state, the state machine goes through state4, in order to activate 2 with the same purpose as described before, but with the parasitic capacitance roles exchanged between them. In the beginning of each state, it is necessary to introduce a delay before performing any comparison between any two voltages, allowing for the parasitic capacitance charges at the bottom plate nodes of M and M 2 to settle before proceeding. The circuit of the ASM phase controller is shown in Figure 4. The four states of the circuit are determined by the output of four latches. When the Set signal of one latch is active (this can depend on the result of a voltage comparison), the output of the latch changes from to. This, in turn, activates the Reset signal of the previous latch, causing its output to change from to, thus completing the change from one state to the Figure 4. Phase controller schematic. The v B reference voltage is obtained by applying the input voltage (v in ) to a voltage divider with the ratio of 9 out of. The output voltage (v dd ) also undergoes a voltage divider, obtaining v 2, which is half v dd. The schematic of the delay circuit is shown in Figure 5. Figure 5. Schematic of the delay circuit. This circuit delays the rising edge of its input signal. The amount of delay is controlled by the time constant formed by C delay and the R DS resistance of transistor M 4 (which operates in the linear region). Most of the transistors in this circuit, as well the transistors in the ASM circuit, are designed to the

4 minimum size allowed by the technology, in order to reduce the power dissipation of the phase controller circuit and thus, improving the efficiency. The circuit only uses transistors with larger sizes where the drive capability of the gates is important, such as for the phase buffers. The schematic of the comparator circuit is shown in Figure 6. working. This circuit also provides the reset signal, and its complement, for the ASM. A. PV cell equivalent circuit The PV cells described in [5], have an open circuit voltage of around 47 mv, which is a value too low to use with a voltage doubler circuit, requiring a step-up converter capable of multiplying by 3. Given that the desired output voltage is low (.2 V), this type of converter would have a very low efficiency [6]. Therefore, it is preferable to use two PV cells in series, in order to obtain an open circuit voltage of around 92 mv. Using the measurement data from [5] it is possible to extrapolate that a PV cell with 3 mm 2 would produce around 39 W and would have a short circuit current of.62 ma. A PV cell can be modeled by an equivalent electric circuit, shown in Figure 8. The values of the parameters of the equivalent circuit (I S, R P and R S ) are adjusted to match as best as possible the extrapolated data for the PV cell. Figure 6. Schematic of the comparator circuit. This comparator circuit is composed by a PMOS differential pair with a positive feedback load, in order to obtain a large voltage gain with a low power supply voltage value and thus, reducing the systematic offset. This stage is followed by three gain stages to increase the overall gain in order to saturate the output voltage to an unambiguous logic level. These comparators are self biased using a PMOS and a NMOS transistor connected in diode. Each comparator draws a DC current of approximately 8 A from the power supply. III. SIMULATION RESULTS In order to verify the functionality of the step-up converter, the circuit was designed in a.3 m CMOS technology and simulated using Spectre. The option of using MOS capacitors allows obtaining an area eight times smaller than the one that would have been if the capacitors implemented by M and M 2 were implemented with MiM capacitors instead. The estimative for the area of M is 46 m 2, but if a MiM capacitor was used instead, this area would increase to 33 m 2, for the same value of capacitance. The schematic of the start-up circuit is depicted in Figure 7. Figure 8. Equivalent electrical circuit of a PV cell. Two PV cells in series (each having 3 mm 2 ) are simulated using two equivalent circuits in series, resulting in the power curves depicted in Figure 9. PV cells output power ( W) Maximum illumination 95% of maximum 9% of maximum 8% of maximum 6% of maximum PV cells output voltage (V) Figure 9. Power curve of two PV cells equivalent circuits connected in series, for different levels of illumination. Figure 7. Start-up circuit schematic. This circuit shunts the input and the output nodes during the start-up of the circuit, guaranteeing that the phase controller circuit has a high enough power supply voltage to start In here, one can depict the PV cells output power functions for some levels of light intensity, namely, for %, 95%, 9%, 8% and 6% of the maximum illumination. The maximum available power at the output will be in accordance to the light intensity to which the cell is subjected. The information about the maximum power available from the PV cells, as well as the voltage at which that maximum power occurs, the short circuit current and the open circuit voltage, is summarized in TABLE I.

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