AUSTROCHIP 2002 IBM EX. 1011

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1 AUSTROCHIP 1 IBM EX. 111

2 Austrochp Insttut für Elektronk Technsche Unverstät Graz Inffeldgasse 1 A-81 Graz Tel: Fax: Emal: Copyrght Insttut für Elektronk ISBN

3 AUSTROCHIP TAGUNGSBAND 4. OKTOBER GRAZ, ÖSTERREICH TECHNOLOGIEVERBUND MIKROELEKTRONIK ÖSTERREICH HERAUSGEBER PETER SÖSER ANDREAS BUSLEHNER INSTITUT FÜR ELEKTRONIK TECHNISCHE UNIVERSITÄT GRAZ, ÖSTERREICH 3

4 ORGANISATION Andreas Buslehner, Technsche Unverstät Graz Banca Deutschmann, Technsche Unverstät Graz Helene Öttl, Technsche Unverstät Graz Peter Söser, Technsche Unverstät Graz VERANSTALTER Insttut für Elektronk, Technsche Unverstät Graz, Mtgled m Technologeverbund Mkroelektronk Österrech (TÖM), zu dem weters de folgenden Insttutonen gehören: Insttut für Angewandte Informatonsverarbetung und Kommunkatonstechnologe, Technsche Unverstät Graz Insttut für Computertechnk, Technsche Unverstät Wen Insttut für Integrerte Schaltungen, Johannes Kepler Unverstät Lnz Fachhochschule Technkum Kärnten, Vllach, Studengang Elektronk BEGUTACHTER DER BEITRÄGE Thomas Bauernfend, Johannes Kepler Unverstät Lnz Gerhard R. Cadek, Technsche Unverstät Wen Martn Horauer, Fachhochschule Technkum Wen Roland Höller, Technsche Unverstät Wen Nkolaus Kerö, Technsche Unverstät Wen Hans Leopold, Technsche Unverstät Graz Manfred Ley, Fachhochschule Technkum Kärnten Erwn Ofner, Fachhochschule Technkum Kärnten Tmm Ostermann, Johannes Kepler Unverstät Lnz Karl C. Posch, Technsche Unverstät Graz Robert Röhrer, Technsche Unverstät Graz Peter Rössler, Technsche Unverstät Wen Gunter Wnkler, Technsche Unverstät Graz Johannes Wolkerstorfer, Technsche Unverstät Graz SPONSOREN austramcrosystems AG CISC Semconductor Desgn+Consultng Infneon Technologes AG PHILIPS Semconductors 4

5 Vorwort der Herausgeber De Tagung AUSTROCHIP fndet heuer zum zehnten Mal statt und hat zum Zel, Wssenschaft und Industre aus dem Berech der Mkroelektronk zusammenzubrngen. AUSTROCHIP betet Ingeneuren aus Wrtschaft und Wssenschaft de Möglchket, Arbeten, n denen nnovatve Entwurfstechnken oder Integratonstechnologen engesetzt wurden, zu präsenteren. AUSTROCHIP wrd von ver Unverstätsnsttuten und ener Fachhochschule getragen. Dese Mkroelektronk-Entwurfszentren snd m Technologeverbund Mkroelektronk Österrech (TMÖ) zusammengeschlossen. Der desjährge Veranstalter st das Insttut für Elektronk der Technschen Unverstät Graz. De Bedeutung der Mkroelektronk als ene der Schlüsseltechnologen für de Informatonsgesellschaft muss ncht egens betont werden. De Umsetzung deser Erkenntns n entsprechende Erfolge für de österrechsche Wrtschaft und Wssenschaft bedarf jedoch auf Grund der mmensen Dynamk deser Technologe mmer weder neuer Akzente. AUSTROCHIP wll en solcher sen. De Tagung hat folgende Schwerpunkte: Unverstätsnsttute stellen hre neuesten wssenschaftlchen Arbeten vor. Industrebetrebe präsenteren Projekte. De klen- und mttelständschen Betrebe sollen vom aufgebauten Know-how auf den Unverstäten profteren. Junge Wssenschaftler nehmen mt der Industre Kontakte auf. Der Technologeverbund Mkroelektronk Österrech präsentert sch als kompetenter und erfahrener Partner m ndustrellen Ensatz aktueller Mkroelektronk. Im heurgen Jahr wurden 31 Beträge engerecht. Das Begutachtungskomtee hat 14 davon zur Präsentaton be der Tagung ausgewählt. Zusätzlch wurden 1 Beträge ausgewählt, welche als Poster präsentert werden können. Jeder engerechte Betrag wurde von zumndest 3 Begutachtern bewertet. 6 der engerechten Arbeten stammen von Autoren, de n der Industre tätg snd. 13 Arbeten wurden von Autoren engerecht, welche an Unverstäten forschen und arbeten. Wetere 1 Arbeten stammen von gemschten Autorenteams, wobe her ene Tendenz zu ener Internatonalserung schtbar wrd. So stammen Partner n den engerechten Beträgen aus Deutschland, Italen und Irland. Dese Mschung der Beträge zegt, dass sch de Tagung AUSTROCHIP zum jährlchen Treffpunkt der enschläggen Forscher und Entwckler m Berech Mkroelektronk etablert hat. Wr bedanken uns be allen Autoren für deren Mühe. Ohne hre Mtarbet gäbe es kene Tagung. Außerdem bedanken wr uns be den Mtgledern des Begutachtungskomtees für hre Arbet. Weterer Dank glt natürlch auch den Sponsoren, de mt hren fnanzellen Beträgen ene - vor allem für Studerende - nteressante Gestaltung des Tagungsbetrages ermöglchen und de auch n engeladenen Vorträgen Aktuelles aus hrem Arbetsumfeld präsenteren. Peter Söser Andreas Buslehner 5

6 Inhaltsverzechns Kurzfassung des engeladenen Vortrags: The Path to Frst Tme Rght Analog Crcuts 1 D. PATTULLO, E. SEEBACHER, W. PRIBYL, austramcrosystems AG, Unterpremstätten. Tagungsbeträge, de als Vortrag präsentert werden: SubCALM: En Smulatonstool zur Abschätzung von Substratkopplungen mt Hlfe von vorberechneten Makromodellen 5 Th. BRANDTNER, Infneon Technologes, Graz; R. WEIGEL Lehrstuhl für Technsche Elektronk, Unverstät Erlangen-Nürnberg. A Synthess Tool for Applcaton Specfc Gate Arrays 13 M. HÜTTER, Insttut für Angewandte Informatonsverarbetung und Kommunkatonstechnologe, TU-Graz; H. BOCK, Infneon Technologes, Graz. APPLES: A Full Gate-tmng Hardware Smulator 1 D. DALTON, A. VADHER, V. BESSLER, J. GRIFFITHS, A. McCARTHY, R. O KANE, Neosera, Dubln; Ch. STEGER, Insttut für Technsche Informatk, TU-Graz. Phase Nose Modellng n Phase Locked Loop Frequency Syntheszers 9 R. NONIS, P. PALESTRI, L. SELMI, DIEGM, Unverstät Udne; N. DA DALT, Infneon Technologes, Vllach. Modellng the Transent Behavour of Swtched-Capactor Integrators 37 A. BUSLEHNER, P. SÖSER, Insttut für Elektronk, TU-Graz. En Überblck über das Projekt LIMA Learnng Platform n Mcroelectronc Applcatons 45 T. OSTERMANN, C. LACKNER, R. KÖSSL, R. HAGELAUER, Insttut für Integrerte Schaltungen, Unverstät Lnz; M. PISTAUER, CISC, Klagenfurt; K. BEER, s.team, München; L. KRAHN, H.-T. MAMMEN, W. JOHN, Fraunhofer Gesellschaft für Zuverlässlchket und Mkrontegraton, München; A. SAUER, P. SCHWARZ, G. ELST, K.-H. DIENER, Fraunhofer Gesellschaft für Integrerte Schaltungen, Außenstelle Entwurfsautomatserung, Dresden. A Flexble, Module-based System-on-Chp for Low-Power VoIP Applcatons 51 P. FUGGER, J. GRAF, Ch. JENKER, F. MÜLLER, E. OITZL, H. WALCHER, J. SALZMANN, M. STEINER, Infneon Technologes, Vllach. Open-Source IP Cores Three Case Studes 57 R. HÖLLER, H. HAMET, M. MAKAREWICZ, Insttut für Computertechnk, TU-Wen. Ene unverselle AES Hardware Archtektur 65 S. DOMINIKUS, St. MANGART, Insttut für Angewandte Informatonsverarbetung und Kommunkatonstechnologe, TU-Graz. 6

7 Surface Scan to pnpont EMC Problems 73 B. DEUTSCHMANN, R. JUNGREITHMAIR, austramcrosystems AG, Unterpremstätten. A 11-Bt Low Power Mult-Bt Contnouos Tme Delta-Sgma ADC for UMTS n a.1 µm CMOS process 79 L. DÖRRER, A. D GIANDOMENICO, A. WIESBAUER, Infneon Technologes, Vllach. Operatonal Amplfer wth Bulk Regulator for extended Input-Voltage Range n dgtal 1 nm CMOS Technology 83 F. SCHLÖGL, H. ZIMMERMANN, H. DIETRICH, H. ARTHABER, Insttut für Elektrsche Messtechnk und Schaltungstechnk, TU-Wen. Analog Frontend Demodulator for Contactless Smart Card ICs 87 M. KUPNIK, CD-Labor für sensorsche Messtechnk, Insttut für Automaton, Un-Leoben; G. MELCHER, T. SCHLAGER, Infneon Technologes, Graz. Entwurf enes ASICs zur Steuerung von Modellesenbahnlokomotven 91 S. RANNINGER, P. SÖSER, Insttut für Elektronk, TU-Graz. Beträge, de zur Tagung angenommen wurden und evt. als Poster präsentert werden: A PCI-Card for Acceleratng Ellptc Curve Cryptography 95 J. WOLKERSTORFER, W. BAUER, Insttut für Angewandte Informatonsverarbetung und Kommunkatonstechnologe, TU-Graz. Modular Constructon System for Embedded Real-Tme Applcatons 13 M. DELVAI, U. EISENMANN, W. HUBER, Insttut für Technsche Informatk, TU-Wen. A Mult-Rate Channel Processng Unt for G/3G Mult-Standard Wreless Access Technolges and Future Software Rado Systems 111 A. BLAICKNER, H. STERNER, L. SHIH-FU, A. MACHNE, C. SCHEICHL, M. NOVAK, H. GRÜNBACHER, Carntha Tech Insttute, Vllach; M. BACHER, M. MÜLLER, Infneon Technologes, Vllach. Entwcklung und Analyse energe-effzenter System-on-Chp Desgns am Bespel der Multmeda Platform 119 J. HAID, Ch. STEGER, R. WEISS, Insttut für Technsche Informatk, TU-Graz; W. SCHÖGLER, P. KAMMERLANDER, M. MANNINGER, austramcrosystems AG, Unterpremstätten. ASICs m Internet Das Projekt asx4web 15 P. RÖSSLER, Insttut für Computertechnk, TU-Wen. Low-cost AES 131 Ch. RECHBERGER, Th. POPP, St. TILLICH, TU-Graz Ene adaptve Methode zur Unterdrückung von Local Oscllator Leakage be Bretband-Homodyn-Modulatoren 137 Ch. LANSCHÜTZER, A. SPRINGER, L. MAURER, R. WEIGEL, Insttut für Nachrchtentechnk und Informatonstechnk, Johannes Kepler Unverstät Lnz; Z. BOOS, Infneon Technologes, München. 7

8 Matlab Toolbox Functons for Desgn and Implementaton of Bt-seral Poly-phase FIR Flters 141 A. HRADETZKY, M. CASTELLI, E. OFNER, H. GRÜNBACHER, Carntha Tech Insttute, Vllach. Modellerung und Entwurf enes ntellgenten, vollständg ntegrerten, kapaztven Absolutwnkelmeßsystems 149 H. NACHTNEBEL, N. KERÖ, Th. SAUTER, Insttut für Computertechnk, TU-Wen En Test-Chp zur Untersuchung des Enflusses von On-Chp Decouplng Kapaztäten zur Verrngerung der Störemsson von Ics 157 T. OSTERMANN, D. SCHNEIDER, Ch. BACHER, Ch. LACKNER, R. KÖSSL, W. GUT, Th. BAUERNFEIND, R. HAGELAUER, Insttut für Integrerte Schaltungen, Unverstät Lnz; B. DEUTSCHMANN, R. JUNGREITHMAIR, austramcrosystems AG, Unterpremstätten. 8

9 A PCI-Card for Acceleratng Ellptc Curve Cryptography Johannes Wolkerstorfer and Wolfgang Bauer Insttute for Appled Informaton Processng and Communcatons (IAIK) Graz Unversty of Technology Inffeldgasse 16a, 81 Graz, AUSTRIA Abstract In ths artcle we present a PCI-card for acceleratng Ellptc Curve Cryptography. The card has applcaton n e- Commerce and e-government where Internet servers establsh secure and authentcated communcaton wth clents over publc networks. All ellptc-curve operatons are processed on the card to lberate the software from ths computatonal ntensve task. The hardware s optmzed for a partcular class of ellptc curves. A medum-szed FPGA serves as target technology, whch allows to update the card n the feld and to customze the hardware quckly to other curves or even mproved algorthms. The current mplementaton s optmzed for an 191-bt ellptc curve over GF( 191 ) and s able to calculate 1 scalar multplcatons per second on a Xlnx Spartan-II devce. A hghly parallel radx-56 dgt-seral multpler accounts for the hgh throughput. The maxmum clock frequency s 7 MHz. 1 Introducton Informaton securty s one of the man aspects of e- Commerce and e-government. In ths fast-growng area new servces only fnd acceptance when they provde a suffcent level of securty n terms of authentcaton, confdentalty, data ntegrty, and non-repudaton. For nstance, the Weßbuch Bürgerkarte [1] focuses on securty aspects of the Austran e-government actvtes and emphaszes the role of secure dgtal-sgnatures as a key technology. Ellptc Curve Cryptography (ECC) s a technology that fulflls all the demands and requres only moderate resources []. Dgtal sgnatures as well as key establshment algorthms, whch are requred to establsh encrypted channels n nsecure networks, belong to the asymmetrc cryptography [3]. ECC can mplement asymmetrc cryptography very effcently because t s based on the Ellptc-Curve- Dscrete-Logarthm-Problem (ECDLP). No algorthm wth sub-exponental runnng tme s known to solve ECDLP. Alternatves to ECC are methods based on the dscrete logarthm problem or the factorzaton problem. Both requre btlengths of 48-bt to obtan adequate securty. ECC s content wth much smaller btlengths to acheve the same level of securty and s thus favored n resourceconstrcted devces lke smartcards. ECC covers all relevant asymmetrc cryptographc prmtves lke dgtal sgnatures and key agreement algorthms and s standardzed by many organzatons. A relevant standard for ths artcle s the ANSI X9.6 standard. It defnes the Ellptc Curve Dgtal Sgnature Algorthm (ECDSA) [5]. ANSI X9.63 defnes cryptographc prmtves for key agreement [6]. The man porton of these prmtves s calculated by the PCI-card to accelerate ECC. Such a dedcated hardware soluton offers the advantage to process data at the full wordsze of m bts. In ths artcle the wordsze s fxed to 191 bts, although the developed hardware-descrpton model has a scalable wordsze. Operatng at the full wordsze wll turn out to be the man contrbutor to outperform software solutons, whch have to operate on 3-bt words. Calculatons on ellptc curves nvolve doublng and addton of curve ponts. These operatons are calculated by operatons n the fnte feld GF( m ). The overall performance of an ellptc-curve processor s manly determned by the speed to multply feld elements. Hence, the multpler wll be the most mportant buldng block of such a processor and parallelzaton of the multplcaton wll be a key ssue n the desgn of the archtecture. If the costly nverson of feld elements s avoded, the enlarged effort to control EC-operatons needs specal attenton n a hardware mplementaton to prevent the crtcal path from beng n the control unt. The remander of ths artcle s structured as follows. Secton hghlghts the applcaton of the ECC-acceleratorcard to pont out the motvaton for ths work and secton 3 gves an overvew over related work that takes both software mplementatons and hardware mplementatons nto account. Secton 4 brefly presents the mathematcal background, whch s useful to explan the desgn consderatons of the hardware archtecture n secton 5. The PCI nterface and the software level are dscussed n secton 6. Secton 7 presents results, and conclusons are drawn n secton

10 Applcaton The PCI-card for acceleratng ECC has an applcaton n e-commerce an e-government. It accelerates the ECoperatons on the server sde as depcted n Fgure 1. costumers, clents ECC e-commerce server, e-government server Fgure 1: Applcaton The performance of EC-operatons on the clent sde of such an applcaton s not crtcal. The authentcaton, the negotaton of encrypton keys, and the sgnng of documents may take up to a second and can be done effcently wth smartcards or smlar devces. The server sde on the other hand has to process EC-operatons for a multtude of clents and to perform other operatons lke database queres. A dedcated ECC-accelerator-card wll releve the computatonal effort of the server. 3 Prevous work Up to our knowledge there are no ECC-accelerator-cards commercally avalable by now. Scentfc results for acceleratng EC-operatons wth hardware wll be gven below. A rough comparson of the throughput can be made by lookng at the performance of hardware-accelerator-cards for asymmetrc cryptography based on the RSA algorthm. For nstance, the AEP SSL Accelerator card from AEP Systems has a throughput of up to encryptons per second for 14-bt btlength [7]. Ths wll reduce to approxmately 5 encryptons for 48 bts, whch s comparable to 191-bt ECC. Darrel Hankerson et al. presented the fastest known software mplementaton of EC-operatons n [8]. Ther assembler optmzed mplementaton on a 4 MHz Pentum-II processor reached 594 EC-operatons per second for a 163-bt curve and 5 operatons for 33-bt. Ths compares roughly to 414 EC-operatons for a 191-bt curve and t should be consdered that the CPU load for these values s 1%. Nothng else can be computed wthout deteroratng the throughput. One of the frst ECC hardware mplementatons was reported 1993 by G. B. Agnew et el. n [9]. Ther mplementaton s a mere coprocessor for operatons n the fnte feld GF( 155 ) and EC-operatons are controlled by a multpurpose processor. Ths ASIC mplementaton s bascally a bt-seral multpler wth a clock frequency of 4 MHz. James Goodman and Anantha P. Chandrakasan publshed ther so-called Doman-Specfc Reconfgurable Cryptographc Processor n [1]. Ther versatle desgn can operate wth btlengths from 4-bt up to 14-bt and can calculate modular nteger-arthmetc besdes operatons n the fnte feld GF( m ). Ths ASIC crcut can be clocked wth 5 MHz and calculates approxmately bt ECoperatons per second. Gerardo Orlando and Chrstof Paar reported the fastest known EC-processor n [1]. Ther FPGA mplementaton s also optmzed for a partcular class of ellptc curves (fxed btlength), has a dgt-seral multpler, and an extra square unt to explot a shortcut offered by GF( m )- arthmetc. A large nternal memory allows the use of algorthms, whch rely on pre-computatons. Ths mplementaton should have a throughput of about EC-operatons per second when t s clocked wth 7 MHz and when a radx-56 multpler s used. M. Ernst et al. presented n [11] an FPGA-based PCIcard for ECC-acceleraton. Contrary to the wdely used polynomal-bass representaton of GF( m )-elements, they use an optmal-normal bass representaton that cannot be drectly compared wth a polynomal representaton. A 191- bt verson of ther PCI-card wth a radx-3 multpler can be clocked wth 36 MHz and has a throughput of 431 ECoperatons. The card can be accessed from a personal computer runnng under Wndows NT va a C++-nterface. 4 Mathematcal background ECC s based on the Ellptc Curve Dscrete Logarthm Problem (ECDLP). The ECDLP states that t s a hard problem to fnd the scalar k n Q=k P when the curve ponts Q and P are gven. No sub-exponental-tme algorthm s known to solve the ECDLP for non-super-sngular ellptc curves [3]. The scalar-multplcaton Q=k P s therefore the basc operaton n all ellptc-curve cryptographc prmtves lke the Ellptc Curve Dgtal Sgnature Algorthm (ECDSA) [5]. The scalar-multplcaton can be calculated by repeated pont addtons Q = k P = P + P + K + P = = k P + k P + k 4P + K + k P 1 or more effcently by the double-and-add algorthm, whch teratvely doubles the pont P (P, P, 4P,...) and accumulates those multples of P where the accordng bt k of the bnary representaton of the scalar k s 1. Ths procedure requres functons to double ponts and to add them. De- 96 1

11 taled nformaton about the mathematcal background of ECC can be found n [4]. A pont P on an ellptc curve over a fnte feld of characterstc s a tupel P=(x, y) where x and y are elements of the fnte feld GF( m ) n our case m s fxed to 191. Every pont on an ellptc curve fulflls the affne equaton of the ellptc curve 3 m EC : y + xy = x + ax + b, a, b GF( ) where the parameters a and b defne a partcular curve over GF( m ). In addton to all tupels fulfllng the curve equaton, the so-called pont-at-nfnty O belongs to the curve. The set of all ponts together wth a general pont addton form a commutatve group. The general pont addton P 1 +P dstngushes between the cases that P 1 P (addton), P 1 =P (double), and P 1 =-P (pont-at-nfnty O). The pont-at-nfnty s the neutral element for the general pont addton: P 1 +O=P 1. Addton and doublng of ponts s calculated by feld operatons on the coordnates of the tupel. Pont doublng s gven by P1 + P = ( x1, y1) + ( x, y ) = ( x3, y3 ), P1 P 1 λ = ( y1 + y )( x1 + x ) x3 = λ + λ + x1 + x + a y = ( x + x ) λ + x + y. 3 1 Pont addton s gven by P = ( x, y) = ( x3, y3 ) 1 λ = yx + x x3 = λ + λ + a y = ( x + x ) λ + x + y From the formulas for pont addton and pont doublng t can be seen that the fnte-feld operatons addton, multplcaton, squarng and nverson are requred to calculate EC-operatons. Inverson s the most complex operaton. It can (nearly) be avoded f projectve coordnates are used to represent ponts. An n-depth descrpton of ths topc s omtted here, but nterested readers should refer to [4]. The trck of projectve coordnates s to avod nverson by representng a pont by a trple (x,y,z) of feld elements. Ths comes at the cost of an ncreased number of multplcatons for pont addton and pont doublng but wll pay off, as long as the cost of an nverson s more than ten tmes hgher than those of a multplcaton. Projectve coordnates requre only one nverson to transform a projectve result (x,y,z) back nto an affne representaton (x,y ) Operatons n the fnte feld GF( m ) Elements of the fnte feld GF( m ) can be represented as polynomals of degree smaller than m wth bnary coeffcents: a( x) = a = m 1 = + a x + a x 1 a x, + Ka x, a( x) GF( a {,1}. Elements of GF( m ) are fully determned by ther bnary coeffcents whch allows to represent them as strngs of m bts. In example, an element of GF( 191 ) can be stored n a 191-bt regster. Operatons on feld elements of GF( m ) are derved from calculatons wth polynomals. The addton a(x)+b(x) of two elements a(x),b(x) œ GF( m ) s done coeffcent-wse: = = a ( x) + b( x) = a x + b x = ( a b ) x. = The symbol denotes the addton n the feld GF(), whch s an nteger addton modulo. Ths corresponds to the Boolean XOR-functon. A hardware mplementaton of the coeffcent-wse addton scheme can be realzed wth m XOR-gates, whch add correspondng bts of the btstrng representaton of a(x) and b(x). Contrary to nteger addton, addton n GF( m ) has a constant complexty of O(1) for arbtrary m because no carry propagaton occurs. A notceable feature of addton n GF( m ) s the fact that an element s ts own addtve dentty: a(x)+a(x)=. Ths observaton accounts for the dentty of addton and subtracton: a(x)+b(x)=a(x)-b(x). Multplcaton n GF( m ) s more complex than addton and has some smlartes to modular nteger multplcaton. A pure polynomal multplcaton a(x) b(x) wll result a polynomal of degree less or equal than (m-1): a ( x) b( x) = a( x) b x = ( a( x) b ) x. = = In case, the result has a degree hgher than m-1 t s not an element of GF( m ) anymore. It s necessary to apply a modular reducton step, whch calculates the remander of a polynomal dvson by an rreducble polynomal. The rreducble polynomal has degree m and defnes the polynomal-bass representaton of the fnte feld GF( m ). The rreducble polynomal n our GF( 191 )-example s f(x) = x 191 +x 9 +1; as defned n Example 1 of Annex J4.3 n [5]. It s possble to avod ntermedate results that have nearly double the btlength by nterleavng the modular reducton n the multplcaton. A MSB-to-LSB scheme of ths procedure s shown n Algorthm 1. In every teraton a partal product a(x)b s added to the ntermedate result c(x). In case c(x) has degree m, the rreducble polynomal f(x) s subtracted to ensure c(x) s an element of GF( m ). m ) 97 11

12 Input: a(x), b(x) œ GF( m ), rreducble polynomal f(x) of degree m Output: c(x)=a(x) b(x) mod f(x) 1: c(x) : for = m-1 to do 3: c(x) c(x) x + a(x)b 4: c(x) c(x) + f(x)c m 5: end for 6: return c(x) Algorthm 1: Multplcaton n GF( m ) A multplcaton of a polynomal by a coeffcent (a(x)b ) corresponds to a btwse Boolean AND-functon: a(x)1=a(x); a(x)=. Multplcaton of polynomals by a power of x (a(x) x ) corresponds to a shft-left operaton where the btstrng representaton of the element s shfted postons. Squarng n GF( m ) can ether be calculated by a multplcaton a(x) a(x) mod f(x). Another possblty s to explot the fact that squarng n GF( m ) s a lnear operaton: (a(x)+b(x)) ª a (x)+b (x) mod f(x). Ths allows to square a(x) by calculatng a ( x) = a x = a x. = = Ths corresponds to an nserton of after each bnary coeffcent n the btstrng representaton of a(x). A subsequent modular reducton of the expanded btstrng wll yeld the desred result. The nverse of an GF( m )-element satsfes the equaton a(x) a -1 (x) ª 1 mod f(x). It can ether be calculated wth the Extended Eucldean algorthm for polynomals (see [3]) or by exponentaton: a 1 ( x) a m = ( x) mod f ( x). The calculaton of the Extended Eucldean algorthm ncludes comparng the degree of polynomals. In a hardware mplementaton ths requres addtonal logc resources and complcates the archtecture. Calculatng the nverse by exponentaton reles on multplcaton and squarng as shown n Algorthm. The tme-complexty of Algorthm s determned by the speed of multplcaton. The performance wll usually be slower than those of the Extended Eucldean algorthm but wll not deterorate the overall performance of an EC-operaton because only a sngle nverson s needed when projectve coordnates are used. Input: a(x) œ GF( m ), rreducble polynomal f(x) of degree m Output: c(x)=a -1 (x) mod f(x) 1: c(x) 1 : for = to m- do 3: a(x) a(x) mod f(x) 4: c(x) c(x) a(x) mod f(x) 5: end for 6: return c(x) Algorthm : Inverson n GF( m ) 5 Hardware archtecture The objectve of the PCI-card for acceleratng ECC s to calculate the scalar-multplcaton of ellptc-curve ponts: k P. From sght of the server where the card s plugged n, the card does ths operaton wth affne coordnates. Internally, the calculatons are processed wth projectve coordnates to avod tme-consumng nversons. The output s transformed on the card nto affne coordnates. So the server s software s completely lberated from ECoperatons and has only to manage IO and to calculate a small number of modular nteger operatons to mplement ECC-prmtves lke the dgtal-sgnature algorthm. The PCI-card n use s an off-the-shelf product. The Cesys XCS_EVAL-card [13] conssts manly of two chps. The frst one s an Infneon PITA- PCI-brdge that handles the communcaton wth the PCI bus [14]. It s nterconnected va a mcro-controller nterface wth the second chp, a Xlnx Spartan-II XCS FPGA [15]. The whole functonalty of the EC-processor resdes wthn ths FPGA. Other resources of the board lke SRAM are not used. The overall archtecture of the EC-processor s shown n Fgure. The most promnent part of the archtecture s the arthmetc unt, whch comprehends a hghly parallel GF( m )-multpler and a square unt. The regster-fle s a storage unt for 191-bt ntermedate results and curve parameters. The arthmetc unt and the regster-fle receve ther control sgnals from the ECC-control-unt. Ths unt controls the scalar-multplcaton sequence that s compound of pont addtons und doublngs. A small nterface unt passes nput and output data from the PCI-brdge to the arthmetc unt. Commands and status nformaton s transferred between the PCI-brdge and the ECC-control-unt. 98 1

13 FPGA a(x) b(x) ECC Control Unt Interface Regster Fle Arthmetc Unt 1 muxm m (x) << w muxm M a(x) m (x) a(x) b(x) a(x) + b(x) mod f(x) C << w ^ muxb dn PCI chpset Infneon PITA- dout c(x) Fgure 3: Arthmetc unt 5.1 Datapath Fgure : Hardware archtecture The datapath of the EC-processor conssts of the arthmetc unt and the regster-fle. The communcaton between these two unts s 191-bt wde. 191-bt buses can transfer ntermedate results and curve parameters n a sngle clock cycle. These values are stored n the regster-fle, whch has a capacty of bt words. The capacty s suffcent for all EC-operatons and has a convenent sze for mplementaton wth Xlnx FPGAs. The basc buldng blocks of Xlnx FPGAs are Confgurable Logc Blocks (CLB) that can be confgured as 16x1-bt memory 191 such blocks make the regster-fle. The regster-fle has a read port and a wrte port, whch share a common address decoder. The read port s always actve; the wrte port s actve when the accordng control sgnal s set. A true dualported regster-fle would ncrease the overall throughput unpercevable at the cost of a more complcated control unt. Therefore, ths dea was abandoned. All operatons n the fnte feld GF( m ) are calculated by the arthmetc unt shown n Fgure 3. The arthmetc unt performs a number of operatons: load a(x), hold c(x), add a(x)+c(x) mod f(x), multply a(x) m(x) mod f(x), and square c (x) mod f(x). In addton to these arthmetc operatons, the arthmetc unt also does the IO for the ECprocessor. The arthmetc unt has two 191-bt regsters. Regster C stores the ntermedate result of a calculaton. Ths value serves as 191-bt output of the arthmetc unt and s fed back externally to the nput b(x). The second 191-bt regster M stores the second argument m(x) requred for multplcaton. Ths regster s not drectly accessble from outsde the unt. Further components of the arthmetc unt are a dgtseral multpler, an adder wth an ntegrated modular re- ducton unt, a square unt, two shfters, and three multplexers to select the desred operaton. The arthmetc unt s optmzed for hgh datathroughput. All operatons except multplcaton are executed n a sngle clock cycle. The number of cycles needed for multplcaton depends on the degree of parallelsm of the multpler unt and s dscussed n detal after an analyss of the sngle-cycle operatons. Hold: The smplest sngle-cycle operaton s hold: Ths operaton sustans the value c(x) n regster C. The value c(x) s externally fed back to the nput b(x) and passes through the multplexer muxb to the adder. The adder does not alter the value f the multpler output s. Ths can be acheved by selectng the multpler nput m (x)=. Load: The load-a(x)-operaton s smlar to the hold operaton. The multplexer muxb selects as nput value for the adder to cut off the b(x)-nput. The multpler passes ts nput value a(x) to the adder by selectng m (x)=1. IO. The IO-operaton s bascally a shft-left operaton of regster C where new data s loaded nto the leastsgnfcant bts and the most-sgnfcant bts are dropped. The wordsze of nput and output data s scaleable and s d- bt wde. The regster C s shfted d postons to the left by selectng the rghtmost nput of multplexer muxb (see Fgure 3). The nput dn provdes the lowest d bts. The hghest d bts of regster C are vsble from outsde at the bus dout. Addton. Addton sums up nput a(x) and the content of regster C. Ths s an addton n GF( m ) whch corresponds to an btwse XOR functon. The nput a(x) s passed to the adder n the same way as durng load. The feedback mechansm for the content of regster C s the same as for the hold-operaton. Multplcaton. Multplcaton s a mult-cycle operaton. It s performed n a dgt-seral manner where the mul

14 tplcand a(x) s assgned at full precson and the multpler m(x) s processed n dgts. The wordsze of the dgts s scaleable. So the EC-processor can be optmzed for hgh throughput (.e. 16-bt or 3-bt dgts) or for low gate count (.e. 4-bt dgts). Scalng of the multpler s accomplshed by a resynthess of the HDL source-code. Actually, 8-bt dgts are used whch s a far tradeoff between throughput and gate count (w=8). The resultng radx-56 multpler needs 5 clock cycles to multply 191-bt values. In the frst clock cycle the content of regster C s loaded nto regster M to become the multpler m(x). Durng the next 4 clock cycles m(x) s assgned dgt-after-dgt to the m (x)-nput of the multpler (see Fgure 3). The mostsgnfcant dgt s processed n the frst cycle, the leastsgnfcant n the last cycle. The regster M generates these dgts by shftng ts content n every cycle w postons to the left and assgnng the hghest w bts to the multpler. Durng the whole multplcaton the regster-fle outputs the multplcand a(x). The multpler generates the partal products a(x) m (x), whch are accumulated n regster C. Intermedate results n regster C have to be algned to new partal products. Ths s done by shftng the feedback b(x) w postons to the left before addton wth the new partal product. In the frst clock cycle the feedback s cut off to set regster C to ts ntal value c(x)=. The generaton of a partal product p(x)=a(x) m (x) s shown n Fgure 4 where a GF( 191 )-multpler s depcted. For convenence, a radx-4 verson of the multpler s shown whch lmts m (x) to two nput bts. The partal product p(x) s the sum of two basc partal-products that are generated by maskng the multplcand a(x) wth ANDgates. The addton of these two values s a btwse XORfuncton of the correspondng bts. When the multpler s scaled to acheve hgher throughput, the number of basc partal-products s ncreased. The VHDL model supports scalng wth powers of two, whch effect the most effcent crcuts because the XOR-gates for summng up the partal products can be arranged n a tree structure. Ths guarantees that the crtcal path grows very slowly: O(log #basc_partal_products). m m 1 p 191 a p 19 a 189 p 189 a +1 p +1 a p a p a 1 p 1 p a a 19..a 1 a 191 a 193 a 19 a 11 a 1 a 9 a 8..a 3 a a 1 a a 19..a 1 a 11 a 1 a 9 a 8..a 3 a a 1 a Fgure 5: Modular reducton n GF( 191 ) Modular reducton. Multplcaton and squarng produces ntermedate results that mght be longer than m bts. Therefore, the adder unt has an ntegrated modular reducton unt, whch shortens ntermedate results to m bts. Modular reducton for arbtrary rreducble polynomals wll result n a bulky crcut. Therefore, the modular reducton s optmzed for a dstnct trnomal or pentanomal. Fgure 5 shows the reducton unt for the rreducble polynomal f(x) = x 191 +x 9 +1 whch s used n our GF( 191 )- example. f(x) s a trnomal because t has three terms. The number of terms nfluences the complexty of the reducton unt. The wdth w of the multpler s another parameter for the complexty: The crcut n Fgure 5 shows the reducton unt for w=4 where three bts have to be reduced. The HDL descrpton for the reducton unt can be parameterzed wth any trnomal/pentanomal and any wdth w to customze the hardware quckly for other felds and multpler szes. Squarng. The arthmetc unt has an extra square unt because ths operaton takes only one clock cycle. The square unt resdes n the feedback path of the arthmetc unt. It actually calculates a (x) mod x w-1 f(x) whch s advantageous because the modular reducton unt wll fully reduce ths ntermedate result to a (x) mod f(x). The calculaton s lmted to trnomals or pentanomals (f(x)=x m +x +x j +x k +1). The archtecture of the square unt s shown n Fgure 6. It explots the fact that a(x) can be splt nto two polynomals whch can be squared ndvdually a(x) = a h (x) x (m-1)/ +a l (x). Only the hgher half a h (x) wll be affected by modular reducton. In case of our GF( 191 )- example the square operaton reduces almost to an addton of the expanded halves: a l (x)+a h (x) (x 9 +1). [a a ] = a l (x) a(x) = [a a ] a h (x) = [a a 96 ] ^ ^ << 1 << k << j << a (x) mod x f(x) Fgure 4: GF( 191 )-multpler Fgure 6: Square unt for GF( 191 ) 1 14

15 5. Controlpath The controlpath of the EC-processor spans the ECCcontrol-unt and the nterface unt. The ECC-control-unt sequences the scalar-multplcaton Q=k P of an ellptccurve pont. Ths operaton s smlar to Algorthm 1: It doubles the pont Q n every teraton and condtonally adds the pont P f the actual bt k of the scalar k s set. Intally, Q s set Q =P, whch requres detectng the hghest bt set n k. Doublng and addng of ponts uses a projectve representaton of curve ponts and are non-trval operatons: Pont doublng comprses 4 addtons, 5 square operatons, and 5 multplcatons n GF( m ); Pont addton nvolves 8 addtons, 4 square operatons, and 1 multplcatons. The scalar-multplcaton concludes by convertng the pont Q nto affne coordnates whch nvolves 1 nverson (Algorthm ), 1 square operaton, and multplcatons n GF( m ). All these operatons have to be sequenced by the ECCcontrol-unt. The sequence was optmzed to elmnate dle cycles of the datapath and to mnmze communcaton between the arthmetc unt and the regster-fle. A complete scalar-multplcaton for our GF( 191 )-example takes more than 5, clock cycles when a radx-56 multpler s used. The performance of an EC-processor can easly be jeopardzed by the control logc. A straghtforward mplementaton of the control unt wll surely result n a crcut where the crtcal path of the whole processor s n the control unt. To prevent ths undesred event, the ECC-controlunt s subdvded nto a state machne and a mcroprogram. The state machne s realzed wth mult-level logc and controls major phases of the scalar-multplcaton: Preshftng the scalar k to detect the hghest bt set, the double-andadd teratons, and the fnal projectve-to-affne converson. The mcroprogram generates the control sgnals for multcycle operatons lke pont addton or pont doublng. These operatons are controlled by patterns stored n a ROM table. The mcroprogram also contans control patterns used for IO. IO-operatons can ether transfer an m-bt value from a specfed address of the regster-fle to the arthmetc unt or vce versa. Another IO-operaton ntates a shft operaton of the arthmetc unt where data from the PCI-nterface s shfted n. The mcroprogram contans a 18x1-bt ROM where the patterns are stored and a 7-bt address counter. A 1-bt ROM-word contans bts for sequence control, 5 bts for controllng the regster-fle (4- bt address, 1-bt wrte sgnal), and 3 bts for selectng the desred operaton of the arthmetc unt. The chosen archtecture of the controlpath s an effcent compromse between bulky mult-level logc and a complex but freely programmable mcro-controller. For an FPGA mplementaton ths approach seems to be deal, as ROMs are fast and small, and costly Boolean logc s kept small. 6 PCI nterface and software The Cesys XCS_EVAL-card [13], whch s used as hardware platform, already contans a PCI-brdge. Therefore, t s only necessary that the EC-processor has an nterface to the PCI-chp Pta-II [14]. Ths nterface dstngushes between data transfer and command nvocaton by separate addresses. Data transfer (ether readng or wrtng) ntates an IO-operaton of the processor, whch shfts the content of the arthmetc unt to the left and places nput data at the least-sgnfcant bts. The hghest bts can be retreved by a read operaton. Command nvocaton s lmted to a small number of operatons to keep the software nterface concse. Commands supported by the ellptc processor are summarzed n Table 1. Command Name Operaton AAAA READ Regster C regfle[aaaa] 1AAAA WRITE Regfle[AAAA] regster C I1xxxx MULT Scalar-multplcaton I11xxxx ADD Pont addton Table 1: Command summary The termnaton of a command can ether be determned by pollng the busy flag n the status regster or a software nterrupt s trggered. Interrupt notfcaton s actvated by settng the I-flag durng command nvocaton. Software that uses the PCI-card for acceleratng ECcryptography communcates wth the card va drvers. The card tself s shpped wth an kernel-mode drver for Wndows NT. Ths drver provdes access to the card va the PCI-bus and allows confgurng the FPGA wth a Xlnx btstream that turns the FPGA nto the EC-processor. Furthermore, the drver offers routnes for communcatng wth the FPGA. A dynamc lnk lbrary (DLL) wrtten n C++ uses these routnes to group them to new functons. The new functons are meanngful for wrtng ellptc-curve crypto-prmtves, as they allow multplyng curve ponts by scalars and addng ponts after scalar-multplcaton. For demonstraton and evaluaton purposes we ntegrated the ellptc-curve accelerator n the Java Cryptography Extenson (JCE) mplemented by IAIK [16]. Applcatons based on ths cryptographc toolkt wll be accelerated substantally. If no card s present, the toolkt automatcally uses the slower software mplementaton. Even f such a toolkt s not avalable, the ntegraton of the card s smple as t offers all ellptc-curve specfc functons for mplementng dgtal-sgnature or key-agreement algorthms. The remanng task for the software s to call the DLL routnes and to calculate a few nteger operatons

16 7 Results The EC-processor was modeled wth VHDL. The VHDL-code was wrtten n a style that t s well suted for synthess. Specal care was taken that the regster-fle wll be mplemented as RAM and that the w-bt XOR functon of the multpler wll be syntheszed as a tree structure to keep the crtcal path short. An mportant ssue of the VHDL model s ts scalablty. All parameters, whch are mportant for scalng the ECprocessor for performance (multpler radx) or to optmze t for dfferent fnte felds (feld sze and rreducble polynomal) are adjustable. A re-synthess of the VHDL code wth new parameters wll produce an optmzed hardware n mnutes. Sze m=191 Complexty [LUT] k P [cycles] f max [MHz] k P / MHz w = 8,563 6, ,4 w = 16 6,454* 36, ,3 w = 3 9,881* 4, ,9 Table : Results for dfferent multpler szes Table summarzes the synthess results for dfferent multpler szes. The complexty of the crcut s measured n Look-Up Tables (LUT), whch are the basc elements of Xlnx FPGAs. LUT-values marked wth an astersk ndcate that the crcut s too large to ft the target FPGA Spartan-II XCS. The maxmum clock frequency s 7 MHz. When the card s clocked wth a 66 MHz oscllator, more than 1, scalar-multplcatons can be calculated per second. These fgures already nclude IO. 8 Conclusons The presented PCI-card s a novel soluton to speed up ellptc curve cryptography. Its applcaton n e-commerce wll accelerate dgtal sgnatures and key-agreement algorthms. The hardware realzaton of the ellptc curve processor s based on a medum szed FPGA. The processor s able to calculate the computatonal-ntensve scalar multplcaton of ponts on ellptc curves over the fnte feld GF( m ). Internally, t operates wth projectve coordnates but t even performs the back transformaton to affne coordnates. The processor s optmzed for a partcular fnte feld. The core of ts performance-optmzed arthmetc unt s a dgt-seral multpler. As all other relevant parameters of the crcut, ts degree of parallelsm can be adjusted n the scaleable VHDL model. The current 191-bt verson wth a radx-56 multpler acheves a throughput of 1 scalar-multplcatons per second when clocked at 66 MHz. References [1] R. Posch, G. Karlnger, D. Konrad, A. Lenngen- Westerburg, Th. Menzel: Weßbuch Bürgerkarte (German), A-SIT whte paper, Ma. [] J. Großschädl, G. A. Kamendje, E. Oswald, R. Posch: Ellptc Curve Cryptography n Practce - The Austran Ctzen Card for e-government Applcatons, Proceedngs of the Internatonal Conference on Advances n Infrastructure for Electronc Busness, Educaton, Scence and Medecne on the Internet, Jan.. [3] A. Menezes, P. van Oorschot, S. Vanstone: Handbook of Appled Cryptography, CRC Press, New York, [4] I. Blake, G. Serouss, N. Smart: Ellptc Curves n Cryptography, London Mathematcal Socety Lecture Note Seres, vol. 65, Cambrdge Unversty Press, [5] ANSI X9.6: Publc Key Cryptography for the Fnancal Servces Industry: The Ellptc Curve Dgtal Sgnature Algorthm (ECDSA), [6] ANSI X9.63, Publc Key Cryptography for the Fnancal Servces Industry: The Ellptc Curve Key Transport Protocols, [7] AEP Systems: AEP SSL Accelerator, data sheet, [8] D. Hankerson, J. L. Hernandez, A. Menezes: Software Implementaton of Ellptc Curve Cryptography Over Bnary Felds, Proceedngs of CHES Workshop, Sprnger- Verlag, LNCS 1965,. [9] G. B. Agnew, R. C. Mulln, S. A. Vanstone: An Implementaton of Ellptc Curve Cryptosystems over F 155, IEEE Journal on Selected Areas n Communcatons, Vol. 11, No. 5, Jun [1] J. Goodman, A. P. Chandrakasan; An Energy-Effcent Reconfgurable Publc-Key Cryptography Processor, IEEE Journal of Sold-State Crcuts, Vol. 36, No. 11, Nov. 1. [11] M. Ernst, S. Klupsch, O. Hauck, S. A. Huss: Rapd Prototypng for Hardware Accelerated Ellptc Curve Publc-Key Cryptosystems, 1 th Workshop on Rapd System Prototypng, Monterey, CA, Jun. 1. [1] G. Orlando, Ch. Paar: A Hgh-Performance Reconfgurable Ellptc Curve Processor for GF( m ), Proceedngs of CHES Workshop, Sprnger-Verlag, LNCS 1965,. [13] Cesys GmbH: XCS_EVAL User Manual,User Manual, Verson 1.3, Aug 1. [14] Infneon Technologes: PITA- PCI Interface for Telephony/Data Applcatons, Prelmnary Data Sheet, 1., [15] Xlnx Inc.: Spartan-II FPGA Famly, Prelmnary Product Specfcaton, v.3, Nov 1. [16] IAIK: IAIK JCE-Toolkt, Insttute for Appled Informaton Processng and Communcatons, TU-Graz, jcewww.ak.at. 1 16

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