COMPUTER MEMORY. Volatile memory - loses data when power is off Non-volatile- keeps memory when power is off

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1 Page of 5 COMPUTER MEMORY Volatile memory - loses data when power is off Non-volatile- keeps memory when power is off Non-volatile ROM memory This is pre-programmed ROM memory, which holds data permanently or semi-permanently. Most ROM chips can be programmed by using special techniques, called programmable ROM (PROM) eg A PROM can be programmed only once (One Time Programmable OTP) and is cheap. An EPROM can be erased by UV light exposure and reprogrammed by using a special high voltage programming pin. An EEPROM is electrically erasable and programmable but is expensive. Modern PCs have the BIOS routines held in EEPROM, often called Flash ROMs. New BIOS systems can therefore be downloaded and reprogrammed into Flash ROM BIOS. Volatile Memory RAM All memory in the PC is this type, some is very low power consumption CMOS, which has a battery for keeping its memory. All other type is either:- DRAM- dynamic RAM or SRAM - static RAM DRAM Generally this is cheap, compact, medium speed memory, with memory access times of about 60ns. (data transfers of 6MHz ) Newer DRAM technologies are available and can have memory access times down to 0ns (00MHz) DRAM chip are difficult to interface to the other signals in the PC and require a special DRAM controller chip to handle the process. Data is stored as an electronic charge on a capacitor built into the DRAM cell. An uncharged C represents a logic 0 and a charged C represents a logic. Uncharged capacitors in integrated circuits easily and quickly becomes charged (because of thermally produced electrons in the ic material being 'drawn in' to the DRAM cell area). This means that extra circuitry is required to constantly check the capacitor charge, uncharging regularly any capacitors which are storing logic 0s. This process is carried out by the controller and is called 'DRAM Refresh'. A DRAM Cell The R and C levels go high to switch on the Access transistors. The data logic level can then be transferred to C. When R and C go low the capacitor C is isolated and holds the charge. Row Address (R) Data Read or write All the DRAM cells are created on a matrix, where each cell can be selected by appropriate 'addressing' of the correct Row and Column lines. R C Column Address C Access transistors A DRAM Array Cell 3, 3 Once the column switches have been created each memory bit only needs one row transistor. This makes a compact circuit with one device per memory bit. One Bit- because only one bit is addressed at a time, DRAM array s are layered together to form 4-bit and 8-bit packages. C

2 Page 2 of 5 Two of these chips would be needed to create MB of DRAM Mb Mb Mb Total of M x 4 = 4Mb Total of M x 8 = MB For this reason, upgraded memory sometimes requires adding more than one bank of chips. SIMMs (Single In Line Memory Modules) & DIMMs (Dual In Line Memory Modules) SIMMs and DIMMs are circuit boards with multiple chips to make the upgrade easier. Runs at much higher clock speeds synchronizes itself with the processor bus works in burst mode (see below) A DRAM memory cells holds one bit, but many PC applications use bursts of 4 bit data (one bit followed by the next four bits, one at a time). This is called 'burst mode' and is utilised in all new faster DRAMs. SDRAM is a burst mode device. Multimedia packages need lots of data, usually held in sequential memory locations, so the burst mode device is useful in speeding up the process. The time delay involved in getting burst mode data access is called the 'Latency' e.g. Latency of a typical SDRAM is 5/// [ the number shows the number of cpu clocks cycles ] This means that the st bit takes 5 times longer to access than the 2 nd, 3 rd and 4 th bit. This is because the st bit latency time involves the CPU having to set up the required memory location, before accessing the bit data. Once the memory location is set up, the chip automatically accesses the next 3 sequential bits. SDRAM also has been improved to access 2 addresses at once to speed up operation. Compare Latency with other types: SDRAM 5/// EDO DRAM 5/2/2/2 FPM DRAM 5/3/3/3 DRAM 5/5/5/5 VRAM (Video RAM) Special bu t expensive, fast RAM (25ns) which can be written to and read from simultaneously (also called 'Dual Port RAM') EDO RAM (Enhanced Data Out RAM) Like DRAM but slightly faster. It works by holding a Row address line high and sequential the Column addresses are used to access different locations in the same Row. DDR SDRAM Another improvement in SDRAM technology to improve speed is the 'Double-Data-Rate SDRAM'. The data retrieval in SDRAM is initiated by a rising clock edge (each rising clock edge finds a new bit of data) In DDR DRAM both the rising and the falling clock edge initiates a data read or write. This doubles the speed of operation. SDRAM (Synchronous DRAM)

3 Page 3 of 5 RDRAM Direct Rambus DRAM. This is an entirely new technology [having its own built-in clock] based on a bus system rather than the traditional memory access systems. The first cpu cycle has the same latency as other systems but the Rambus chip runs at a high internal clock rate to produce many memory cell accesses during each cpu cycle. It is anticipated that Rambus memory access time might be as low as 0.6ns after further development, bringing it up to cpu Cache memory speed. General Things about Memory Chips Banks Single or double-in-line memory modules (SIMMs or DIMMs) are fitted to a PC. The DIMMs have a data width twice that of the SIMMs. It is important to know the width of the data bus used in the PC and the data width of the SIMM (or DIMM) before upgrading the memory. A cpu with a 32-bit data bus uses a memory bank which is also 32-bits wide. e.g. if the cpu data bus is 64-bits and the SIMM you are fitting is 32-bits, you will need to fit 2 SIMMs to complete the upgrade. The 2 SIMMs will work together to give a 64-bit piece of data when accessed by the cpu. DIMMs [which have 68 pins] have 64-bit data widths and therefore a single DIMM can be used as an upgrade to a 64-bit system like a Pentium III SPD - Serial presence Detect DIMMs contain more than just DRAM memory chips, they also contain data stored in a small onboard ROM chip which describes the structure of the DIMM in terms of speed and. This data is automatically detected by the POST when new DIMMs are added and the PC is rebooted. The data is sent serially via the SPD data pin on the DIMM to the PC. Presence Detect is also used on SIMMs but it is direct parallel detection via 5 pins which are either grounded or not, to indicate a series of different size and speed values. Memory modules can be either unbuffered or buffered, but PCs only use unbuffered types to increase speed Voltage supply can be 3.3 V of 5 V ( most are 3.3 V types) Fortunately special keys are cut out from the SIMM/DIMM modules to prevent accident insertion of the wrong type of buffering or voltage into a motherboard. Memory Speed Memory chip speed is usually defined by its access time (e.g. 60ns) but take care of the following: if the PC needs a DRAM of 60ns, you can use a DRAM with a speed of 60ns or faster (e.g. 50ns is ok but 80ns is not ok) an SDRAM for a PC processor bus running at 00MHz would need a chip with a slightly faster access time than that indicated by taking the reciprocal of the bus speed i.e. /00MHz = 0ns SRAM Static RAM is usually used in Cache memory circuits because of its fast access speed, 2 to 0ns. (Data transfers up to 500MHz). SRAM chips are more complex than DRAMs and take up more silicon die area. For this reason they cannot be as densely packed onto a chip as DRAM. Each SRAM memory cell needs 4 access transistors. All these reasons result in SRAM (cache) memory being much more expensive than equivalent DRAM chips. However SRAM cells are very stable and do not require refreshing circuitry, which means they are easy to use and interface with the PC circuits. Flip-Flop The heart of the SRAM as a simple flip-flop circuit (or bistable) much like a simple version of the SR flip flop. When the input is held momentarily at logic, the state is stored and the stable state is reinforced by feedback from a cross-coupled logic gate. See below. SIMMs/DIMMs/RIMMs types

4 Page 4 of 5 The Standard SRAM Cell 5v i/p= 0v 5V Q=0 What is a memory cache? It is a block of SRAM (often 256 kb or 52 kb) which built into the CPU (L and L2) or on the motherboard L3 (sometimes L2). It is accessed before the slower DRAM (main memory). Whenever a the cpu needs to read or write to a memory location (usually reading program instructions) the cache is investigated first to see if the data is available there. If the data is found it is called a 'cache hit' and is transferred to the cpu. When the cpu is busy processing the data (or when it is idle) the cache memory is loaded with many of the bytes of data found at addresses close to the last one accessed. In this way it is more likely that the next required piece of data will be found in the cache, resulting in another cache hit. Data RAM chips usually have smaller capacity than DRAMs and their data output per chip is often arranged to be 4-bit or 8bit ( byte ) wide. e.g. The 5258 chip is arranged as a 64k x 4bit, which means that it holds 64k of addresses (65536) each storing 4 bits at once. This requires 6 address lines (2 6 =64k) It has 24 pins in total. 6 pins for addressing-- A0 to A5 4 pins for data --D0 to D3 pin for read/write--r/w' 2 pins for power supply --Vcc and GND pin for chip select (enable) -- CS' SRAM memory cache size is often limited to 256kB, 52kB or MB owing to the cost. Cache Memory All PC systems operate a 'cache memory' system which is always SRAM and therefore fast (but expensive). 0 The control of all this activity is the responsibility of the cache controller. If the data is not found in the cache then a 'cache miss' occurs and the controller transfers the request to the DRAM. When the DRAM data is found (which, being slow, causes the cpu to wait - inserting 'wait cycles' into the request cycle ) a copy of the DRAM data and neighbouring data is made in the cache before it is passed back to the cpu. A cache system can cause large increases in performance especially if the cpu requests data in sequential memory locations. Its success depends on the probability of a cache hit and is therefore dependent on the cache controller predicting the next block of memory locations correctly. Cache consistency Whenever data is being held in 2 places at once it is vital that that a memory update is performed to both places. The cache controller handles this and maintains the correct data is stored. This duplication of correct information is called Cache consistency. Obviously cache consistency is maintained at times when the cpu is idle, otherwise copying cache data to DRAM would slow operations down.

5 Page 5 of 5 Tutorial on Computer Memory. What is a typical access time for (i) Dram (ii) Sram devices? 2. What does the D of Dram stand for? What does it mean? 3. Upgrading memory from 6MB to 32MB means adding more of which type of memory? 4. Increasing Cache memory means adding more of which type of memory? 5. Draw a simple Dram cell and briefly explain how data is stored and read back from the cell. 6. What is a SIMM, a DIMM and a SODIMM? 7. What is refresh circuitry needed for? 8. How many address pins are needed for 56kB Sram chip? 9. What is the main function of a Dram controller? 0. What is EDORAM, VRAM, EEPROM, and PROM?. What does S of Sram mean and why is it so named? 2. What does S of Sdram mean and why is it so named? 3. Why are Srams a smaller memory capacity than Drams? 4. Why do Srams have more pins on the package than Drams? 5. Briefly explain what Cache memory is used for. 6. What is the difference between level and level 2 Cache? 7. What is a Cache hit and a Cache miss? 8. What sort of program would benefit the most from an increase in Cache memory? 9. What is Cache consistency? 20. What does volatile memory mean? 2. Draw the circuit of the bistable cell used in an Sram chip (a) using 2 NOT gates (b) using MOSFET devices What are wait cycles and why are they used? 22. What is latency 23. Three Dram chips are described in a catalogue as (a) 4M x 6 (b) 64M x72 (c) 6M x 64. How many bit and bytes of data can they each store? 24. What does access time mean? 25. What is flash memory and where is it used?