FYS4260/FYS9260: Microsystems and Electronics Packaging and Interconnect. Components

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1 FYS4260/FYS9260: Microsystems and Electronics Packaging and Interconnect Components

2 Topics Introduce descriptions of geometrical, thermal and some electrical properties of main types of components. No description of electrical properties of integrated circuits.

3 Types of general purpose fixed resistors Examples of general purpose fixed resistors Type Carbon Metal film Wirewound Surface mount Tolerance 2-10% (5%) 0.1-5% (1%) 0.1-5% (1%) 0.1-5% (1%) Power rating W (¼W) 0.1-5W (¼W) 1-200W (10W) W (0.1W) Temp. coefficient ppm/k (450) ppm/k (50) ppm/k (50) ppm/k (100) Table 2: Examples of general purpose fixed resistors with typical ranges for tolerance, power rating and temperature coefficient of resitance. Typical value in bold. FYS4260/FYS9260 Frode Strisland 3

4 Hole Mounted Resistors Mature design, fig. 4.1: Carbon composite (a) Metal film (b) Wire wound (c)

5 Surface Mounted Resistors Fig.4.2.a: Thick film layers on ceramic substrate, rectangular shape Slide 5

6 Surface Mounted Resistors Fig. 4.2 b): Metal system for termination on SMD resistors. Slide 6

7 Surface Mounted Resistors Table 4.1. Properties of SMD resistors (Philips). Resistance range and tolerance ohm to 1 Mohm (E24* series) ± 2% Table 4.1: Properties of10 SMD 1 ohm to 10resistors Mohm (E24 series) ± 5% 1 ohm to 10 Mohm (E12 series) ±10% Dimensions 3,2 x 1,6 x 0,6 mm Operating temperature range -55 C to C Temperature coefficient (-40 C to 125 C) <+200 x 10-6/K Absolute max. dissipation at Tamb= 70 C 0,25 W Maximum permissible voltage 200 V (r.m.s.) Climatic category (IEC68) 55/155/56 Jumper resistance = 50 mohm Maximum current 2A *See Table 4.2 Slide 7

8 Surface Mounted Resistors Table. 4.2: The resistance series E24, E12 and E6. The numbers mean that for example in series E6 there are 6 resistance values for each decade: 10, Table 15, 4.2: 22, 33, The 47 and resistance 68 x10 n ohms. series E24, 12 and 6 E E E Slide 8

9 Surface Mounted Components Coding of component sizes Still very common to define sizes in fractions of inches, e.g. For example: 0603 = 0.06inch x 0.03 inch = 60mils x 30 mils = (1.6 mm 0.8 mm) mils 30 mils A word of warning: Some locations use a similar, metric system FYS4260/FYS9260 Frode Strisland 9

10 Dimensions of Surface Mount Passives. Power rating of resistors Code Length (l) Width (w) Height (h) Power Imperial Metric inch mm inch mm inch mm Watt /20 (0.05) /16 (0.062) /10 (0.10) /8 (0.125) /4 (0.25) /2 (0.50) /4 (0.75) FYS4260/FYS9260 Frode Strisland 10

11 Hole Mounted Resistors Coding: Color Value Multiplier Tolerance (%) Black Brown 1 1 ±1 Red 2 2 ±2 Orange 3 3 ±0.05 Yellow Green 5 5 ±0.5 Blue 6 6 ±0.25 Violet 7 7 ±0.1 Gray White Gold - -1 ±5 Silver - -2 ±10 None - - ±20 Slide 11

12 Tolerances Components of different tolerances are often picked according to value from the same production. +/- 1% What you might get if you use +/- 10% components R o FYS4260/FYS9260 Frode Strisland 12

13 Capacitors In addition the capacitance, the following properties are important: Maximum voltage rating Temperature dependence of the capacitance (temperature coefficient) Loss tangent (tan δ) Equivalent series resistance Long term stability and ageing phenomena High frequency properties Leakage current Ability to withstand various production processes (high temperature, etc.) Price, physical size, etc. Web: Slide 13

14 Capacitors, continued Main types: Ceramic multilayer Electrolytic dry, polarized Electrolytic, wet, polarized Metallized plastic film Mica Slide 14

15 Capacitors, continued Electrical model: C = (ε o ε r A) /d Z = [ R s 2 + (ωl - 1/ωC) 2 ] 1/2 C A = electrode area d= electrode distance R s = series resistance (R p neglected), L = inductance, fig. 4.5 Resonance frequency will be when: ωl = 1/ωC L R s C Rp Loss tangent: tan δ = R / Im Z = { R p + R s [1+ (ωcr p ) 2 ]} / [ ωcr p 2 - ω L (1+ (ωcr p ) 2 ] Slide 15

16 Fig. 4.3: Electrical equivalent model for capacitor. If R p can be neglected the impedance is given by: Capacitors, continued Rp L R s C Z = [R s 2 + (ωl - 1/ωC) 2 ] 1/2 Fig. 4.4: The frequency dependence of impedance for multilayer ceramic capacitors (lower curve) and tantalum electrolytic capacitors (upper curve), all having 100 nf capacitance value. Slide 16

17 Capacitors, continued Fig. 4.5: Frequency dependence of the loss tangent tan δ schematically. tan δ = R / Im Z = [R p + R s ( 1+ ( ωcr p ) 2 ) ] / ( ωcr p 2 - ω L (1+ ( ωcr p ) 2 ) ] Slide 17

18 Multilayer Ceramic Capacitors Capacitors, continued Fig. 4.7.a: SMD Multilayer Ceramic Capacitor Fig. 4.7.b: Metal system for the end termination of multilayer ceramic capacitors. Slide 18

19 Multilayer Ceramic Capacitor Buildup Detailed construction of a multilayer ceramic chip capacitor (MLCC). 1. Ceramic dielectric, 2. Ceramic or lacquered coating, 3. Metallized electrode, 4. Connecting terminals "MLCC-Structure-Details" by Elcap, Jens Both, SVG-Version: Hk kng - based on de:bild:mlcc- Aufbau-detailliert.png. Licensed under CC BY-SA 3.0 via Wikimedia Commons - Structure-Details.svg FYS4260/FYS9260 Frode Strisland 19

20 Multilayer Ceramic Capacitor, continued Class 1: Low capacitance, good electrical properties, types NP0, N220, N750, COG, etc. Class 2: High capacitance, poorer electrical behaviour, types X7R, Z5U Fig. 4.8: Relative dielectric constant for ferroelectric ceramic compositions (class 2), as a function of temperature, near the Curie point Slide 20

21 Multilayer Ceramic Capacitors, continued Fig. 4.9: Properties of dielectrics of the types NP0, X7R and Z5U in SMD ceramic multilayer capacitors. Top: The voltage dependence of capacitance. Middle: Loss tangent as function of temperature. Bottom: The temperature coefficient of the capacitance (Philips). Slide 21

22 Take home message: A capacitor is not always the capacitor you think it is: Check ratings and intended usage before selecting component. FYS4260/FYS9260 Frode Strisland 22

23 Multilayer Ceramic Capacitors, continued Fig. 4.10: Crack formation because of thermal stress in ceramic capacitors Slide 23

24 Electrolytic capacitors Electrolytic capacitors uses a metal oxide as dielectric Electrolytic capacitors are polarized they can only be biased one way The anode electrode (+) consist of a metal on which an insulating oxide layer acting as the dielectric. The has been fromed by anodization A non-solid or solid electrolyte which covers the surface of the oxide layer in principle serves as the second electrode (cathode) (-) of the capacitor. FYS4260/FYS9260 Frode Strisland 24

25 Tantalum dry electrolytic capacitor A tantalum electrolytic capacitor is an electrolytic capacitor, a passive component of electronic circuits. It consists of a pellet of tantalum metal as anode, covered by an insulating oxide layer that forms the dielectric, surrounded by liquid or solid electrolyte as a cathode. The tantalum capacitor distinguishes itself from other capacitors in having high capacitance per volume and weight. Tantalum capacitors have lower equivalent series resistance (ESR), lower leakage, and higher operating temperature than other electrolytic capacitors, although other types of capacitors are even better in these regards. Tantalum capacitors are more expensive than other commonly used type of capacitor, so they are used only in applications where the small size or better performance are important. "Tantalum-SMD-Chip-Molded" by Elcap - Own work. Licensed under CC0 via Wikimedia Commons - Molded.jpg#mediaviewer/File:Tantalum-SMD-Chip-Molded.jpg FYS4260/FYS9260 Frode Strisland 25

26 Capacitors, continued Electrolytic Capacitors why they are polarised: The capacitance is the oxidised surface of the anode Reversed polarity will remove the oxide by reduction reaction at the anode and loss of dielectric isolation leading to short-circuiting Fig a): Tantalum SMD electrolytic capacitor (Philips), and hole mounted tantalum capacitors (Siemens) Slide 26

27 Tantalum, Dry Electrolytic Capacitors, continued Dissipation factors vary with temperature: Maximum values which are not exceeded by any capacitor are as follows. Temperature -55 C 25 C 85 C 125 C Rated Voltage 4 to 10 V d.c. 10% 12% 12% 12% Rated Voltage 15 to 50 V d.c. 8% 6% 6% 6% The d.c. leakage current (at rated voltage) is within the limit set below 25 C < 0,01 µa/µf V or < 1 µa whichever is greater 85 C < 0,10 µa/µf V or < 10 µa whichever is greater 125 C < 0,125 µa/µf V or < 12,5 µa whichever is greater Fig b): Electrical properties of dry tantalum electrolytic capacitors. (Data from Philips) Slide 27

28 Aluminum wet electrolytic capacitor An aluminum electrolytic capacitor with a non-solid electrolyte always consists of two aluminum foils separated mechanically by a spacer, mostly paper, which is saturated with a liquid or gel-like electrolyte. One of the aluminum foils, the anode, is etched (roughened) to increase the surface and oxidized (formed). The second aluminum foil, called the "cathode foil", serves to make electrical contact with the electrolyte. A paper spacer mechanically separates the foils to avoid direct metallic contact. Both foils and the spacer are wound and the winding is impregnated with liquid electrolyte. Multiple electrolytes are used. Further reading: Wikipedia "Al-e-cap-construction" by Elcap - Own work. Licensed under CC0 via Wikimedia Commons - FYS4260/FYS9260 Frode Strisland 28

29 Diodes and Transistors Fig. 4.13: Axial, plastic encapsulated, hole mounted diodes to the left. Right: A plastic can with metal base for power diodes. It can be hole mounted or surface mounted, depending on how the leads are bent. The base is screwed to the substrate. Slide 29

30 Diodes and Transistors, continued Fig. 4.14: Various types of hole mounted transistor packages: a) Left: Plastic packages, b) Centre: Low power metal packages c) Right: Metal package for high power transistors. For the high power package, the collector is connected to the metal body. Slide 30

31 Diodes and Transistors, continued Fig. 4.16: SOT-packages for SMD diodes and transistors: The most common, SOT-23 top left, SOT-89 for power transistors in the middle, and SOT-143 with four terminals to the right. The dimensions for SOT-23 are shown bottom left, and a cut-through SOT-89 in the middle. Ceramic SMD transistor packages with terminal placement like for SOT-23 are shown bottom right. Slide 31

32 IC Packages Plastic or Ceramic IC Packages? Plastic: Not hermetic Low price in large quantities High initial cost Low thermal conductivity Limited time at high temperature Thermal mismatch to Si chip and metals Not suitable for high frequency circuits Ceramic: Hermetic, good reliability Costly, but OK for prototyping Good thermal conductivity Low thermal coefficient of expansion, matches well with Si, mismatch to organic substrates Gold metallization must be removed Well defined high frequency properties Slide 32

33 Packages for Hole Mounted ICs Fig. 4.17:a) DIP (Dual-in-line) IC package. b) Partly cross-sectioned DIP package which shows the silicon chip, bonding wires, lead frame and plastic body. c) The terminal organisation for 4 two-input NOR gates in a 14 pins package. Electronic Pack.. Chapter 4 Components for Electronic Systems Slide 33

34 Packages for Hole Mounted ICs, continued Fig. 4.18: Pin grid packages: To the left a cavity up ceramic package, and to the right a plastic moulded package. Slide 34

35 SMD IC Packages Small Outline (SO) Plastic Leaded Chip Carrier (PLCC) Leadless Chip Carrier (LLCC) Leaded Ceramic Chip Carrier (LDCC) Flatpack, mini-flatpack TapePak Chip Scale Packages Slide 35

36 Surface Mount Plastic Package types Malestrom: Printed Circuits Handbook 6ed FYS4260/FYS9260 Frode Strisland 36

37 SMD IC Packages, continued Fig. 4.19: Surface mounted SO (Small Outline) IC package. (From Philips) Slide 37

38 Outline Encapsulation Maximum width SMD IC Packages, continued SO Maximum width Maximum length Lead end to lead end [mm] [mm] [mm] SO-8 4,0 5,00 6,2 SO-8 7,6 7,6 12,4 SO-14 4,0 8,75 6,2 SO-16 4,0 10,00 6,2 SO-16L 7,6 10,5 10,65 SO-20 7,6 13,0 10,65 SO-24 7,6 15,6 10,65 SO-28 7,6 18,1 10,65 VLO-40 7,6 15,5 12,8 VSO-56 11,1 21,6 15,8 Table 4.3: Dimensions for SO- and VSO packages. Centre-to-centre lead distance is normally 50 mils, except for VSO-40 with 30 mils and VSO-56 with 0.75 mm. Slide 38

39 SMD IC Packages: Plastic Leaded Chip Carrier (PLCC) Fig. 4.20: Plastic leaded chip carrier with (PLCC). They are normally square with an equal number of terminals on all four sides (top). For large DRAMs, the package has terminals on only two sides, also being called SOJ. The bottom figure shows a 1 or 4 Mbit DRAM package. Slide 39

40 SMD IC Packages: Plastic Leaded Chip Carrier (PLCC) Leads Format Lead pitch Maximum body dimensions [AxB] [mm] Maximum Device Dimensions (LxW) [mm] Typical Height (C) [mm] [mm] 20 5x5 1,27 9,1x9,1 10,1x10,1 3,5-4,7 28 7x7 1,27 11,6x11,6 12,6x12,6 3,5-4, x11 1,27 16,8x16,8 17,8x17,8 3,5-4, x13 1,27 19,3x19,3 20,3x20,3 3,5-4, x17 1,27 24,4x24,4 25,4x25,4 3,5-4,7 18 5x4 1,27 10,9x7,5 11,9x8,5 3,5-4,7 28 9x5 1,27 14,1x9,0 15,1x10,0 3,5-4,7 32 9x7 1,27 14,1x11,6 15,1x12,6 3,5-4,7 Table 4.4: Dimensions for PLCC packages. Format means the number of terminals on two neighbouring sides. Slide 40

41 Leadless Chip Carrier (LLCC) Leaded Ceramic Chip Carrier (LDCC) Fig a): The various types of ceramic chip carriers [4.15]. Types A -D to the left are leadless (LLCC), whereas types A and B to the right are meant for mounting leads (LDCC). Slide 41

42 Image Description Image Description Image Description CBGA - Ceramic Ball Grid Array MQFP - Metric Quad Flat Package PQFP - Plastic Quad Flat Pack CCGA - Ceramic Column Grid Array CerDIP - Ceramic Dual-in-Line Package CerPack - Ceramic Package CLCC - Ceramic Leadless Chip Carrier MSOP - Micro Small Outline Package PBGA - Plastic Ball Grid Array PDIP - Plastic Dual-in-Line Package PLCC - Plastic Leaded Chip Carrier PSOP - Power Small Outline Package QFN - Quad Flat No Leads Package QSOP - Quarter Size Outline Package SBDIP - Sidebraze Dual-in-Line Package CPGA - Ceramic Pin Grid Array PPGA - Plastic Pin Grid Array SC-70 - Small Outline Transistor CQFP - Ceramic Quad Flat Pack D2PAK or DDPAK - Dou-ble Decawatt Package PQFN - Power Quad Flat No Leads Package TFBGA - Thin Fine-Pitch Ball Grid Array SIP - Single-In-Line Package SOIC - Small Outline IC Package FYS4260/FYS9260 Frode Strisland 42

43 DFN - Dual Flat No Leads Package DPAK - Decawatt Package FBGA - Fine- Pitch Ball Grid Array JLCC - J-Leaded Ceramic Chip Carrier LFBGA - Low Profile Fine-Pitch Ball Grid Array LGA - Land Grid Array LQFP - Low- Profile Quad Flat Package MLP - Micro Leadframe Package TQFP - Thin Quad Flat Pack TSOP - Thin Small Outline Package TSSOP - Thin Shrink Small Outline Package UTDFN - Ultra Thin Dual Flat No Leads Package UTQFN - Ultra Thin Quad Flat No Leads Package VFBGA - Very Thin Fine-Pitch Ball Grid Array PQFP - Plastic Quad Flat Pack PSOP - Power Small Outline Package SOT-23 - Small Outline Transistor SPDIP - Shrink Plastic Dual-in-Line Package SSOP - Shrink Small Outline Package TDFN - Thin Dual Flat No Leads Package TFBGA - Thin Fine- Pitch Ball Grid Array VSOP - Very Small Outline Package XDFN - Extreme Thin Dual Flat No Leads Package XQFN - Extreme Thin Quad Flat No Leads Package FYS4260/FYS9260 Frode Strisland 43

44 Leadless Chip Carrier (LLCC) Fig b): LLCC packages, additional details. The longest terminal is to designate electrical terminal number 1 in the circuit. Slide 44

45 Leadless Chip Carrier (LLCC), continued Leads Format Pad Pitch (p) [mm] Maximum Dimension (AxB) [mm] 20 5x5 1,27 9,1x9,1 28 7x7 1,27 11,6x11, x11 1,27 16,8x16, x13 1,27 19,3x19, x17 1,27 24,4x24, x21 1,27 29,6x29,6 18 5x4 1,27 10,9x7,5 28 9x5 1,27 14,1x9,0 32 9x7 1,27 14,1x11,6 Table 4.5. LLCCs, dimensions. Slide 45

46 Leaded Ceramic Chip Carrier (LDCC) Fig. 4.22: Leaded ceramic chip carriers. Slide 46

47 Leaded Ceramic Chip Carrier (LDCC), continued Fig. 4.23: Various shapes of the leads, and leadless termination for comparison. Slide 47

48 Flatpacks Fig. 4.24: Quad flatpack with leads on all four sides. Flatpacks are usually made of plastic or ceramic. They have leads on four or two sides. Slide 48

49 Mini-flatpacks Fig. 4.25: Mini-flatpacks is a name for higher density flatpacks: Typically terminals and a pitch of 25 mils. Slide 49

50 High Performance Packages Multilayer ceramic, Al 2 O 3 or AlN Ground planes Controlled characteristic impedance Thermal vias Slide 50

51 High Performance Packages Fig. 4.27: Thermal via-holes in the printed circuit board, for better heat conduction. Slide 51

52 High Performance Packages, continued Fig. 4.29: Multichip package for memory module in a Hitachi high-performance computer [4.18]. The module contains 6 ECL chips, mounted by flip chip. Slide 52

53 MEMS packaging differ from IC packaging: Includes an interface to the environment Contains delicate structures sensitive to mechanical stress Often combination of MEMS element and ASIC in single package Packaging often an integral part of the device operation, for example in a hearing aid or an implantable device Differential pressure sensor FYS4260/FYS9260 Frode Strisland 53

54 Electrostatic Discharges (ESD) Unprotected MOS: Max 5-80 V on input before destroyed Triboelectricity: >>1000 V discharge Billions of $ damage annually Protected circuits tolerate V Extensive precautions in industry, handling and packing Slide 54

55 Electrostatic Discharges Component Damages and Precautions Fig. 4.33: MOS transistor schematically. The gate oxide is very vulnerable for damage by electrostatic discharge. Gate oxides down below 200 Å (20 nm) are now used. Slide 55

56 Electrostatic Discharges - Component Damages and Precautions, continued Fig. 4.34: CMOS circuit exposed to electrostatic damage: Silicon has molten in a small area. Picture size 5µm x 5µm. Slide 56

57 Component Packaging Paper tape (hole mounted passives) Blister tape (SMD passives, discretes, small ICs) Sticks (DIPs, SMD ICs) Waffle trays (Flatpacks) Stack magazine Bulk: Not suited for automatic mounting Slide 57

58 Component Packaging for Automatic Placement Fig. 4.36: Blister tape for surface mounted components. Standard dimensions for 8 mm wide tape. Slide 58

59 Component Packaging for Automatic Placement Fig. 4.37: Plastic sticks as packaging for SMD integrated circuits. Slide 59

60 Component Packaging for Automatic Placement Fig. 4.38: Waffle trays packaging for flatpacks to the left, frame for stacking of single component to the right. Slide 60

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