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1 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR HIGH SPEED : f MAX = 80MHz (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC =2µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: I OH = I OL = 4mA (MIN) BALANCED PROPAGATION DELAYS: t PLH t PHL WIDE OPERATING VOLTAGE RANGE: V CC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 73 DESCRIPTION The M74HC73 is an high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated with silicon gate C 2 MOS technology. Depending on the logic level applied to J and K inputs, this device changes state on the negative going traition of clock input pulse (CK). The PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES TSSOP PACKAGE TUBE T & R DIP M74HC73B1R SOP M74HC73M1R M74HC73RM13TR TSSOP M74HC73TTR clear function is accomplished independently of the clock condition when the clear input (CLR) is taken low. All inputs are equipped with protection circuits agait static discharge and traient excess voltage. DIP SOP August /11
2 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION TRUTH TABLE X : Don t Care LOGIC DIAGRAM INPUTS PIN No SYMBOL NAME AND FUNCTION 1, 5 1CK, 2CK Clock Input 2, 6 Asynchronous Reset 1CLR, 2CLR Inputs 12, 9 1Q, 2Q True Flip-Flop Outputs 13, 8 1Q, 2Q Complement Flip-Flop Outputs 14, 7, 3, 10 1J, 2J, 1K, 2K Synchronous Inputs Flip-Flop 1 and 2 11 GND Ground (0V) 4 Vcc Positive Supply Voltage OUTPUTS CLR J K CK Q Q FUNCTION L X X X L H CLEAR H L L Q n Q n NO CHANGE H L H L H ---- H H L H L ---- H H H Q n Q n TOGGLE H X X Q n Q n NO CHANGE 2/11
3 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V CC Supply Voltage -0.5 to +7 V V I DC Input Voltage -0.5 to V CC V V O DC Output Voltage -0.5 to V CC V I IK DC Input Diode Current ± 20 ma I OK DC Output Diode Current ± 20 ma I O DC Output Current ± 25 ma I CC or I GND DC V CC or Ground Current ± 50 ma P D Power Dissipation 500(*) mw T stg Storage Temperature -65 to +150 C T L Lead Temperature (10 sec) 300 C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditio is not implied (*) 500mW at 65 C; derate to 300mW by 10mW/ C from 65 C to 85 C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit V CC Supply Voltage 2 to 6 V V I Input Voltage 0 to V CC V V O Output Voltage 0 to V CC V T op Operating Temperature -55 to 125 C t r, t f V CC = 4.5V 0 to 500 Input Rise and Fall Time V CC = 2.0V 0 to 1000 V CC = 6.0V 0 to 400 3/11
4 DC SPECIFICATIONS Test Condition Value Symbol V IH V IL V OH V OL I I I CC Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current V CC (V) T A = 25 C -40 to 85 C -55 to 125 C Min. Typ. Max. Min. Max. Min. Max I O =-20 µa I O =-20 µa I O =-20 µa I O =-4.0 ma I O =-5.2 ma I O =20 µa I O =20 µa I O =20 µa I O =4.0 ma I O =5.2 ma V I = V CC or GND ± 0.1 ± 1 ± 1 µa 6.0 V I = V CC or GND µa Unit V V V V 4/11
5 AC ELECTRICAL CHARACTERISTICS (C L = 50 pf, Input t r = t f = 6) Test Condition Value Symbol t TLH t THL t PLH t PHL t PLH t PHL f MAX t W(H) t W(L) t W(L) t s t h t REM Parameter Output Traition Time Propagation Delay Time (CK - Q) Propagation Delay Time (CLR - Q) Maximum Clock Frequency Minimum Pulse Width (CK) Minimum Pulse Width (CLR) Minimum Set-up Time Minimum Hold Time Minimum Removal Time V CC (V) CAPACITIVE CHARACTERISTICS T A = 25 C -40 to 85 C -55 to 125 C Min. Typ. Max. Min. Max. Min. Max Test Condition 1) C PD is defined as the value of the IC s internal equivalent capacitance which is calculated from the operating current coumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC /2 (per FLIP/ FLOP) Value Symbol Parameter V CC T A = 25 C -40 to 85 C -55 to 125 C Unit (V) Min. Typ. Max. Min. Max. Min. Max. C IN Input Capacitance pf C PD Power Dissipation Capacitance (note pf 1) Unit MHz 5/11
6 TEST CIRCUIT C L = 50pF or equivalent (includes jig and probe capacitance) R T = Z OUT of pulse generator (typically 50Ω) WAVEFORM 1: MINIMUM REMOVAL TIME (f=1mhz; 50% duty cycle) 6/11
7 WAVEFORM 2 : MINIMUM PULSE WIDTH, PROPAGATION DELAY TIME (f=1mhz; 50% duty cycle) WAVEFORM 3 : PROPAGATION DELAY TIME, MINIMUM PULSE WIDTH, SETUP AND HOLD TIME (f=1mhz; 50% duty cycle) 7/11
8 Plastic DIP-14 MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. a B b b D E e e F I L Z P001A 8/11
9 SO-14 MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A a a b b C c1 45 (typ.) D E e e F G L M S 8 (max.) PO13G 9/11
10 TSSOP14 MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A A A b c D E E e 0.65 BSC BSC K L A A2 A1 b e D c K L E E1 PIN 1 IDENTIFICATION D 10/11
11 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no respoibility for the coequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licee is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificatio mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom 11/11
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