MC14001B Series B-Suffix Series CMOS Gates

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1 MCB Series B-Suffix Series CMOS Gates MCB, MCB, MCB, MCB, MCB, MCB, MCB, MCB The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired. Features Supply Voltage Range =. to All Outputs Buffered Capable of Driving Two Lowpower TTL Loads or One Lowpower Schottky TTL Load Over the Rated Temperature Range. Double Diode Protection on All Inputs Except: Triple Diode Protection on MCB and MCB PinforPin Replacements for Corresponding CD Series B Suffix Devices NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AECQ Qualified and PPAP Capable These Devices are PbFree and are RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to ) Symbol Parameter Value Unit DC Supply Voltage Range. to +. V V in, V out Input or Output Voltage Range (DC or Transient). to +. V I in, I out P D Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note ) ± ma mw T A Ambient Temperature Range to + C T stg Storage Temperature Range 6 to + C T L V ESD Lead Temperature (Second Soldering) ESD Withstand Voltage Human Body Model Machine Model Charged Device Model 6 C > > N/A Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. Temperature Derating: D/DW Packages:. mw/ C From 6 C To C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V in and V out should be constrained to the range (V in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. V SOIC D SUFFIX CASE A Device MCB MCB MCB MCB MCB TSSOP DT SUFFIX CASE G MARKING DIAGRAMS xxbg AWLYWW xx A WL, L YY, Y WW, W G or MCB MCB MCB SOIC xxb ALYW DEVICE INFORMATION Description Quad Input NOR Gate Quad Input NAND Gate Triple Input NAND Gate Triple Input NOR Gate Quad Input OR Gate TSSOP = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = PbFree Package (Note: Microdot may be in either location) Triple Input AND Gate Quad Input AND Gate Dual Input AND Gate ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Semiconductor Components Industries, LLC, July, Rev. Publication Order Number: MCB/D

2 MCB Series LOGIC DIAGRAMS NOR NAND OR AND MCB Quad Input NOR Gate MCB Quad Input NAND Gate MCB Quad Input OR Gate MCB Quad Input AND Gate INPUT MCB Triple Input NOR Gate MCB Triple Input NAND Gate MCB Triple Input AND Gate MCB Dual Input AND Gate INPUT 6 MCB Quad Input NOR Gate 6 MCB Quad Input NAND Gate PIN ASSIGNMENTS 6 MCB Triple Input NAND Gate = PIN = PIN FOR ALL DEVICES NC = 6, MCB Triple Input NOR Gate IN A IN A IN D IN A IN A IN D IN A IN A IN C IN A IN A OUT A IN D OUT A IN D IN B IN C IN B OUT B OUT D OUT B OUT D IN B IN C IN B IN B OUT C IN B OUT C IN B OUT C IN B IN B 6 IN C IN B 6 IN C OUT B 6 OUT A OUT B 6 IN C IN C IN A IN C IN C IN C OUT C OUT A IN A MCB Quad Input OR Gate MCB Triple Input AND Gate MCB Quad Input AND Gate MCB Dual Input AND Gate IN A IN A IN D IN A IN A IN C IN A IN A IN D OUT A IN A OUT A IN D IN B IN C OUT A IN D IN A OUT B OUT D IN B IN C OUT B OUT D IN A IN B OUT C IN B OUT C IN B OUT C IN A IN B 6 IN C OUT B 6 OUT A IN B 6 IN C NC 6 IN C IN A IN C OUT B IN B IN B IN B IN B NC NC = NO CONNECTION

3 MCB Series ELECTRICAL CHARACTERISTICS (Voltages Referenced to ) Characteristic Output Voltage V in = or Level Symbol V OL. V. Level V in = or OH Input Voltage Level (V O =. or. ) (V O =. or. ) (V O =. or. ) (V O =. or. ) (V O =. or. ) (V O =. or. ) Level Output Drive Current (V OH =. ) Source (V OH =.6 ) (V OH =. ) (V OH =. ) V IL. V IH. I OH.. C C C Min Max Min Typ (Note ) Max Min Max Unit madc (V OL =. ) Sink (V OL =. ) (V OL =. ) I OL Input Current I in ±. ±. ±. ±. Adc Input Capacitance (V in = ) Quiescent Current (Per Package) Total Supply Current (Notes, ) (Dynamic plus Quiescent, Per Gate, C L = pf) C in.. pf I DD. I T I T = (. A/kHz) f + I DD /N I T = (.6 A/kHz) f + I DD /N I T = (. A/kHz) f + I DD /N Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance.. The formulas given are for the typical characteristics only at C.. To calculate total supply current at loads other than pf: I T (C L ) = I T ( pf) + (C L ) Vfk where: I T is in A (per package), C L in pf, V = ( ) in volts, f in khz is input frequency, and k =. x the number of exercised gates per package madc Adc Adc

4 MCB Series BSERIES GATE SWITCHING TIMES SWITCHING CHARACTERISTICS (Note ) (C L = pf, T A = C) Characteristic Output Rise Time, All BSeries Gates t TLH = (. ns/pf) C L + ns t TLH = (.6 ns/pf) C L + ns t TLH = (. ns/pf) C L + ns Symbol t TLH. Min Typ (Note 6) Max Unit ns Output Fall Time, All BSeries Gates t THL = (. ns/pf) C L + ns t THL = (.6 ns/pf) C L + ns t THL = (. ns/pf) C L + ns t THL. ns Propagation Delay Time MCB, MCB only t PLH, t PHL = (. ns/pf) C L + ns t PLH, t PHL = (.6 ns/pf) C L + ns t PLH, t PHL = (.6 ns/pf) C L + ns All Other,, and Input Gates t PLH, t PHL = (. ns/pf) C L + ns t PLH, t PHL = (.6 ns/pf) C L + ns t PLH, t PHL = (.6 ns/pf) C L + ns Input Gates (MC6B, MCB) t PLH, t PHL = (. ns/pf) C L + ns t PLH, t PHL = (.6 ns/pf) C L + 6 ns t PLH, t PHL = (.6 ns/pf) C L + ns t PLH, t PHL. The formulas given are for the typical characteristics only at C. 6. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance ns PULSE GENERATOR INPUT * C L OUTPUT *All unused inputs of AND, NAND gates must be connected to. All unused inputs of OR, NOR gates must be connected to. ns ns INPUT % % % t PHL t PLH OUTPUT INVERTING OUTPUT NON-INVERTING t THL t PLH t TLH V % V OH % % V OL t TLH t PHL V OH % % % V OL t THL Figure. Switching Time Test Circuit and Waveforms

5 MCB Series CIRCUIT SCHEMATIC NOR, OR GATES MCB, MCB One of Four Gates Shown MCB One of Three Gates Shown, 6,,,,,,, *,,,,, * *Inverter omitted in MCB, 6,,, *Inverter omitted in MCB CIRCUIT SCHEMATIC NAND, AND GATES MCB, MCB One of Three Gates Shown MCB, MCB One of Four Gates Shown *,,,,,,,,,, *, 6,, *Inverter omitted in MCB,,, 6, *Inverter omitted in MCB

6 MCB Series TYPICAL BSERIES GATE CHARACTERISTICS NCHANNEL DRAIN CURRENT (SINK) PCHANNEL DRAIN CURRENT (SOURCE) T A = - C + C - C + C + C T A = - C + C - C + C + C V DS, DRAIN-TO-SOURCE VOLTAGE () V DS, DRAIN-TO-SOURCE VOLTAGE () Figure. V GS =. Figure. V GS = T A = - C - C + C + C + C T A = - C - C + C + C + C V DS, DRAIN-TO-SOURCE VOLTAGE () V DS, DRAIN-TO-SOURCE VOLTAGE () Figure. V GS = Figure. V GS = T A = - C - C + C + C + C T A = - C - C + C + C + C V DS, DRAIN-TO-SOURCE VOLTAGE () Figure 6. V GS = V DS, DRAIN-TO-SOURCE VOLTAGE () Figure. V GS = These typical curves are not guarantees, but are design aids. Caution: The maximum rating for output current is ma per pin. 6

7 MCB Series TYPICAL BSERIES GATE CHARACTERISTICS (cont d) VOLTAGE TRANSFER CHARACTERISTICS V out, OUTPUT VOLTAGE ()..... SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND V out, OUTPUT VOLTAGE () SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND V in, INPUT VOLTAGE () V in, INPUT VOLTAGE () Figure. =. Figure. = V out, OUTPUT VOLTAGE () SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND DC NOISE MARGIN The DC noise margin is defined as the input voltage range from an ideal or input level which does not produce output state change(s). The typical and guaranteed limit values of the input values V IL and V IH for the output(s) to be at a fixed voltage V O are given in the Electrical Characteristics table. V IL and V IH are presented graphically in Figure. Guaranteed minimum noise margins for both the and levels =. V with a. V supply V in, INPUT VOLTAGE (). V with a. V supply. V with a. V supply Figure. = V out V out V O V O V O V O V in V in V IL V IH (a) Inverting Function V IL V IH = VOLTS DC (b) NonInverting Function Figure. DC Noise Immunity

8 MCB Series ORDERING INFORMATION Device Package Shipping MCBDG NLVBDG* MCBDRG NLVBDRG* MCBDTRG NLVBDTRG* MCBFELG SOIC (PbFree) SOIC (PbFree) TSSOP (PbFree) SOEIAJ (PbFree) Units / Rail Units / Tape & Reel Units / Tape & Reel MCBDG NLVBDG* MCBDRG NLVBDRG* MCBDTRG NLVBDTRG* MCBFG MCBFELG SOIC (PbFree) SOIC (PbFree) TSSOP (PbFree) SOEIAJ (PbFree) Units / Rail Units / Tape & Reel Units / Rail Units / Tape & Reel MCBDG MCBDRG NLVBDRG* MCBFELG SOIC (PbFree) SOIC (PbFree) SOEIAJ (PbFree) Units / Rail Units / Tape & Reel Units / Tape & Reel MCBDG NLVBDG* MCBDRG NLVBDRG* SOIC (PbFree) SOIC (PbFree) Units / Rail Units / Tape & Reel MCBDG NLVBDG* MCBDRG NLVBDRG* MCBDTG MCBDTRG NLVBDTRG* SOIC (PbFree) SOIC (PbFree) TSSOP (PbFree) Units / Rail Units / Tape & Reel 6 Units per Rail Units / Tape & Reel MCBDG MCBDRG SOIC (PbFree) SOIC (PbFree) Units / Rail Units / Tape & Reel

9 MCB Series ORDERING INFORMATION (continued) Device Package Shipping MCBDG NLVBDG* MCBDRG NLVBDRG* MCBDTRG NLVBDTRG* SOIC (PbFree) SOIC (PbFree) TSSOP (PbFree) Units / Rail Units / Tape & Reel MCBDG SOIC Units / Rail NLVBDG* (PbFree) MCBDRG Units / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AECQ Qualified and PPAP Capable.

10 MCB Series PACKAGE DIMENSIONS TSSOP CASE G ISSUE B. (.6) T. (.6) T L. (.) T SEATING PLANE U U S X L/ PIN IDENT. S D C X K REF. (.) M T U S V S N. (.) M B U A V G H N J J F DETAIL E K K ÇÇÇ ÉÉÉ SECTION NN DETAIL E W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.M,.. CONTROLLING DIMENSION: MILLIMETER.. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED. (.6) PER SIDE.. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED. (.) PER SIDE.. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE. (.) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A.... B...6. C.. D....6 F.... G.6 BSC.6 BSC H..6.. J.... J K.... K.... L 6. BSC. BSC M SOLDERING FOOTPRINT*.6.6 PITCH X.6 X.6 DIMENSIONS: MILLIMETERS *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

11 MCB Series PACKAGE DIMENSIONS H. M B M e D X b A B E. M C A S B S A A C SEATING PLANE SOIC NB CASE A ISSUE K DETAIL A h X M L A DETAIL A NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y.M,.. CONTROLLING DIMENSION: MILLIMETERS.. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE. TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION.. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS.. MAXIMUM MOLD PROTRUSION. PER SIDE. MILLIMETERS INCHES DIM MIN MAX MIN MAX A....6 A.... A.... b.... D.... E.... e. BSC. BSC H h.... L...6. M SOLDERING FOOTPRINT* 6. X.. PITCH X. DIMENSIONS: MILLIMETERS *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 6, Denver, Colorado USA Phone: 6 or 6 Toll Free USA/Canada Fax: 66 or 6 Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MCB/D

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