Analog and Telecommunication Electronics

Transcription

1 Politecnico di Torino Electronic Eng. Master Degree Analog and Telecommunication Electronics D3 - A/D converters» Error taxonomy» ADC parameters» Structures and taxonomy» Mixed converters AY /04/ ATLCE - D DDC 2016 DDC 1

2 Lesson D3: ADC taxonomy and errors Analog to Digital converters Transfer function and error taxonomy (linear, nonlinear, dynamic) Converter parameters: complexity and speed Examples of A/D converters Flash, Tracking, Successive approximation Residue, subranging, folding, pipeline Mixed architectures References: Elettronica per Telecom.: 4.3 Convertitori analogico/digitale Design with Op Amp : 12.4 A/D Conversion Techniques Design choices for ADC : course website 16/04/ ATLCE - D DDC 2016 DDC 2

3 Errors in A/D converters Dual transfer function vs D/A X axis: analog values (continuous) Y axis: numeric values (discrete) Same approach to error taxonomy Each A Di interval corresponds to a D i value stair transfer function If N large looks as a continuous line Same error classification as D/A Linear: offset and gain Nonlinearity: differential and integral Dynamic parameters 16/04/ ATLCE - D DDC 2016 DDC 3

4 Ideal A/D transfer function D (digital) M Di LSB A (analog) A Di A D 0 S 16/04/ ATLCE - D DDC 2016 DDC 4

5 ADC vs DAC transfer function DAC: Discrete input D, discrete output A squence of dots ADC: Continuos input A, discrete output D staircase A D A D 1 LSB D A LSB A D 16/04/ ATLCE - D DDC 2016 DDC 5

6 Static errors: two-steps analysis Linear approximation of actual transfer function Actual transfer function vs linear approximation Nonlinearity errors: integral nonlinearity Linear approximation vs ideal transfer function Linear errors: offset and gain Detailed quantization interval analysis Differential nonlinearity 16/04/ ATLCE - D DDC 2016 DDC 6

7 Actual vs ideal transfer function M D ideal 0 0 Actual transfer function S A 16/04/ ATLCE - D DDC 2016 DDC 7

8 Best linear approximation M D Best approx. straigth line 0 0 Actual transfer function S A 16/04/ ATLCE - D DDC 2016 DDC 8

9 Linear approx. vs ideal transf. function M D ideal G Best approx. straigth line O 0 0 S A 16/04/ ATLCE - D DDC 2016 DDC 9

10 Integral nonlinearity error M D integral nonlinearity Nonlinearity band error inl Best approx. straigth line 0 0 Actual transfer function S A 16/04/ ATLCE - D DDC 2016 DDC 10

11 Complete view M D integral nonlinearity error inl Nonlinearity band ideal Best approx. straigth line 0 0 Actual transfer function S A 16/04/ ATLCE - D DDC 2016 DDC 11

12 Linear and nonlinear errors Offset error shift of the output Gain errors rotation of the transfer function Both can be compensated with gain and offset corrections in the signal chain Integral nonlinearity error inl Position dependent Compensation possible (lookup table), but expensive 16/04/ ATLCE - D DDC 2016 DDC 12

13 Ideal A/D transfer function Uniform quantization: All quantization intervals AD have the same amplitude M D A D 0 0 S A 16/04/ ATLCE - D DDC 2016 DDC 13

14 Differential nonlinearity error Actual quantization intervals: A D A D Differential nonlinearity: DNL = A D -A D M D Ideal transfer function A D 0 A D Actual transfer function 0 S A 16/04/ ATLCE - D DDC 2016 DDC 14

15 Missing code error Wide intervals reduce adjacent ones Very wide intervals can suppress adjacent ones Missing code error high differential nonlin.: DNL > 1 LSB M D A D1 A D2 0 This code is never generated 0 S A 16/04/ ATLCE - D DDC 2016 DDC 15

16 Integral and differential nonlinearity Integral nonlinearity INL Unique figure: deviation of transfer function from a straight line Differential nonlinearity DNL Difference A D -A D between ideal (A D ) and actual (A D ) amplitude of each quantization interval Specific to each interval (but has a max!) ε INL = ( DNL ) = ( DNL ) ε DNL = Der( INL ) Fixed polarity ε DNL high ε INL Alternate polarity ε DNL low ε INL 16/04/ ATLCE - D DDC 2016 DDC 16

17 Dynamic parameters Conversion from A to D requires some time: conversion time Tc Can be specified also as conversion frequency Fc = 1/Tc In most cases The ADC receives a Conversion Start (CS) command After Tc the ADC raises a End Of Conversion (EOC) flag. Some ADC can follow a (slowly) changing signal: tracking converters Dynamic behavior specified by max track rate (Slew Rate) 16/04/ ATLCE - D DDC 2016 DDC 17

18 ADC error summary Linear errors: Gain: G Offset: O Nonlinearity errors: Integral NL: inl Differential NL: dnl Dynamic parameters Conversion time: t C Tracking rate: max(dv/dt) 16/04/ ATLCE - D DDC 2016 DDC 18

19 Lesson D3: A/D converters Analog to Digital converters Error taxonomy (linear, nonlinear, dynamic) Converter parameters: complexity and speed Examples of A/D converters Flash, Tracking Successive approximation, Residue/subranging Pipeline structures Performance tradeoff 16/04/ ATLCE - D DDC 2016 DDC 19

20 A/D converter architectures Various types of ADC, which can be classified from: Complexity» Number of comparators in the circuit» Better if few comparators Conversion time Tc» Or conversion rate Fc, inverse of Tc» Better if low Tc (high speed, high Fc) Linked parameters: High speed converters are more complex High speed and high resolution are expensive. 16/04/ ATLCE - D DDC 2016 DDC 20

21 A/D converters classification Complexity Conv time Parallel (flash) Pipeline Residue Successive approximation Tracking, Ramp Complexity: number of comparators. Conversion time: Tc = 1/Fc (inverse of the number of conversion/s). 16/04/ ATLCE - D DDC 2016 DDC 21

22 Parallel (flash) ADC V R thermometric or linear output coding A Analog input level (between 0 and V R ) 16/04/ ATLCE - D DDC 2016 DDC 22

23 Flash ADC with coded output V R M N encoder A M-N enc M = 2 N -1 N 16/04/ ATLCE - D DDC 2016 DDC 23

24 Flash converter parameters 2 N comparators (2 N -1) 1 comparison cycle for N bits Fast all comparators operate in the same time slot Complex requires many comparators 16/04/ ATLCE - D DDC 2016 DDC 24

25 DAC - feedback converters A logic network builds an approximation A of the input A using results of A<--> A comparison A is obtained from D through a DAC D is the numeric representation of A A A + - Logic network DAC D 16/04/ ATLCE - D DDC 2016 DDC 25

26 Feedback converters algorithms The logic network modifies D till A becomes the best approximation of A (within the N-bit resolution) Two procedures: Steps of one LSB: tracking converters 2 N steps for full scale change; conversion time: T C = 2 N T CK Start from MSB: successive approximation converters N steps for any conversion: T C = N T CK 16/04/ ATLCE - D DDC 2016 DDC 26

27 LSB steps: staircase converter Counter with enable If A < A, EN = 1 (counter enabled) If A > A, EN = 0 (counter disabled) M = 2 N steps from 0 to S:T C = 2 N T CK A A + - EN counter CK DAC D 16/04/ ATLCE - D DDC 2016 DDC 27

28 Signal acquisition with staircase ADC As long as A < A, EN = 1 and counter is enabled, The feedback signal A goes up 1 LSB for each Tck As A > A the comparator disables the counter; A stops max conversion time: Tc max (0 to S change of A) = 2 N Tck For new conversion reset counter to 0 16/04/ ATLCE - D DDC 2016 DDC 28

29 LSB steps: tracking converter Up/Down counter If A < A, D = D + 1 If A > A, D = D - 1 M = 2 N steps from 0 to S:T C = 2 N T CK A A + - U/D U/D counter CK DAC D 16/04/ ATLCE - D DDC 2016 DDC 29

30 Acquisition of constant signal As long as A < A, counter goes UP on CK edges The feedback signal A moves 1 LSB for each Tck As A > A the counter reverses count direction max conversion time: Tc max (0 to S change of A) = 2 N Tck 16/04/ ATLCE - D DDC 2016 DDC 30

31 Tracking of variable signals The converter can track signals with dv/dt < A D /Tck Overload Tracking 16/04/ ATLCE - D DDC 2016 DDC 31

32 Tracking converter parameters 1 comparator 2 N comparison cycle for N bits Slow fully sequential decisions limited dv/dt tracking capability Simple requires a single comparator 16/04/ ATLCE - D DDC 2016 DDC 32

33 Start with MSB: succ. approx. ADC Input signal compared with S/2: result --> MSB MSB = 0: next comparison with S/4 MSB = 1: next comparison with 3S/4 result --> MSB A A + - Successive approximation register (SAR) DAC D 16/04/ ATLCE - D DDC 2016 DDC 33

34 Approximation sequence - 1 Input signal A S A S/2 0 t 16/04/ ATLCE - D DDC 2016 DDC 34

35 Approximation sequence - 2 A is compared with S/2 A = S/2 by setting MSB = 1 S A S/2 0 t A = S/2 16/04/ ATLCE - D DDC 2016 DDC 35

36 Approximation sequence - 3 Since A > S/2, MSB = S/2 excluded from possible A values S A S/2 0 t A = S/2 A > A MSB = 1 16/04/ ATLCE - D DDC 2016 DDC 36

37 Approximation sequence - 4 A compared with mid-value of possible range A = 3S/4 by setting MSB-1 = 1 S A 3S/4 S/2 0 t A = S/2 A > A MSB = 1 A = 3S/4 16/04/ ATLCE - D DDC 2016 DDC 37

38 Approximation sequence - 5 Since A < 3S/4, MSB -1 = 0 3S/4 - S range excluded from possible A values S A 3S/4 S/2 0 t A = S/2 A > A MSB = 1 A = 3S/4 A < A MSB-1 = 0 16/04/ ATLCE - D DDC 2016 DDC 38

39 Approximation sequence - 6 A is compared with mid-value of possible range A = 5S/8 by setting MSB - 2 = 1 S A 3S/4 S/2 0 t A = S/2 A > A MSB = 1 A = 3S/4 A < A MSB-1 = 0 A = 5S/8 16/04/ ATLCE - D DDC 2016 DDC 39

40 Approximation sequence - 7 Since A < 5S/8, MSB - 2 = 1 S/2-5S/8 range excluded from possible A values S A 3S/4 S/2 0 t A = S/2 A > A MSB = 1 A = 3S/4 A < A MSB-1 = 0 A = 5S/8 A > A MSB-2 = 1 A = 11S/16 16/04/ ATLCE - D DDC 2016 DDC 40

41 Approximation sequence - 8 Since A < 11S/16, MSB - 3 must be 0 11S/16-3S/4 range excluded from possible A values S A 3S/4 S/2 0 t A = S/2 A > A MSB = 1 A = 3S/4 A < A MSB-1 = 0 A = 5S/8 A > A MSB-2 = 1 A = 11S/16 A < A MSB-3 = 0 16/04/ ATLCE - D DDC 2016 DDC 41

42 Complete decision tree S 3S/4 A S/2 0 lower: 0 higher: 1 lower: Sequence of possible output A from D/A which are compared with A t 16/04/ ATLCE - D DDC 2016 DDC 42

43 Successive approx. ADC parameters Single comparator N comparison cycles for N-bit conversion Vs flash ADC Simpler: 1 comparator vs 2 N Slower: N steps vs 1 Vs tracking ADC Same complexity: 1 comparator faster: N steps vs 2 N 16/04/ ATLCE - D DDC 2016 DDC 43

44 Speed vs complexity Complex Conv time Parallel (flash) 2 N 1??? (Pipeline) N 1??? (Residue) N N Successive Approx 1 N Tracking 1 2 N Complexity: Conversion time: proportional to the number of comparators. the maximum number of comparator delay (clock periods) to complete a conversion the table suggest two new types of ADC. 16/04/ ATLCE - D DDC 2016 DDC 44

45 Lesson D3: A/D converters Analog to Digital converters Error taxonomy (linear, nonlinear, dynamic) Converter parameters: complexity and speed Examples of A/D converters Flash, Tracking Successive approximation, Residue/subranging Pipeline structures Performance tradeoff 16/04/ ATLCE - D DDC 2016 DDC 45

46 Comparison in SAR ADC Sequence of comparison in the SAR ADC: MSB: A > S/2? MSB-1: A > S/4 + S/2 MSB? A > S/4 if MSB = 0 A > S/4 + S/2 if MSB = 1 A - S/2 MSB > S/4? 2(A - S/2 MSB) > S/2? A - S/2 MSB = R1 (MSB residue) MSB-1 decision becomes 2 R1 > S/2? Similar to MSB decision (comparison A S/2) 16/04/ ATLCE - D DDC 2016 DDC 46

47 Comparison in SAR ADC Sequence of comparison in the SAR ADC: MSB: A > S/2? MSB-1: A > S/4 + S/2 MSB? A > S/4 if MSB = 0 A > S/4 + S/2 if MSB = 1 A - S/2 MSB > S/4? 2(A - S/2 MSB) > S/2? A - S/2 MSB = R1 (MSB residue) MSB-1 decision becomes 2 R1 > S/2? The SAR algorithm can find bit(msb-i) by comparing residue Ri with S/2 MSB: i = 0; MSB-1: i = 1;. 16/04/ ATLCE - D DDC 2016 DDC 47

48 Subranging/residue converter The residue (order M) is the difference between A and its M-bit approximation on each step the residue is amplified (x 2) and compared again with S/2 S A S/2 R1 2 R1 2 R2 R3 0 S = S/2 MSB = 1 R2 S = S/2 MSB-1 = 0 S = S/2 MSB-2 = 1 t 16/04/ ATLCE - D DDC 2016 DDC 48

49 Subranging ADC procedure - 1 At first step A is compared with S/2 Since A > S/2, MSB = 1 S A S/2 0 S = S/2 A > S/2? t 16/04/ ATLCE - D DDC 2016 DDC 49

50 Subranging ADC procedure - 2 The MSB residue is R1 R1 is amplified (x 2) and compared with S/2 S A S/2 R1 2 R1 0 S = S/2 MSB = 1 S = S/2 2R1 > S/2? t 16/04/ ATLCE - D DDC 2016 DDC 50

51 Subranging ADC procedure - 3 Since 2R1 < S/2, MSB-1 = 0 The MSB-1 residue is R2 R2 is amplified (x 2)and compared with S/2 S A S/2 R1 2 R2 0 S = S/2 MSB = 1 2 R1 R2 S = S/2 MSB-1 = 0 S = S/2 2R2 > S/2? t 16/04/ ATLCE - D DDC 2016 DDC 51

52 Subranging ADC procedure - 4 Since 2R2 > S/2, MSB-2 = 1 The MSB-2 residue is R3 R3 is amplified (x 2)and compared with S/2 S A S/2 R1 R3 0 S = S/2 MSB = 1 R2 2 R1 2 R2 S = S/2 MSB-1 = 0 S = S/2 MSB-2 = 1 t 16/04/ ATLCE - D DDC 2016 DDC 52

53 Subranging ADC procedure - 5 Ri = A (i-bit approximation of A) At each step the residue Ri is amplified (x 2) and compared with S/2 S A S/2 R1 R3 0 S = S/2 MSB = 1 R2 2 R2 S = S/2 MSB-1 = 0 S = S/2 MSB-2 = 1 t 16/04/ ATLCE - D DDC 2016 DDC 53

54 Residue converter parameters The residue ADC uses, for each bit One comparator (for bit value decision) One 1-bit DAC (to build the approximation) One (analog) adder (to evaluate the residue) One amplifier (gain = 2) (to bring residue to full scale) 16/04/ ATLCE - D DDC 2016 DDC 54

55 Block diagram of residue ADC R1 or 2R1 R2 2R2 16/04/ ATLCE - D DDC 2016 DDC 55

56 Precision in subranging converters Any error in residue evaluation is propagated to the following stages Residue must be evaluated with a resolution corresponding to the residual bit number» ADC precision» DAC precision» Amplifiers and S/H (pipeline) precision Previous example First stage (MSB): ADC and DAC need 8-bit precision Second stage (MSB-1): only 7 bits must be evaluated; the precision required corresponds to 7-bit ADC Third stage: 6 bits remaining Precision decreases going towards LSBs 16/04/ ATLCE - D DDC 2016 DDC 56

57 Subranging ADC parameters N comparators N comparison cycles for N-bit conversion Vs successive approximation ADC: Same speed: N steps Higher complexity: N vs 1 comparator No benefit Useful as starting structure for pipeline ADC 16/04/ ATLCE - D DDC 2016 DDC 57

58 Lesson D3: A/D converters Analog to Digital converters Error taxonomy (linear, nonlinear, dynamic) Converter parameters: complexity and speed Examples of A/D converters Flash, Tracking Successive approximation, Residue/subranging Pipeline structures Performance tradeoff 16/04/ ATLCE - D DDC 2016 DDC 58

59 Pipeline sequence Input sample sequence: A, B, C, D,... Operate on different samples at the same time Needs analog memory elements Processing: stage t 1 t 2 t 3 t 4 1 A B C D 2 X A B C 3 X X A B 4 X X X A t 1 : Input sample 1 t 2 : Input sample 2, processa 1 t 3 : Input sample 3, processa 2, processb 1... result of sample A conversion available 16/04/ ATLCE - D DDC 2016 DDC 59

60 Pipeline-subranging ADC 16/04/ ATLCE - D DDC 2016 DDC 60

61 Comparison with other techniques A N-bit pipeline A/D converter uses: N comparators N comparison cycles (to complete the conversion of each sample) Conversion time: N-cycle latency 1-cycle conversion (throughput) Same speed as a flash with N comparators (2 N in the flash) 16/04/ ATLCE - D DDC 2016 DDC 61

62 Speed vs complexity Complex Conv time Latency Parallel (flash) 2 N 1 1 Pipeline N 1 N Residue N N N Successive Approx 1 N N Tracking 1 2 N 2 N Complexity: Conversion time: Latency: proportional to the number of comparators. the maximum number of comparator delay (clock periods) to complete a conversion delay to get the result. 16/04/ ATLCE - D DDC 2016 DDC 62

63 Classic 8-bit converters 8-bit Flash: = 255 comparators; T CT = T C 8-bit SAR: 1 comparator; T CT = 8 T C + 7 T DA Limited choice No room for tradeoff Can we do something between? Faster than SAR, slower than flash Less expensive than flash (less comparators) 16/04/ ATLCE - D DDC 2016 DDC 63

64 Example: best cost/speed architecture Goal: 8-bit ADC Conversion time Tct < 60 ns Devices available: comparators with Tc = 10 ns Suitable classic design SAR: conversion time Tc = 8 x 10 = 80 ns too long Flash: Tc = 10 ns, but» Expensive: 255 comparators» Overkill: too fast, 60 ns is enough! Any other choice? 16/04/ ATLCE - D DDC 2016 DDC 64

65 Multibit residue architectures First-stage conversion on 1, 2, 3, M bits Comparators are replaced by M-bit ADC The approximation is built using M-bit DAC Residue has a max value Ad = S/ 2 M Gain required to bring residue up to S: 2 M Multibit-residue provides various speed/complexity tradeoffs Higher speed, with the same number of comparators Less comparators for the same speed Better tuning of design to specifications 16/04/ ATLCE - D DDC 2016 DDC 65

66 Choices for 8-bit converters Comparators, conversion time (T CT ), latency (T L ) 8-bit Flash: = 255 comparators; T CT = T C T L = 1 8-bit SAR: 1 comparator; T CT = 8 T C + 7 T DA T L = 8 Something in the middle: multibit residue subranging converters Two cascaded 4-bit flash: 2(2 4-1) = 30 comparators; T CT = 2T C +T DA T L = 2 Four cascaded 2-bit flash: 4(2 2-1) = 12 comparators; T CT = 4T C + 3 T DA T L = 4 16/04/ ATLCE - D DDC 2016 DDC 66

67 Multibit residue ADC comparison A/D - 4bit + 16 D/A - 4bit MSB,.. (D7, 6, 5, 4) A/D - 2bit + 4 D/A - 2bit MSB, MSB-1 (D7, D6) A/D - 4bit D3, 2, 1, 0 A/D - 2bit D5, D4 8-bit residue ADC: 2 4-bit cells Total conversion time: Tct = 2 x Tc(A/D) + Ta(D/A) + 4 D/A - 2bit A/D - 2bit D3, D2 + D/A - 2bit 8-bit residue ADC: 4 2-bit cells Total conversion time: 4 A/D - 2bit LSB+1, LSB (D1, D0) Tct = 4 x Tc(A/D) + 3 x Ta(D/A) 16/04/ ATLCE - D DDC 2016 DDC 67

68 Mixed and multistage converters Application of subranging to bit groups (K-bit) Comparator N bit ADC Residue evaluation N bit DAC + differential amplifier With K-bit groups N/K stages Interstage amplifier gain 2 N Basic ADC: FLASH Complexity: Ps = 2 K total: P T = N/K x 2 K Conversion time T C = 1 total: T CT = N/K x T C Basic ADC: SAR Complexity: Ps = 1 total: P T = N/K Conversion time T C = K total: T CT = N x T C 16/04/ ATLCE - D DDC 2016 DDC 68

69 Speed vs complexity with multibit - 1 Complex Speed Conv time Latency Parallel (flash) 2 N 1 1 Pipeline N 1 N Residue N N N Residue K bit N/K N/K N Successive Approx 1 N N Tracking 1 2 N 2 N. 16/04/ ATLCE - D DDC 2016 DDC 69

70 Pipeline converters Pipeline can be used for any multistage Reduces the equivalent conversion time T CT Faster equivalent conversion rate F S Same latency time Pipeline = Residue + Memory element (analog) at the input of each stage Change each amplifier into Sample/Hold + amplifier Some added complexity Multibit residue pipeline FLASH ADC: equivalent T CT = 1 (more precisely T C +T DA ) SAR ADC: equivalent T CT = K T C (more precisely K (T C +T DA )) Additional design freedom 16/04/ ATLCE - D DDC 2016 DDC 70

71 Speed vs complexity with multibit - 2 Complex Speed Time Latency Parallel (flash) 2 N 1 1 Pipeline N 1 N Residue N N N Residue K bit Flash (2 K )N/K N/K N/K Residue K bit SAR N/K N N Successive Approx 1 N N Tracking 1 2 N 2 N. 16/04/ ATLCE - D DDC 2016 DDC 71

72 Speed vs complexity - graph Complexity (log) 2 N Flash N Pipeline Residue 1 SAR 1 N 2 N Tracking Conversion time (log). 16/04/ ATLCE - D DDC 2016 DDC 72

73 Choices for 12-bit residue ADC Complexity (log) Residue 12x1 (Flash) Residue 6x2 <bit/stage>x<num stage> Residue 4x3 Residue 3x4 Residue 2x6 Residue 1x > Conv. time. 16/04/ ATLCE - D DDC 2016 DDC 73

74 Telecom applications ADC Direct RF or IF signal conversion Key parameters Dynamic range (resolution, bit number) Conversion rate (1/Tc) Linearity (total harmonic distortion: THD) Full power bandwidth Spurious free dynamic range (SFDR) Signal/(noise+distortion) ratio (SINAD) 16/04/ ATLCE - D DDC 2016 DDC 74

75 Lab experiment Operation and errors of a D/A converter D/A converter with weighted resistors or ladder network, voltage switches, voltage output. Voltage SW: CMOS logic circuit output (counter) Measurement of A(D) Evaluation of approximating straight line Evaluation of gain, offset, nonlinearity errors Conversion in tracking ADC Dynamic range and slew rate verification Text reference (IT) sect. 4.L1 16/04/ ATLCE - D DDC 2016 DDC 75

76 Lesson D3 - final test Which is the effect of strong differential nonlinearity error? Describe the missed-code error. Which parameters can be used to classify ADCs? Draw the block diagram of a residue/subranging converter. Explain the difference between conversion time and latency. How many comparators are required for a 8-bit flash ADC? Which is the conversion delay (as number of comparator decision times) for a 8-bit SAR ADC? Draw the block diagram of a residue converter using 3 stages, with 3 bits each. 16/04/ ATLCE - D DDC 2016 DDC 76