1. BASIC LOGIC GATES

Transcription

1 1. BASIC LOGIC GATES AIM: To study and verify the truth table of Basic logic gates COMPONENTS REQUIRED: Logic gates (IC) trainer kit. Connecting patch chords. IC 7400, IC 7408, IC 7432, IC 7406, IC 7402, IC 7404, IC 7486 Gates IC NO. AND 7408 OR 7432 NAND 7400 NOR 7402 NOT 7404 XOR 7486 THEORY: Logic gates are idealized or physical devices implementing a Boolean function, which it performs a logical operation on one or more logical inputs and produce a single output. Depending on the context, the term may refer to an ideal logic gate, one that has for instance zero rise time and unlimited fan out or it may refer to anon-ideal physical device. The main hierarchy is as follows:- 1. Basic Gates 2. Universal Gates 3. Advanced Gates CSE Page 1

2 Basic Gates 1. AND gate: - Function of AND gate is to give the output true when both the inputs are true. In all the other remaining cases output becomes false. Following table justifies the statement:- Input A Input B Output IC OR gate: - Function of OR gate is to give output true when one of the either inputs are true.in the remaining case output becomes false. Following table justifies the statement:- Input A Input B Output CSE Page 2

3 IC NOT gate: -Function of NOR gate is to reverse the nature of the input.it converts true input to false and vice versa. Following table justifies the statement :- Input 1 0 Output 0 1 IC 7404 CSE Page 3

4 Universal Gates 1. NAND gate: -Function of NAND gate is to give true output when one of the two provided input are false. In the remaining output is true case.following table justifies the statement :- A Input B Input Output IC NOR gate: - NOR gate gives the output true when both the two provided input are false. In all the other cases output remains false. Following table justifies the statement :- Input A B Input Output CSE Page 4

5 IC 7402 Advanced Gates XOR gate: - The function of XOR gate is to give output true only when both the inputs are true. Following table explain this:- Input A Input B Output IC 7486 CSE Page 5

6 PROCEDURE: Initially all IC s are fixed on bread broad tightly. Give a supply of +5V cc to the 14 th terminal of IC Connect the 7 th terminal of the IC to the common ground terminal. Verify the truth table of the function by switching ON and OFF the input switches and connecting the output terminals of each gates of IC to the logic Output indictor. Observe the glow of LED at the output indicator. PRECAUTIONS: Loose connections are to be avoided Proper IC s must be selected RESULT: All Basic logic gates have been studied and also verified the truth table. VIVA QUESTIONS AND ANSWERS: 1 What is a logic gate? A Logic gates can have one or more inputs and only one output. The output is active only for certain input combinations. Logic gates are the building blocks of any digital circuit and are also called switches. 2 State the different types of logic gates? The different types of logic gates are AND, OR, NOT etc. 3 Mention various types of IC s available for basic logic gates AND gate OR gate NOT gate 7408 IC 7432 IC 7404 IC CSE Page 6

7 2.UNIVERSAL GATES Aim: Implementing all individual gates with Universal Gates NAND & NOR Apparatu s: Breadboard trainer system, ICs 7400, 7402 Circuit Using NAND Using NOR Diagram CSE Page 7

8 Theory: AND, OR, NOT are called basic gates as their logical operation cannot be simplified further. NAND and NOR are called universal gates as using only NAND or only NOR any logic function can be implemented. Using NAND and NOR gates and De Morgan s Theorems different basic gates & EX-OR gates are realized. PROCEDURE: Initially all IC s are fixed on bread broad tightly. Give a supply of +5V cc to the 14 th terminal of IC Connect the 7 th terminal of the IC to the common ground terminal. Verify the truth table of the function by switching ON and OFF the input switches and connecting the output terminals of each gates of IC to the logic Output indictor. Observe the glow of LED at the output indicator. PRECAUTIONS: Loose connections are to be avoided Proper IC s must be selected OBSERVARION: I N P U T A I N P U T B OUTPUT Result: All individual gates with Universal Gates NAND & NOR has been implemented. VIVA QUESTIONS AND ANSWERS: 1 Mention various types of IC s available for universal logic gates NAND gate 7400 IC NOR gate 7402 IC 2 Why NAND and NOR gates are called Universal gates? NAND and NOR gates are called universal gates because they can be used in construct of all basic gates that AND, OR and NOT at any combination of the functions. CSE Page 8

9 3 Realize the XOR gate using minimum number of NOR gates. 4 Realize the XOR gate using minimum number of NAND gates. CSE Page 9

10 3. De-MORGAN Law Aim:- Design a circuit for the given canonical form, draw the circuit diagram and verify the DE-Morgan laws Components:- 1. Logic gates (IC) trainer kit. 2. Connecting wires. 3. IC 7408, IC Theory : We have known the basic operation of binary arithmetic such as binary addition, binary subtraction, binary multiplication and binary division. Now we will look through the most important part of binary arithmetic on which a lot of Boolean algebra stands, that is De-Morgan s Theorem which is called De-Morgan s Laws often. Before discussing De-Morgan's theorems we should know about complements. Complements are the reverse value of the existing value. We are trying to say that as there are only two digits in binary number system 0 & 1. Now if A = 0 then complement of A will be 1 or A = 1.There are actually two theorems that were put forward by De-Morgan. On the basis of DE Morgan s laws much Boolean algebra are solved. Solving these types of algebra with De-Morgan's theorem has a major application in the field of digital electronics. De Morgan s theorem can be stated as follows:- Theorem 1: The compliment of the product of two variables is equal to the sum of the compliment of each variable.thus according to De-Morgan's laws or De- Morgan's theorem if A and B are the two variables or Boolean numbers. Then accordingly (A.B) = A + B Theorem 2: The compliment of the sum of two variables is equal to the product of the compliment of each variable. Thus according to De Morgan s theorem if A and B are the two variables then. (A + B) = A.B CSE Page 10

11 Circuit Diagram: Truth Table: Output Y=(A'+ B').(B'+C').( A'+C') PROCEDURE: CSE Page 11

12 Initially all IC s are fixed on bread broad tightly. Give a supply of +5V cc to the 14 th terminal of IC Connect the 7 th terminal of the IC to the common ground terminal. Verify the truth table of the function by switching ON and OFF the input switches and connecting the output terminals of each gates of IC to the logic Output indictor. Observe the glow of LED at the output indicator. PRECAUTIONS: Loose connections are to be avoided Proper IC s must be selected RESULT: Hence, the canonical form for a given circuit has been designed and also verified the truth table by using the De-Morgan Laws. VIVA QUESTIONS AND ANSWERS 1 What is De Morgan theorem De Morgan's laws are a pair of transformation rules that are both valid rules of inference. They are named after Augustus De Morgan 2 What are the types of Canonical and standard forms? Two dual canonical forms of a Boolean function are available: The sum of minterms (SoM) form The product of maxterms (PoM) form. 3 What are minterms? A minterm is a product of all variables taken either in their direct or complemented form 4 What are maxterms? A maxterm is a sum of all variables taken either in their direct or complemented form CSE Page 12

13 4. MULTIPLEXER Aim: Design a combinational logic circuit for 4x1 MUX and verify the truth table Apparatus: Breadboard trainer system,ic Circuit diagram Theory : Multiplexer is a combinational ckt. that is one of the most widely used in digital design. The multiplexer is a data selector which gates one out of several i/ps to a single o/p. It has n data i/ps & one o/p line & m select lines where 2 m = n. Depending upon CSE Page 13

14 the digital code applied at the select inputs one out of n data input is selected & transmitted to a single o/p channel. Normally strobe(g) input is incorporated which is generally active low which enables the multiplexer when it is LOW. Strobe i/p helps in cascading. A 4:1 Mux. using NAND gate can be designed as shown in dgm 1. No. of ICs are available such as 74157, (Quad 2:1 mux), 74352, (dual 4:1 Mux.), 74151A, (8:1 Mux.), (16:1 Mux). IC 74151A is a 8 : 1 multiplexer which provides two complementary o/ps Y & The o/p Y is same as the selected & Y is its i/p complement. The n:1 multiplexer can be used to realize a m variable function. (2 m = n, m is no. of select inputs) PROCEDURE: Initially all IC s are fixed on bread broad tightly. Give a supply of +5V cc to the 14 th terminal of IC Connect the 7 th terminal of the IC to the common ground terminal. Verify the truth table of the function by switching ON and OFF the input switches and connecting the output terminals of each gates of IC to the logic Output indictor. Observe the glow of LED at the output indicator. PRECAUTIONS: Loose connections are to be avoided Proper IC s must be selected Observation table: Inp uts Outputs C Sele ct B S t r o b e S Q A CSE Page 14

15 0 0 0 B C D E F G H 1 X 1 0 Result: A combinational logic circuit for 4x1 MUX have been designed and also verified it s the truth table. Viva Via Question And Answer: 1 What is a multiplexer? Multiplexer (MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2 n inputs has n select lines, which are used to select which input line to send to the output. 2 List some IC s of MUX IC s, IC s are used for MUX 3 What is the another name of multiplexer A multiplexer is also called a data selector CSE Page 15

16 5.DEMULTIPLEXER Aim: Design a combinational logic circuit for 1x4 DE-MUX and verify the truth table Apparatus: Logic trainer system, connecting wires IC 74155, IC Pinout: Theory: Demux takes single i/p & distributes it over several o/ps. It has one data line, n o/p lines & m select lines where 2 m = n. The logic ckt. of 1:4 demux. using NAND gates is shown in the dgm 1. The ckt. can also be used as binary to decimal decoder with binary inputs applied at the select i/p lines & o/p will be obtained on the corresponding line. MSI ICs available in TTL family for demux. are 74138(3 line to 8 line decoder/demux.), 74139(dual 2 to 4 line decoder/driver.), 74154(4 to 16 line decoder/demux), 74155(dual 2 to 4 line decoder) etc. IC is a dual 2 to 4 line decoder. It has two sets of active low outputs 1Y0 to 1Y3 & 2Y0 to 2Y3. A & B are the select terminals common for both the demux. C1, C2 & G1, G2 are the data lines CSE Page 16

17 & strobe(enable) inputs for the two demux. C1 is active high, C2, G1, G2 are active low. The two 2 line to 4 line demux. can be combined to implement 3 line to 8 line demux. PROCEDURE: Initially all IC s are fixed on bread broad tightly. Give a supply of +5V cc to the 14 th terminal of IC Connect the 7 th terminal of the IC to the common ground terminal. Verify the truth table of the function by switching ON and OFF the input switches and connecting the output terminals of each gates of IC to the logic Output indictor. Observe the glow of LED at the output indicator. PRECAUTIONS: Loose connections are to be avoided Proper IC s must be selected CSE Page 17

18 TRUTH TABLE: SELECT INPUT INPUT ( Aor B) OUTPUT S0 S1 _E I0 I1 I2 I3 Z X X 1 X X X X X X X X X X X 0 X X X 1 X X X X 0 X X X 1 X X X X X X X 1 1 Result: A combinational logic circuit for 1x4 DE-MUX have been designed and also verified it s the truth table. VIVA QUESTIONS AND ANSWERS: 1. what are de-multiplexer? A demultiplexer (or demux) is a device taking a single input signal and selecting one of many data-output-lines, which is connected to the single input. 2. How many control inputs are there in 1:16 demultiplexer? A: 4 3. List some IC s of DE-MUX A: 74150,74151A,74153,74157,74352 IC s are used for DE-MUX CSE Page 18

19 6. DECODER AIM: To design a 2:4 decoder using basic gates. COMPONENTS REQUIRED: i.bread BOARD TRAINNER SYSTEM ii.ic iii. IC iv. Bread board and connecting wires THEORY: A decoder is a combinational circuit that connects the binary information from n input lines to a maximum of 2 n unique output lines. Decoder is also called a min-term generator/max-term generator. A min-term generator is constructed using AND and NOT gates. The appropriate output is indicated by logic 1 (positive logic). Max-term generator is constructed using NAND gates. The appropriate output is indicated by logic 0 (Negative logic). LOGIC DIAGRAM: CSE Page 19

20 Fig: 2:4 DECODER TRUTH TABLE: INP UT OU TP UT BOOLAEN EXPRESSIONS: Y 0 AB Y1 Y 2 Y 3 AB AB AB PROCEDURE: Initially all IC s are fixed on bread broad tightly. CSE Page 20

21 th terminal of IC Give a supply of +5V cc to the 14 Connect the 7 th terminal of the IC to the common ground terminal. Verify the truth table of the function by switching ON and OFF the input switches and connecting the output terminals of each gates of IC to the logic Output indictor. Observe the glow of LED at the output indicator. PRECAUTIONS: Loose connections are to be avoided Proper IC s must be selected RESULT: A 2:4 Decoder using basic gates has been designed. VIVA QUESTIONS AND ANSWERS: 1) What is a decoder? Ans: A decoder is a combinational circuit which has n inputs and to a maximum of 2 n outputs. 2) Give the applications of decoder Ans: Decoders are used for data distribution, code conversion and they are used to route the input data to a specified output line. 3) Why is a demultiplexer called data distributor? Ans: Because the input will be distributed to one of the outputs. 4) Which digital system translates coded characters into a more useful form? Ans: Decoder 5) Differentiate between decoder and demultiplexer. CSE Page 21

22 Ans: A decoder is a combinational circuit which has n inputs and to a maximum of 2 n outputs. A decoder with enable input is known as demultiplexer. 7. ADDER Aim: Design a Half adder and full adder using logic gates and verify the truth table Apparatus: 7404 Logic gate trainer,connecting wires ICs 7486, 7432, 7408, Theory: The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). The carry signal represents an overflow into the next digit of a multi-digit addition. The value of the sum is 2C + S. The simplest half-adder design, pictured on the right, incorporates an XOR CSE Page 22

23 gate for S and an AND gate for C. With the addition of an OR gate to combine their carry outputs, two half adders can be combined to make a full adder. The half adder adds two input bits and generates a carry and sum, which are the two outputs of a half adder. The input variables of a half adder are called the augend and addend bits. The output variables are the sum and carry. Half adder Half adder I n p u t A O u t p u t s u m O u t p u t c a r r y CSE Page 23

24 A one-bit full adder adds three one-bit numbers, often written as A, B, and C in ; A and B are the operands, and C in is a bit carried in from the previous less significant stage. The full adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. bit binary numbers. The circuit produces a two-bit output, output carry and sum typically represented by the signals C out and S, where Full adder Full adder I n p u t I n p u t In p ut Ci n O u t p u t Out put carr y A B s u m Initially all broad tightly PROCEDURE: IC s are fixed on bread CSE Page 24

25 Give a supply of +5V cc to the 14 th terminal of IC Connect the 7 th terminal of the IC to the common ground terminal. Verify the truth table of the function by switching ON and OFF the input switches and connecting the output terminals of each gates of IC to the logic Output indictor. Observe the glow of LED at the output indicator. PRECAUTIONS: Loose connections are to be avoided Proper IC s must be selected Result: Half adder and full adder using logic gates has been designed and verified it s the truth table. VIVA VIA QUESTION AND QUESTION: 1. What is a half adder? a. The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). 2. What are the applications of half adder? a. The applications of half adder are digital computer system, arithmetic circuit. 3. What are the different types of IC s used to build half adder a IC,7400 IC,7402 IC,7408 IC are the different types of IC s used to build half adder. 4. Design a half adder using NAND gates 5. What is a full adder a. A logic circuit that can be added three bits at a time is called as Full Adder CSE Page 25

26 8. SUBTRACTOR Aim: Design a Half subtractor and full subtractor using a basic gates and verify the truth table Apparatus: 7404 Logic gate trainer,connecting wires ICs 7486, 7432, 7408, Theory: HALF SUBTRACTOR: The half subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, the minuend and subtrahend and two outputs the difference and borrow out. The borrow out signal is set when the subtractor needs to borrow from the next digit in a multi-digit subtraction. That is, when. Since and are bits, if and only if and. An important point worth mentioning is that the half subtractor diagram aside implements and not since on the diagram is given by I n p u t A O u t p u t d i f f e r e O u t p u t c b o r r o w CSE Page 26

27 n c e FULL SUBTRACTOR: The full subtractor is a combinational circuit which is used to perform subtraction of three input bits: the minuend, subtrahend, and borrow in. The full subtractor generates two output bits: the difference and borrow out. is set when the previous digit borrowed from. Thus, is also subtracted from as well as the subtrahend. Or in symbols:. Like the half subtractor, the full subtractor generates a borrow out when it needs to borrow from the next digit. Since we are subtracting by and, a borrow out needs to be generated when. When a borrow out is generated, 2 is added in the current digit. (This is similar to the subtraction algorithm in decimal. Instead of adding 2, we add 10 when we borrow.) Therefore,. I n p u t I n p u t In p ut Ci n O u t p u t Out put bor row A B d i f f e CSE Page 27

28 r e n c e PROCEDURE: Initially all IC s are fixed on bread broad tightly. Give a supply of +5V cc to the 14 th terminal of IC Connect the 7 th terminal of the IC to the common ground terminal. Verify the truth table of the function by switching ON and OFF the input switches and connecting the output terminals of each gates of IC to the logic Output indictor. Observe the glow of LED at the output indicator. PRECAUTIONS: Loose connections are to be avoided Proper IC s must be selected RESULT: Thus, half subtractor and full subtractor have been designed and also verified its truth table. VIVA QUESTIONS AND ANSWERS: 1. What is a half subtractor? a. The half subtractor which can subtract two single binary digits A and B. It has two outputs, difference (D) and borrow (B). 2. What are the applications of half subtractor? a. The applications of half subtractor are digital computer system, arithmetic circuit. 3. What are the different types of IC s used to build half subtractor a IC,7400 IC,7402 IC,7408 IC,7404 IC are the different types of IC s used to build half subtractor. 4. What are the advantages of Full Subtractor over half subtractor? CSE Page 28

29 a. The full subtractor can be constructed from two half subtractor. 5. What is a full subtractor a. A logic circuit that can be subtract three bits at a time is called as Full Subtractor. CSE Page 29

30 9. FLIP-FLOPS Aim: Verification of truth table of basic flip flop with synchronous and asynchronous modes Apparatus: Digital flip flop trainer ICs 7400, 7402, 7404, 7476, Circuit Diagram I) SR FF using NAND INPUT CLK Input R Input S Output Q OUTPUT Q 0 X X PREVIOUS STATE Q Q II) JK FF (IC 7476) INDETERMINITE INPUT CLK Input R Input S Output Q OUTPUT Q 0 X X PREVIOUS STATE NO CHANGE Q (TOGGLE) CSE Page 30

31 III) T FF using JK CLK T Q INPUT CLK INPUT T O X X 1 0 Q N 1 1 Q N OUTPUT Q N+1 D FILP FLOP INPUT CLK INPUT D OUTPUT Q N+1 O X PREVIOUS STATE Theory: Flip-flops are the basic building blocks of sequential ckt. The clocked FFs change their o/p state depending upon i/p's at certain interval of time synchronized with the clock pulse applied to it. Different types of FFs are S-R, J-K, D & T. Their operations are described by the respective truth tables. MSI chip 7476 incorporates two negative edge triggered Master Slave JK flip-flops. The J-K flip-flop can be converted to D & T flip flop. PROCEDURE: Initially all IC s are fixed on bread broad tightly. Give a supply of +5V cc to the 14 th terminal of IC Connect the 7 th terminal of the IC to the common ground terminal. Verify the truth table of the function by switching ON and OFF the input switches and connecting the output terminals of each gates of IC to the logic Output indictor. Observe the glow of LED at the output indicator. PRECAUTIONS: Loose connections are to be avoided Proper IC s must be selected CSE Page 31

32 Result: Truth table of basic flip flop with synchronous and asynchronous modes has been verified. VIVA VIA QUESTION AND QUESTION: 1 What is a flip flop A flip-flop stores a single bit (binary digit) of data; one of its two states represents a "one" and the other represents a "zero". Such data storage can be used for storage of state, and such a circuit is described as sequential logic. 2 What are the basic application of flip flop in digital systems i.used in memory unit or storage cell ii.use to construction of source switches iii.register and counter CSE Page 32

33 10. J-K MASTER SLAVE FLIP-FLOP Aim: Implementation of master and slaves flip flops with JK flip flops and verify the truth table for race around condition. Apparatus: Digital trainer system, ICs 7400, 7410 J-K Master slave flip-flops Procedure: CSE Page 33

34 1. Connect the Flip-flop circuits as shown above. 2. Apply different combinations of inputs and observe the outputs Result: The master slave JK flip flop truth table has been verified in race around condition. VIVA VIA QUESTION AND QUESTION: What is a race around condition? Race around condition occurs write associating with JK flip-flop while using J=K=1condition.In this condition the output will be assocating in between 0 and 1 this operation is known as toggling condition What are the basic applications of flip flop in digital system i.used as a memory unit or storage cell ii.use in construction of source switch iii.latches iv.register and counters 11. DECADE COUNTER Aim: Design a Decade counter and verify the truth table Apparatus: i) JK FilpFlop(74LS73IC) 4 ii) 3-Input And Gate (74LS10) 1 iii) Digital IC Trainer Kit iv) Logic Probes and Connecting Wires Theory: This type of asynchronous counter counts upwards on each trailing edge of the input clock signal starting from 0000 until it reaches an output 1001 (decimal 0-9). Both outputs QA and QD are now equal to logic 1. One the application of the next clock pulse, the output from the 74LS10 NAND gate changes state from logic 1 to a logic 0 level. CSE Page 34

35 asynchronous decade counter: Truth table: Clock Output bit Pattern Decimal CSE Page 35

36 Count QD QC QB QA Value Counter Resets its Outputs back to Zero PROCEDURE: Initially all IC s are fixed on bread broad tightly. Give a supply of +5V cc to the 14 th terminal of IC Connect the 7 th terminal of the IC to the common ground terminal. Verify the truth table of the function by switching ON and OFF the input switches and connecting the output terminals of each gates of IC to the logic Output indictor. Observe the glow of LED at the output indicator. PRECAUTIONS: Loose connections are to be avoided Proper IC s must be selected Result: Thus, hence Decade counter has been designed and verified it s the truth table Viva Via Question And Answer: 1) What is a counter? Ans: A counter is a sequential logic circuit capable of counting the number of clock pulses arriving at its clock input. 2) What is a decade counter? CSE Page 36

37 Ans: A decade counter is one that counts in decimal digits, rather than binary. A decade counter may have each or other binary encodings. "A decade counter is a binary counter that is designed to count to 1010b (decimal 10). 3) How many flip flops are required to construct a decade counter? Ans: 4 4) What are the types of counters? Ans: Asynchronous counter, synchronous counter CSE Page 37

38 12. 4-Bit Mod-K SYNCHRONOUS COUNTER AIM: To design a 4-Bit MOD-K synchronous counter using JK filpflop. APPARATUS REQUIRED: BREAD BOARD TRAINNER SYSTEM 2 i/p quad AND gate(ic 7408)-1 JK Flip Flop (IC 74LS76)-2 Connecting wires PIN DIAGRAM: LOGIC DIAGRAM: CSE Page 38

39 TRUTH TABLE: Q 3 PRESENT STATE NEXT STATE FLIP FLOP INPUT S Q Q Q Q Q Q Q T T T PROCEDURE: The circuit for MOD K synchronous counter is designed using JK flip flop After the circuit is realized it is connected as per the circuit diagram Give various combinations of inputs and note down the output with help of LED for all gate ICs one by one T 0 PRECAUTIONS: Loose connections are to be avoided Proper IC s must be selected RESULT: A 4-Bit Mod Synchronous counter using JK flip flop has been designed and also verified its truth table. CSE Page 39

40 VIVA VIA QUESTION AND ANSWER: 1) What is a counter? Ans: A counter is a sequential logic circuit capable of counting the number of clock pulses arriving at its clock input. 2) What is a Modulus Counter? Ans: MOD NCounter :The 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple counter is called as MOD-8 counter. So in general, an n-bit ripple counter is called as modulo-n counter. Where, MOD number = 2 n. 3) List the applications of counter? Ans: Digital clock Time measurement A to D converter Frequency counters Frequency divider circuits Digital triangular wave generator. CSE Page 40

41 DIGITAL LOGIC DESIGN 13. UNIVERSAL SHIFT REGISTER AIM: To design a bidirectional universal shift register. COMPONENTS REQUIRED: BREAD BOARD TRAINNER SYSTEM IC 74LS194-1 Bread board and connecting wires LOGIC DIAGRAM: D 0 D 1 D 2 D CLR 9 SL SER S LS194 IC 4Bit S 1 Universal Bidirectional Shift 2 SR SER Register 7 11 CLK Q 0 Q 1 Q 2 Q 3 CSE Page 41

42 DIGITAL LOGIC DESIGN THEORY: A universal shift register is an integrated logic circuit that can transfer data in three different modes. Like a parallel register it can load and transmit data in parallel. Like shift registers it can load and transmit data in serial fashions, through left shifts or right shifts. In addition, the universal shift register can combine the capabilities of both parallel and shift registers to accomplish tasks that neither basic type of register can perform on its own. For instance, on a particular job a universal register can load data in series (e.g. through a sequence of left shifts) and then transmit/output data in parallel. Universal shift registers, as all other types of registers, are used in computers as memory elements. Although other types of memory devices are used for the efficient storage of very large volume of data, from a digital system perspective when we say computer memory we mean registers. In fact, all the operations in a digital system are performed on registers. Examples of such operations include multiplication, division, and data transfer. PROCEDURE: Initially all IC are fixed on bread broad tightly. Give a supply of +5V cc to the 16 th terminal of IC Connect the 8 th terminal of the IC to the common ground terminal. Connect the input terminals of each pin of IC to logic input switches Connect the output terminal to the logic output indicator. Corresponding shift operations are observed. PRECAUTIONS: Loose connections are to be avoided Proper IC s must be selected. RESULT: Hence the operation of universal shift register was verified. VIVA VIA QUESTION AND ANSWER: 1) What is a register? Ans: A register is basically a set of flip flops logically connected to perform various operations. 2) What is the need of a register? Ans Registers are used for temporary storage of binary information. Registers are also used for shifting the binary information stored in it. 3) What is universal shift register? CSE Page 42

43 DIGITAL LOGIC DESIGN Ans: A unidirectional shift register is a register that can capable of transferring data in only one direction. 4) What is bidirectional shift register? Ans: The register that is capable of transferring data in both left and right direction is called a bidirectional shift register. Now let we have a register which can capable to transfer data in both the shift-right and shift-left, along with the necessary input and output terminals for parallel transfer, then it is called a shift register with parallel load or universal shift register. CSE Page 43