ECE 369. Chapter 3 ECE369

Transcription

1 ECE 369 Chapter 3

2 Our Goal 2

3 Lets Build a Processor, Introduction to Instruction Set Architecture First Step Into Your Project!!! How could we build a -bit ALU for add, and, or? Need to support the set-on-less-than instruction (slt) slt is an arithmetic instruction produces a if a < b and otherwise use subtraction: (a-b) < implies a < b Need to support test for equality (beq $t5, $t6, $t7) use subtraction: (a-b) = implies a = b a operation How could we build a 32-bit ALU? 32 ALU result Must Read Appendix B b

4 One-bit adder Takes three input bits and generates two output bits Multiple bits can be cascaded c out = a.b + a.c in + b.c in sum = a <xor> b <xor> c in 4

5 Building a 32 bit ALU CarryIn Operation Operation a CarryIn a b CarryIn ALU CarryOut Result Result a b CarryIn ALU CarryOut Result b 2 a2 b2 CarryIn ALU2 CarryOut Result2 CarryOut a3 b3 CarryIn ALU3 Result3 5

6 What about subtraction (a b)? Two's complement approach: just negate b and add. How do we negate? A very clever solution: Binvert CarryIn Operation CarryIn a a Operation Result Result = and = or = add = subtract b b CarryOut 2 CarryOut 2 6

7 Supporting Slt Can we figure out the idea? = and = or = add = subtract = slt 7

8 Test for equality Notice control lines Bnegate Operation = and = or = add = subtract = slt a b a b CarryIn ALU Less CarryOut CarryIn ALU Less CarryOut Result Result Zero Note: Zero is a if result is zero! a2 b2 CarryIn ALU2 Less CarryOut Result2 a3 b3 CarryIn ALU3 Less Result3 Set Overflow 8

9 How about a nor b = and = or = add = subtract = slt 9

10 Big Picture

11 Conclusion We can build an ALU to support an instruction set key idea: use multiplexor to select the output we want we can efficiently perform subtraction using two s complement we can replicate a -bit ALU to produce a 32-bit ALU Important points about hardware all of the gates are always working speed of a gate is affected by the number of inputs to the gate speed of a circuit is affected by the number of gates in series (on the critical path or the deepest level of logic ) Our primary focus: comprehension, however, Clever changes to organization can improve performance (similar to using better algorithms in software) How about my instruction smt (set if more than)???

12 ALU Summary We can build an ALU to support addition Our focus is on comprehension, not performance Real processors use more sophisticated techniques for arithmetic Where performance is not critical, hardware description languages allow designers to completely automate the creation of hardware! 2

13 Overflow 3

14 Formulation 4

15 A Simpler Formula? 5

16 Problem: Ripple carry adder is slow! Is a 32-bit ALU as fast as a -bit ALU? Is there more than one way to do addition? Can you see the ripple? How could you get rid of it? c = ab + ac + bc c2 = ab + ac + bc c2 = c3 = a2b2 + a2c2 + b2c2 c3 = c4 = a3b3 + a3c3 + b3c3 c4 = Not feasible! Why? 6

17 Carry Bit c = ab+ ac + bc out i+ i i i in i i in c = a b + a c + bc c + = ab + ac bc c + 2 = ab + ac b c = = i ( a b + a c + b c ) + b ( a b + a c b ) a + b + a c a + b + aab + aac + ab c + ba b + ba c bb c c + 3 = a2b2 + a2c2 b2c2 7

18 Generate/Propagate c + = a b + a c bc = a b + ( a b ) c c + c + 2 = ab + ac bc = a b + ( a + b ) c = [ a b + ( a b ] a ( + c b + a + b ) ) common = { aibi, ai + bi} a i b i c i+ generate = a b i i a i b i c i+ propagate = a i + bi 8

19 Generate/Propagate (Ctd.) generate = a b i i propagate = a i + b i c ( + c = a b + a b ) = g + p c c + 2 = a b + ( a b ) c = g + p ( g + p c ) = g + + p g p p c c = g + i + i p i c i 9

20 Carry-look-ahead adder Motivation: If we didn't know the value of carry-in, what could we do? When would we always generate a carry? g i = a i. b i When would we propagate the carry? p i = a i + b i Did we get rid of the ripple? c = g + pc c2 = g + pc c2 = g + pg + ppc c3 = g2 + p2c2 c3 = g2 + p2g + p2pg + p2ppc c4 = g3 + p3c3 c4 = g3 + p3g2 + p3p2g + p3p2pg + p3p2ppc Feasible! Why? c = ab + ac + bc c2 = ab + ac + bc c2 = c3 = a2b2 + a2c2 + b2c2 c3 = c4 = a3b3 + a3c3 + b3c3 c4 = a3 a2 a a b3 b2 b b 2

21 A 4-bit carry look-ahead adder Generate g and p term for each bit Use g s, p s and carry in to generate all C s Also use them to generate block G and P CLA principle can be used recursively 2

22 6 Bit CLA 22

23 Gate Delay for 6 bit Adder generate = a i b i propagate = a i + b i

24 Multiplication More complicated than addition Accomplished via shifting and addition More time and more area 24

25 Multiplication: Implementation Start Multiplicand Shift left Multiplier =. Test Multiplier Multiplier = 64 bits 64-bit ALU Multiplier Shift right 32 bits a. Add multiplicand to product and place the result in Product register 2. Shift the Multiplicand register left bit Product 64 bits Write Control test 3. Shift the Multiplier register right bit 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done 25

26 Example Multiplicand 64 bits Shift left 64-bit ALU Multiplier Shift right 32 bits Product 64 bits Write Control test 26

27 Second version Multiplicand Shift left 64 bits Start 64-bit ALU Multiplier Shift right 32 bits Multiplier =. Test Multiplier Multiplier = Product Write Control test 64 bits a. Add multiplicand to the left half of the product and place the result in the left half of the Product register Multiplicand 32 bits 2. Shift the Product register right bit 32-bit ALU Multiplier Shift right 3. Shift the Multiplier register right bit Product Shift right Write Control test 32 bits No: < 32 repetitions 32nd repetition? Yes: 32 repetitions 64 bits Done 27

28 Example Multiplicand 32 bits 32-bit ALU Multiplier Shift right 32 bits Product 64 bits Shift right Write Control test 28

29 Final version Start Multiplicand Product =. Test Product Product = 32 bits 32-bit ALU a. Add multiplicand to the left half of the product and place the result in the left half of the Product register Product 64 bits Shift right Write Control test 2. Shift the Product register right bit 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done 29

30 Example Multiplicand 32 bits 32-bit ALU Product 64 bits Shift right Write Control test 3

31 Division Even more complicated Can be accomplished via shifting and addition/subtraction More time and more area Negative numbers: Even more difficult There are better techniques, we won t look at them 3

32 Division: First version 32

33 Example 33

34 Division: Second version 34

35 Improved Division 35

36 Division (7 2) 36

37 Floating point (a brief look) We need a way to represent Numbers with fractions, e.g., 3.46 Very small numbers, e.g.,. Very large numbers, e.g., x 9 Representation: Sign, exponent, fraction: ( ) sign x fraction x 2 exponent More bits for fraction gives more accuracy More bits for exponent increases range IEEE 754 floating point standard: single precision: 8 bit exponent, 23 bit fraction double precision: bit exponent, 52 bit fraction 37

38 IEEE 754 floating-point standard.f x 2 e.s s 2 s 3 s 4. s n x2 e Leading bit of significand is implicit Exponent is biased to make sorting easier All s is smallest exponent, all s is largest Bias of 27 for single precision and 23 for double precision 38

39 Single Precision summary: ( ) sign x (+significand) x 2 (exponent bias) Example: / = / 2 =. =.x - Decimal: -.75 = -3/4 = -3/2 2 Binary: -. = -. x 2 - IEEE single precision: exponent-bias=- => exponent = 26 = 39

40 Opposite Way Sign Exponent Fraction - 29 x2 - +x2-2 =.25 4

41 Floating point addition.6x x.6x x.5x.5x 2.2x 2 4

42 Floating point addition Sign Exponent Fraction Sign Exponent Fraction Start. Compare the exponents of the two numbers. Small ALU Shift the smaller number to the right until its exponent would match the larger exponent Exponent difference 2. Add the significands Control Shift right 3. Normalize the sum, either shifting right and incrementing the exponent or shifting left and decrementing the exponent Big ALU Overflow or underflow? Yes No Exception Increment or decrement Shift left or right 4. Round the significand to the appropriate number of bits Rounding hardware No Still normalized? Yes Sign Exponent Fraction Done 42

43 Add.5 and

44 Multiplication 44

45 Floating point multiply To multiply two numbers Add the two exponent (remember access 27 notation) Produce the result sign as exor of two signs Multiply significand portions Results will be x.xxxxx or.xxxx. In the first case shift result right and adjust exponent Round off the result This may require another normalization step 45

46 Multiplication.5 and

47 Floating point divide To divide two numbers Subtract divisor s exponent from the dividend s exponent (remember access 27 notation) Produce the result sign as exor of two signs Divide dividend s significand by divisor s significand portions Results will be.xxxxx or.xxxx. In the second case shift result left and adjust exponent Round off the result This may require another normalization step 47

48 Floating point complexities Operations are somewhat more complicated (see text) In addition to overflow we can have underflow Accuracy can be a big problem IEEE 754 keeps two extra bits, guard and round Four rounding modes Positive divided by zero yields infinity Zero divide by zero yields not a number Other complexities Implementing the standard can be tricky Not using the standard can be even worse See text for description of 8x86 and Pentium bug! 48

49 Chapter Three Summary Computer arithmetic is constrained by limited precision Read pages Bit patterns have no inherent meaning but standards do exist two s complement IEEE 754 floating point Operations are somewhat more complicated (see text) In addition to overflow we can have underflow Implementing the standard can be tricky Not using the standard can be even worse (3.) See text for description of 8x86 and Pentium bug! 49