Different Implementations

Transcription

1 Building a CPU

2 Different Implementations Not easy to decide the best way to build something Don't want too many inputs to a single gate Don't want to have to go through too many gates For our purposes, ease of comprehension is important Let's look at a -bit ALU for addition: a b 2 CarryOut Sum ABCi Co Sum

3 Different Implementations Remember that we've developed a simple bit adder from basic gates (and, or, xor) a b Sum CarryOut c out = a b + a c in + b c in sum = a b c in 3

4 Review : Logic Combining half adders to make a full adder A B Cin Half Adder Sum Cout Half Adder Cout OR Sum Cout 4

5 Selects one of the inputs to be the output, based on a control input A B Review: The Multiplexor / S C note: we call this a 2-input mux even though it has 3 inputs! Lets build our ALU using a MUX: 5

6 Building a bit ALU a Operation Result What is Result? if a = b = = op = What is Carry Out? b CarryOut 2 What is Result? if a = b = = op = What is Carry Out? 6

7 Building a 32 bit ALU What is Result? if a = b = = op = What is Carry Out? a b a b ALU CarryOut ALU CarryOut Operation Result Result What is Result? if a = b = = op = What is Carry Out? 7 a2 b2 a3 b3 ALU2 CarryOut ALU3 Result2 Result3

8 What about subtraction (a b)? Two's complement approach: just negate b and add. Binvert Operation How do we negate? a very clever solution: / a Result b 2 8 CarryOut

9 What about subtraction (a b)? Two's complement approach: just negate b and BNegate add. a / Binvert Operation So, OpCode Becomes 3 bits - and - or - add - sub Result b 2 9 CarryOut

10 Building a 32 bit ALU What is Result? if a = b = = op = What is Carry Out? a b a b ALU CarryOut ALU CarryOut Operation Result Result What is Result? if a = b = = op = What is Carry Out? a2 b2 a3 b3 ALU2 CarryOut ALU3 Result2 Result3

11 Tailoring the ALU to the MIPS Need to support the set-on-less-than instruction (slt) remember: slt is an arithmetic instruction produces a if rs < rt and otherwise use subtraction: (a-b) < implies a < b Need to support test for equality (beq $t5, $t6, $t7) use subtraction: (a-b) = implies a = b

12 To "less" on bit zero C a r r y O u t High bit i n v e r t r i a. r r y I n a L b 2 s 3 2 O v e r f l o w d e t e Supporting e s u l t slt (see p. 238) opcode S e t

13 Binvert Operation high bit set if negative answer implying a < b 32 bit ALU a b a b a2 b2 ALU Less CarryOut ALU Less CarryOut ALU2 Less CarryOut Result Result Result2 OPCODES and or add sub slt a3 b3 ALU3 Less Set Result3 Overflow 3

14 high bit set if negative answer implying a < b 32 bit ALU c h a Binvert b a b a b a2 b2 ALU Less CarryOut ALU Less CarryOut ALU2 Less CarryOut f ag Operation j Result i Result Result2 OPCODES and or add sub slt d a3 b3 ALU3 Less e Set Result3 Overflow 4

15 slt Example 3 bits a =, b=, a < b, so output a binvert =, carry in =, op = (slt) result of addition =, carry out =, so high bit is set, actual result = this high bit is tied into LESS on bit, so it will be output (selected by the on the multiplexor) indicating that a < b, our desired 5 response

16 slt Example 3 bits a =, b=, a NOT< b, so output a binvert =, carry in =, op = (slt) result of addition =, carry out =, so high bit is clear, actual result is this high bit is tied into LESS on bit, so it will be output (selected by the on the multiplexor) indicating that a is not < b, our 6 desired response

17 B i n v e r t O p e r a t i o n C a r r y I n a b 2 R e s u l t L e s s 3 Supporting a. C a r r y O u t slt B i n v e r t O p e r a t i o n C a r r y I n (see p. 238) a b 2 L e s s 3 R e s u l t S e t Note overflow. see p.238 see p b. O v e r f l o w d e t e c t i o n O v e r f l o w

18 Overflow A simple test for overflow in 2s complement look at carryout & carryin of high bit. + =!CI and!co =!OV 2. + = CI and CO =!OV 3. + =!CI and CO = OV 4. + = CI and!co = OV NOTE: for unsigned, you can simply look at the carryout. If carryout, then overflow 8

19 Overflow CI CO OV For 2's complement overflow detection, run the carry in on the high bit and the carry out of the high bit into an XOR gate = overflow detection 9

20 Test for equality- zero detector Bnegate Operation Note control lines: = and = or = add = sub = slt a b a b ALU Less CarryOut ALU Less CarryOut Result Result Zero a2 b2 ALU2 Less CarryOut Result2 Note: zero is a when the result is zero! a3 b3 ALU3 Less Result3 Set Overflow 2

21 Conclusion We can build an ALU to support the MIPS instruction set key idea: use multiplexor to select the output we want we can efficiently perform subtraction using two s complement we can replicate a -bit ALU to produce a 32-bit ALU Important points about hardware all of the gates are always working the speed of a gate is affected by the number of inputs to the gate the speed of a circuit is affected by the number of gates in series (on the critical path or the deepest level of logic ) Our primary focus: comprehension, however, Clever changes to organization can improve performance (similar to using better algorithms in software) 2 we ll look at two examples for addition and multiplication

22 Problem: ripple carry adder is slow Is a 32-bit ALU as fast as a -bit ALU? Is there more than one way to do addition? two extremes: ripple carry and sum-of-products Can you see the ripple? How could you get rid of it? c = b c + a c + a b c 2 = b c + a c + a b c 3 = b 2 c 2 + a 2 c 2 + a 2 b 2 22 c 4 = b 3 c 3 + a 3 c 3 + a 3 b 3

23 An approach in-between our two extremes Motivation: Carry-lookahead adder If we didn't know the value of carry-in, what could we do? When would we always generate a carry? g i = a i b i generates a carryout independent of a carryin When would we propagate the carry? pi = a i + b I propagates a carryin to a carryout Did we get rid of the ripple? c = g + p c c 2 = g + p c c 2 = c 3 = g 2 + p 2 c 2 c 3 = c 4 = g 3 + p 3 c 3 c 4 = 23 Feasible! Why?

24 Use principle to build bigger adders a b a b a2 2 b2 2 a3 3 b3 ALU P G C pi gi ci + Result--3 Carry-lookahead unit a4 4 b4 4 a5 5 b5 5 a6 6 b6 6 a7 7 b7 a8 8 b8 8 a9 9 b9 9 a b a b a2 2 b2 2 a3 3 b3 3 a4 4 b4 4 a5 5 b5 24 ALU P G ALU2 P2 G2 ALU3 P3 G3 C2 C3 C4 CarryOut pi + gi + ci + 2 pi + 2 gi + 2 ci + 3 pi + 3 gi + 3 ci + 4 Result4--7 Result8-- Result2--5 Can t build a 6 bit adder this way... (too big) Could use ripple carry of 4-bit CLA adders Better: use the CLA principle again!

25 Overflow A simple test for overflow in 2s complement look at carryout & carryin of high bit. + =!CI and!co =!OV 2. + = CI and CO =!OV 3. + =!CI and CO = OV 4. + = CI and!co = OV NOTE: for unsigned, you can simply look at the carryout. If carryout, then overflow 25

26 Test for equality- zero detector Bnegate Operation Note control lines: = and = or = add = sub = slt a b a b ALU Less CarryOut ALU Less CarryOut Result Result Zero a2 b2 ALU2 Less CarryOut Result2 Note: zero is a when the result is zero! a3 b3 ALU3 Less Result3 Set Overflow 26

27 The Processor: Datapath & Control We're ready to look at implementation of MIPS Simplified to contain only: memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beq, j Generic Implementation: use the program counter (PC) to supply instruction address get the instruction from memory read registers use the instruction to decide exactly what to do 27

28 Implementation Details Abstract / Simplified View: Two types of functional units: elements that operate on data values (combinational) elements that contain state (sequential) Data PC Address Instruction Registers ALU Instruction memory Register # Register # Register # Address Data memory Data 28

29 Clocks used in synchronous logic when should an element that contains state be updated? State Elements falling edge cycle time rising edge 29

30 An unclocked state element The set-reset latch output depends on present inputs and also on past inputs 3

31 Our Implementation An edge triggered methodology Typical execution: read contents of some state elements, send values through some combinational logic write results to one or more state elements State element Combinational logic State element 2 3 Clock cycle

32 Register File Note: we still use the real clock to determine when to write Write C D Register Register number n-to- decoder n C D Register n Register data C Register n D C D Register n 32

33 Register File register number register number 2 Register Register Register n Register n M u x data register number register number 2 Register file Write register Write data Write data data 2 M u x data 2 33

34 Simple Implementation Include the functional units we need for each Instruction address instruction PC Instruction Add Sum MemWrite Instruction n memory d n a. Instruction ae memory b. Program counter c. Adder Address Write data data Data memory 6 Sign 32 extend Register numbers Data d 5 3 ALU control d register data dr 5 register 2 Zero U Registers Data ALU ALU e 5 Write result register d e Write data 2 data RegWrite Mem a. Data memory unit b. Sign-extension unit Why do we need this stuff? a. Registers b. ALU 34

35 Simple Implementation Include the functional units we need for each instruction Instruction address Instruction PC Add Sum Instruction memory a. Instruction memory b. Program counter c. Adder 35

36 Simple Implementation Include the functional units we need for each instruction Register numbers Data 5 3 register 5 5 register 2 Registers Write register Write data data data 2 RegWrite Data ALU ALU control Zero ALU result a. Registers b. ALU 36

37 Simple Implementation Include the functional units we need for each instruction M e m Write A d dre s s Write da ta Da ta me m ory R e a d d ata 6 Sig n 32 exte nd M e m R ea d a. Data m e mo ry unit b. Si gn -exte nsio n unit 37

38 Building the Datapath Use multiplexors to stitch them together PCSrc M u U t 4 Add Shift left 2 Add ALU result M u x d d U e sd n M e u a e n PC address Instruction Instruction memory Registers register data register 2 Write register data 2 Write data RegWrite 6 Sign 32 extend ALUSrc M u x 3 ALU operation MemWrite Zero MemtoReg ALU ALU result Address data M u Data x Write memory data Mem 38

39 PCSrc Add M ux 4 Shift left 2 Add ALU result PC address Instruction Instruction memory register register 2 Write register Write data RegWrite Registers data data 2 6 Sign 32 extend ALUSrc M ux 3 ALU operation Zero ALU ALU result Address Write data Mem MemWrite data Data memory MemtoReg M ux 39

40 Control Selects the operations to perform (ALU, read/write, etc.) Controlls the flow of data (multiplexor inputs) Information comes from the 32 bits of the instruction Example: add $8, $7, $8 Instruction Format: op rs rt rd shamt funct ALU's operation based on instruction type and function code 4

41 Control Example: lw $, ($2) 35 2 op rs rt 6 bit offset 4

42 Control ALU control input AND OR add subtract set-on-less-than Why is the code for subtract and not? 42

43 Control M u U t 4 Add Instruction [3 26] Control RegDst Branch Mem MemtoReg ALUOp MemWrite ALUSrc RegWrite Shift left 2 Add result ALU M u x Look at drawing in book d d d n U ed n M e u a e PC address Instruction memory Instruction [3 ] Instruction [25 2] Instruction [2 6] Instruction [5 ] M u x register data register 2 Registers Write data 2 register Write data M u x Zero ALU ALU result Address Write data data Data memory M u x n U Instruction [5 ] 6 Sign 32 extend ALU control Instruction [5 ] Memto- Reg Mem Mem Instruction RegDst ALUSrc Reg Write Write Branch ALUOp ALUp R-format lw sw X X beq X X 43

44 M ux 4 Add Instruction [3 26] Control RegDst Branch Mem MemtoReg ALUOp MemWrite ALUSrc RegWrite Shift left 2 Add result ALU PC address Instruction memory Instruction [3 ] Instruction [25 2] Instruction [2 6] Instruction [5 ] M ux register data register 2 Registers Write data 2 register Write data M ux Zero ALU ALU result Address Write data Data memory data M ux Instruction [5 ] 6 Sign 32 extend ALU control Instruction [5 ] 44

45 Control Try at home this: add $3, $5, $7 PC = $ 3 =?? $ 5 = 68 $7 = 32 45

46 Control Try this: lw $3, (6) $5 PC = $ 3 =?? $ 5 = 4 (6) $5 =

47 MAIN Control M e m to R e g M e m M e m In s tru c tio nr e g D s ta L U S rc R e g W riter e a d W rite B ra n c ha L U O p A L U p R -fo rm a t l w s w X X b e q X X 47

48 ALU Control Describe hardware to compute 3-bit ALU control input given instruction type = lw, sw = beq, = arithmetic function code for arithmetic Describe it using a truth table (can turn into gates): 48 ALUOp computed from instruction type ALUOp Funct field Operation ALUOp ALUOp F5 F4 F3 F2 F F X X X X X X X X X X X X X X X X X X X X X X X X X X X X Look at drawing in book

49 Control Simple combinational logic (truth tables) Inputs Op5 Op4 Op3 ALUOp Op2 Op ALU control block Op ALUOp ALUOp F (5 ) F3 F2 F F Operation2 Operation Operation Operation R-format Iw sw beq Outputs RegDst ALUSrc MemtoReg RegWrite Mem MemWrite Branch ALUOp ALUOpO 49

50 ALU & MAIN Control Simple combinational logic (truth tables) Inputs ALUOp Op5 Op4 ALU control block Op3 ALUOp Op2 ALUOp Op Op F3 Operation2 F (5 ) F2 F F Operation Operation Operation R-format Iw sw beq Outputs RegDst ALUSrc MemtoReg RegWrite Mem MemWrite Branch ALUOp ALUOpO 5

51 Control Simple combinational logic (truth tables) ALUOp ALUOp ALUOp ALU control block F3 Operation2 F (5 ) F2 F F Operation Operation Operation 5

52 MAIN Control Simple combinational logic (truth tables) Inputs Op5 Op4 Op3 Op2 Op Op R-format Iw sw beq Outputs RegDst ALUSrc MemtoReg RegWrite Mem MemWrite 52 Branch ALUOp ALUOpO

53 Our Simple Control Structure All of the logic is combinational We wait for everything to settle down, and the right thing to be done ALU might not produce right answer right away we use write signals along with clock to determine when to write Cycle time determined by length of the longest path e t State element Combinational logic State element 2 53 Clock cycle

54 Our Simple Control Structure e t State element Combinational logic State element 2 Clock cycle 54

55 Single Cycle Implementation Calculate cycle time assuming negligible delays except: PCSrc memory (2ns), ALU and adders (2ns), register file access M (ns) u U t 4 Add RegWrite Shift left 2 ALU Add result M u x d d d n d e U d M nm e u u ea n U PC address Instruction [3 ] Instruction memory Instruction [25 2] Instruction [2 6] M u Instruction [5 ] x RegDst Instruction [5 ] register data register 2 Write register data 2 Write data Registers 6 Sign 32 extend ALUSrc M u x ALU control Zero ALU ALU result MemWrite Address data Write Data data memory Mem MemtoReg M u x Instruction [5 ] ALUOp 55

56 Single Cycle Implementation PCSrc Add M ux 4 RegWrite Shift left 2 Add ALU result PC address Instruction [3 ] Instruction memory Instruction [25 2] Instruction [2 6] M ux Instruction [5 ] RegDst Instruction [5 ] register register 2 Write register Write data data data 2 Registers 6 Sign 32 extend ALUSrc M ux ALU control Zero ALU ALU result MemWrite Address Write data Data memory Mem data MemtoReg M ux Instruction [5 ] ALUOp 56

57 Where we are headed Single Cycle Problems: what if we had more complicated instruction like floating point? wasteful of area One Solution: use a smaller cycle time have different instructions take different numbers of cycles a multicycle datapath: n n y PC Address Instruction Memory or data Data Instruction register Memory data register Data Register # Registers Register # Register # A B ALU ALUOut 57

58 Where we are headed n PC n y Address Instruction Memory or data Data Instruction register Memory data register Data Register # Registers Register # Register # A B ALU ALUOut 58

59 Multicycle Approach We will be reusing functional units ALU used to compute address and to increment PC Memory used for instruction and data Our control signals will not be determined soley by instruction e.g., what should the ALU do for a subtract instruction? We ll use a finite state machine for control 59