COURSE PLANNING AND EVALUATION

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1 COURSE PLANNING AND EVALUATION By: Pedro Tomás ADVANCED COMPUTER ARCHITECTURES ARQUITECTURAS AVANÇADAS DE COMPUTADORES (AAC)

2 OUTLINE 2 Introduction to computer architectures Course planning Student evaluation method

Example of a modern COMPUTER ARCHITECTURE 3 3rd 3 Generation Mobile Platform for Intel i5 or i7 processors (Q2 2012) GPU RAM Memory Graphics Processing Unit Monitor Hard Disk Drive (HDD) Audio In/out

3 Example of a modern COMPUTER ARCHITECTURE 3 3rd 3 Generation Mobile Platform for Intel i5 or i7 processors (Q2 2012) GPU RAM Memory Graphics Processing Unit Monitor Hard Disk Drive (HDD) Audio In/out Ethernet / Wireless USB Devices Universal Serial Bus ROM Memory Hierarchical interconnections: closest to the CPU faster and dedicated interconnections standardized Interfaces System initialization software

INTERCONNECTION HIERARCHY 4 4-core processor UnCore Core #0 Core L1-I #0 L1-D L2 L3: Last

L1-D Core L1-I #0 L1-D Core L1-I #0 L1-D L2 L2 L2 Coherence Ring Interconnect DDR3 Memory

Interface DDR3 RAM Memory GPU Graphics Processing Unit Input/Output Controller Hub

PCI Express Controller Wireless/Ethernet Controller Solid State Drive (SSD) or Hard Disk

Controller Note: actual architecture depends on the processor model CPU Chip Display

4 INTERCONNECTION HIERARCHY 4 4-core processor UnCore Core #0 Core L1-I #0 L1-D L2 L3: Last Level Cache (LLC) Universal Serial Bus (USB) Controller Core #1 Core #2 Core #3 Core L1-I #0 L1-D Core L1-I #0 L1-D Core L1-I #0 L1-D L2 L2 L2 Coherence Ring Interconnect DDR3 Memory Controller PCIe Controller I/O Interface Quickpath Interconnect (QPI) VGA/HDMI Display Interface DDR3 RAM Memory GPU Graphics Processing Unit Input/Output Controller Hub (Southbridge) CPU Additional general purpose processor (GPP) SATA Controller PCI Controller PCI Express Controller Wireless/Ethernet Controller Solid State Drive (SSD) or Hard Disk Drive (HDD) Additional GPU or FPGA Graphics Core Power and Clock Control Audio Input/Output Controller Note: actual architecture depends on the processor model CPU Chip Display Controller Hierarchical interconnections: closest to the CPU faster and dedicated interconnections standardized Interfaces

5 Simplified software perspective of PROGRAM EXECUTION 5 PROGRAMA... Instrução n ADD R1,R2 Instrução n+1 Instrução n+2 SUB R4,R1 MOV R3,R4 Cada instrução identifica uma operação (SUB) os operandos (R4 e R1) Instrução n+3 DIV R3,R5... Mundo físico Entradas (sensores) Saídas (actuadores) Processador Memória (estado do processador)

6 Simplified hardware perspective of PROGRAM EXECUTION 6 STEP 1: The program counter is used to address the main memory and read (fetch) the instruction to execute Program Counter (PC) Instruction Processador Memória (estado do processador)

7 Simplified hardware perspective of PROGRAM EXECUTION 7 STEP 2: The instruction is identified and decoded (translated) into a set of signals that control the processor Program Counter (PC) Instruction Instruction Decode (ID) Processador Memória (estado do processador)

8 8 Simplified hardware perspective of PROGRAM EXECUTION STEP 3: The instruction operands are fetch from either the registers or the memory Program Counter (PC) Instruction R0 R1 R2 R3 R4 R5 R6 R7 R8... Instruction Decode (ID) Operand Fetch (OF) Processador Memória (estado do processador)

9 9 Simplified hardware perspective of PROGRAM EXECUTION STEP 4: The instruction is executed in the Arithmetic and Logic Unit (ALU) Program Counter (PC) Instruction R0 R1 R2 R3 R4 R5 R6 R7 R8... Instruction Decode (ID) Operand Fetch (OF) Processador Execution (EX) Memória (estado do processador)

10 10 Simplified hardware perspective of PROGRAM EXECUTION STEP 5: The results of the instruction (if any exist) are stored in either the registers or the memory Program Counter (PC) Instruction R0 R1 R2 R3 R4 R5 R6 R7 R8... Instruction Decode (ID) Operand Fetch (OF) Processador Execution (EX) Write Back (WB) Memória (estado do processador)

11 11 Simplified hardware perspective of PROGRAM EXECUTION STEP 6: Change the PC (typically by incrementing it) so that it points to the next instruction Program Counter (PC) Instruction R0 R1 R2 R3 R4 R5 R6 R7 R8... Instruction Decode (ID) Operand Fetch (OF) Processador Execution (EX) Write Back (WB) Increment PC Memória (estado do processador)

CIRCUITS PROGRAMS Hardware/Software view of a COMPUTING ARCHITECTURE 12 Usually addressed in Computer Science courses Usually addressed in Computer Engineering

12 CIRCUITS PROGRAMS Hardware/Software view of a COMPUTING ARCHITECTURE 12 Usually addressed in Computer Science courses Usually addressed in Computer Engineering courses Coordination between different abstraction levels Convergence between technology and programming Requires the project, analysis and evaluation of a processing system

13 COURSE TOPICS single cycle processor 2. pipeline processor The division of the processor in stages allows increased clock frequency. Control Datapath Ctrl Ctrl Dp Dp Dp While each instructions now takes multiple clock cycles to execute, the instruction throughput is higher Each instruction takes one clock cycle to execute 3. solving data & control dependencies Static and dynamic techniques allow to solve or mitigate these dependencies 1. Data forwarding Processor 2. Static scheduling Compiler 3. Dynamic scheduling Processor 4. Branch prediction Processor Ctrl Ctrl Dp Dp Dp The drawback is that multiple data and control dependencies are generated. These dependencies must be resolved for correct operation

14 COURSE TOPICS 14 Ctrl 3. solving data & control dependencies Ctrl Dp Dp Dp 4. multiple instruction issue Ctrl Instruction #0 Ctrl Dp Dp Dp Instruction #1 To increase performance, modern processors can simultaneously issue (and execute) multiple instructions at the same time These processors are usually named superscalar. Processors addressed in this course: MIPS (main focus) Latest generations of: Intel x86 and x86_64 processors ARM processors Other dedicated processors, e.g., GPUs

15 COURSE TOPICS 15 Instruction Set Architectures (ISAs) addressed in this course: RISC Reduced Instruction Set Computer (e.g., MIPS and ARM) CISC Complex Instruction Set Computer (e.g., Intel Processors) VLIW Very Long Instruction Word (e.g., Digital Signal Processors) Stream and Graphics Processors (e.g., GPUs) Processors addressed in this course: MIPS (main focus) Latest generations of: Intel x86 and x86_64 processors ARM processors Other dedicated processors, e.g., GPUs

16 COURSE TOPICS 16 Beyond the processing cores: 5. accessing data Ctrl Instruction #0 Ctrl Dp Dp Dp Instruction #1 Instructions Data Memory Each processing core requires access to the memory to fetch instructions and read/write data. Processor performance has been increasing faster than memory performance. Memory access is a bottleneck in overall performance.

17 COURSE TOPICS accessing data 6. hierarchical memory system Access time: Memory space: Ctrl Instruction #0 Ctrl Dp Dp Dp Instruction #1 Ctrl Instruction #0 Ctrl Dp Dp Dp Instruction #1 Hard Disk Drive (HDD) Instructions Memory Data Instructions Access time: Memory L1 space: Instructions Data L1 Data Each processing core requires access to the memory to fetch instructions and read/write data. L2 Unified L3 Unified RAM Memory

18 COURSE TOPICS virtual memory (support for multitasking) Ctrl Instruction #0 Ctrl Dp Dp Dp Instruction #1 To guarantee multitasking, one has to virtualize the memory space for each process The virtual memory decreases system performance Instructions Data Caching of virtual memory addresses allows to significantly reduce the performance penalty of virtual memory systems. Virtual Memory Space for PROCESS A Virtual Memory Space for PROCESS B Virtual Memory Space for PROCESS C

19 COURSE TOPICS 19 Can we still improve performance? Yes Exploring fine-grained parallelism: Vector processors ISA extensions: MMX, SSE, SSE2, SSE3, AVX Exploring coarse-grained parallelism Multicore systems Exploring thread-level parallelism Stream and Graphics processors

20 COURSE ORGANIZATION: THEORETICAL CLASSES 20 RISC Processors Pipelining Identification of data and control dependencies Solving data and control dependencies Data forwarding paths in the processor Compiler based techniques VLIW processors Dynamic Techniques: Scoreboard and Tomasulo Branch Prediction Superscalar and CISC processors Midterm test 1 April 15

21 COURSE ORGANIZATION: THEORETICAL CLASSES 21 Memory Hierarchy Cache Memories Virtual Memory Cache + Virtual Memory Parallel Architectures Vector architectures Single Instruction Multiple Data (SIMD) instructions Multicore Systems Graphics Processing Units Midterm test 2 June 8 1 st Exam date June 8 2 nd Exam date June 27

22 COURSE ORGANIZATION: LABORATORY Multi-cycle processor 2. Pipeline processor 3. Parallelism using one of the following choices: a) Vector instructions (SIMD: Single Instruction Multiple Data) b) Multicore processing (MIMD: Multiple Instruction Multiple Data) c) General Purpose Processing on Graphics Processing Units (GPGPU) (not yet guaranteed) Groups of 3 students, exceptionally 2. Project 1 March Xilinx ISE (any version) VHDL/Verilog, C/C++ Project 2 April 28-May 1 Project 3 May 23-27

23 COURSE ORGANIZATION: EVALUATION 23 Student grading is performed as follows: Theoretical component (T) T = max( mid term test average ; exam ) Practical component (P) P avg = average( Project 1 ; Project 2 ; Project 3 ) Grade subject to oral discussion at the end of the semester Final Grade (F) Grading is subject to completion of all project assignments (P1, P2 and P3); failure to deliver any of the assignments results in a grade of N/A (not evaluated) Minimum grade for either the theoretical (T) and the practical (P) components is 9.5 IF T 9.5 and P 9.5 then the final grade is computed as: F = 0.5 T P avg

24 COURSE ORGANIZATION: BIBLIOGRAPHY 24 RECOMMENDED: Computer Architecture: A Quantitative Approach 5 th edition, John L. Hennessy and David A. Patterson, Morgan Kaufmann, 2011 ALTERNATIVE/ADDITIONAL: Computer Architecture: A Quantitative Approach 4 th edition, John L. Hennessy and David A. Patterson, Morgan Kaufmann, 2006 Computer Organization and Design: the Hardware/Software Interface 4 th edition, David A. Patterson and L. Hennessy, Morgan Kaufmann, 2008

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